JPH0415859U - - Google Patents
Info
- Publication number
- JPH0415859U JPH0415859U JP1990056759U JP5675990U JPH0415859U JP H0415859 U JPH0415859 U JP H0415859U JP 1990056759 U JP1990056759 U JP 1990056759U JP 5675990 U JP5675990 U JP 5675990U JP H0415859 U JPH0415859 U JP H0415859U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- built
- integrated circuit
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａは本考案の第１実施例のモールド樹脂
を除いた透視平面図、第１図ｂはＡ−Ａ′線断面
図、第２図ａは第２実施例のセラミツクパツケー
ジを除いた創始平面図、第２図ｂはＢ−Ｂ′線断
面図である。 １，１１……チツプコンデンサ、２……ＩＣチ
ツプ、３……ベースリボン、４……プラスチツク
、６，１５……電源端子リード、７……接地端子
リード、１３……マウント基板部（接地）。
を除いた透視平面図、第１図ｂはＡ−Ａ′線断面
図、第２図ａは第２実施例のセラミツクパツケー
ジを除いた創始平面図、第２図ｂはＢ−Ｂ′線断
面図である。 １，１１……チツプコンデンサ、２……ＩＣチ
ツプ、３……ベースリボン、４……プラスチツク
、６，１５……電源端子リード、７……接地端子
リード、１３……マウント基板部（接地）。
Claims (1)
- パツケージ内に、ＩＣチツプの電源ラインと接
地ライン間に接続されたチツプコンデンサを内蔵
したことを特徴とする半導体集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990056759U JPH0415859U (ja) | 1990-05-30 | 1990-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990056759U JPH0415859U (ja) | 1990-05-30 | 1990-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415859U true JPH0415859U (ja) | 1992-02-07 |
Family
ID=31580873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990056759U Pending JPH0415859U (ja) | 1990-05-30 | 1990-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415859U (ja) |
-
1990
- 1990-05-30 JP JP1990056759U patent/JPH0415859U/ja active Pending