JPH04154155A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04154155A
JPH04154155A JP2277821A JP27782190A JPH04154155A JP H04154155 A JPH04154155 A JP H04154155A JP 2277821 A JP2277821 A JP 2277821A JP 27782190 A JP27782190 A JP 27782190A JP H04154155 A JPH04154155 A JP H04154155A
Authority
JP
Japan
Prior art keywords
island
paste
resin
conductive paste
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2277821A
Other languages
Japanese (ja)
Inventor
Kazuhiko Muto
和彦 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2277821A priority Critical patent/JPH04154155A/en
Publication of JPH04154155A publication Critical patent/JPH04154155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To prevent flow of paste on an island and prevent electrical short- circuiting, generation of cracks, etc., by forming a protruding bank or a groove line which sections larger than a contour of a chip on an upper surface of the island. CONSTITUTION:A conductive paste 3 is applied on an island at an inside region which is surrounded by a groove line 2 which is formed on an upper surface of an island 1a. When a semiconductor chip 4 is placed on this paste 3 and is lightly pressed, an extra paste is drop into the groove line 2 and is raised but does not flow to an edge of the island, thus preventing electrical short- circuiting with a lead 1a, air bubbles from being generated when molding a resin 6, and cracks from being generated.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、樹脂封止型の半導体装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resin-sealed semiconductor device.

［従来の技術］ この種の半導体装置では、半導体チップをアイランドに
固定するために導電性のペーストを使用している。即ち
、第５図に示すように、平坦なアイランド１ａ上に導電
性ペースト３を塗布し、そのうえに半導体チップ４を軽
（押し付けて、密着するのである。そして、上記半導体
チップ４とリード１ｂとの間をリードワイヤ５で結び、
上記リード１ｂの外端を残して、これらを非導電性の樹
脂６でモールドするのである。[Prior Art] This type of semiconductor device uses a conductive paste to fix a semiconductor chip to an island. That is, as shown in FIG. 5, a conductive paste 3 is applied onto a flat island 1a, and a semiconductor chip 4 is lightly pressed onto the conductive paste 3 to bring them into close contact. Connect the gap with lead wire 5,
These are molded with non-conductive resin 6, leaving the outer ends of the leads 1b.

［発明が解決しようとする課題］ しかしながら、上記半導体装置では、アイランド上に塗
布された導電性ペーストの量が多いと、半導体チップを
押し付けるときに、余分な導電性ペーストが上記アイラ
ンドと半導体チップとの間隙から周囲に押し出され、上
記アイランドの周囲へはみ出すことがある。その結果、
上記導電性ペーストが上記リードに接触し、電気的にア
イランドとリードとを導通してしまい、ＩＣなどが誤動
作する原因になったり、あるいはその破壊をもたらす。[Problems to be Solved by the Invention] However, in the semiconductor device described above, if the amount of conductive paste applied on the island is large, when the semiconductor chip is pressed, the excess conductive paste will come between the island and the semiconductor chip. It may be pushed out from the gap to the periphery and protrude to the periphery of the island. the result,
The conductive paste contacts the leads and electrically connects the islands to the leads, causing malfunction or destruction of the IC.

また、樹脂のモールドに際して、はみ出した同電性ペー
ストが、符号８で図示するように、気泡を持ち、そこが
原因してクラックを誘発するなどの欠点が有る。Furthermore, when molding the resin, the protruding isoelectric paste has bubbles, as shown by reference numeral 8, which causes cracks.

［発明の目的］ 本発明は上記事情に基いてなされたもので、アイランド
に導電性ペーストの拡がりを阻止する手段を設けること
で、上記欠点を解消できる半導体装置を提供しようとす
るものである。[Object of the Invention] The present invention has been made based on the above-mentioned circumstances, and aims to provide a semiconductor device that can eliminate the above-mentioned drawbacks by providing means for preventing the spread of conductive paste on the island.

［課題を解決するための手段］ このため、本発明ではアイランドに導電性ペーストを介
して半導体チップを装着した樹脂封止型の半導体装置に
おいて、上記アイランドの上面には上記チップの輪郭よ
り太き（区画する突堤あるいは溝条が形成され、上記ア
イランド上での上記ペーストの流れを阻止するように構
成している。[Means for Solving the Problems] Therefore, in the present invention, in a resin-sealed semiconductor device in which a semiconductor chip is attached to an island through a conductive paste, the upper surface of the island has a shape that is thicker than the outline of the chip. (A dividing jetty or groove is formed to prevent the paste from flowing on the island.

［作　用］ 従って、余分のペーストは上記突堤あるいは溝条で、流
れを阻止されて、少なくともアイランドの縁に流れるこ
とがなく、リードとの電気的短絡を防止でき、また、樹
脂のモールドに際して、気泡の発生によるクラックなど
を回避できる。[Function] Therefore, the excess paste is prevented from flowing by the above-mentioned jetty or groove, and at least does not flow to the edge of the island, thereby preventing electrical short circuit with the lead. Cracks caused by the generation of air bubbles can be avoided.

［実施例］ 以下、本発明を図示の実施例にもとずいて具体的に説明
する。なお、従来と同一部分には同一符号を付して説明
を省略する。第１図及び第２図において、符号２は半導
体チップ４の輪郭を囲む様にアイランド１ａの上面に形
成した溝条であり、上記溝条２で囲まれた内側の領域で
、上記アイランド上には導電性ペースト３が塗布される
。[Examples] Hereinafter, the present invention will be specifically described based on illustrated examples. It should be noted that the same parts as those in the prior art are denoted by the same reference numerals and the description thereof will be omitted. In FIGS. 1 and 2, reference numeral 2 denotes a groove formed on the upper surface of the island 1a so as to surround the outline of the semiconductor chip 4; conductive paste 3 is applied.

従って、このペースト３上に半導体チップ４を載せて、
軽く押し付けると、余分のペーストは上記溝条２内に落
ち込み、盛り上がるが、上記アイランドの縁には流れな
い。このため、リード１ａとの電気的短絡は起こらない
。また、樹脂６のモールドに際しても、気泡を発生せず
、クラックの原因をもたらさない。Therefore, by placing the semiconductor chip 4 on this paste 3,
When pressed lightly, excess paste sinks into the grooves 2 and rises, but does not flow to the edges of the islands. Therefore, no electrical short circuit with the lead 1a occurs. Also, when molding the resin 6, no bubbles are generated and no cracks are caused.

なお、上記実施例では、溝条２はアイランド１ａ及びリ
ード１ｂを製造する際に、エツチングにより同時に加工
することができるので、余計な工程を追加する必要がな
い。In the above embodiment, the groove 2 can be etched at the same time when the island 1a and the lead 1b are manufactured, so there is no need to add any extra steps.

第３図及び第４図は本発明の他の実施例で、ここでは、
溝条２の代りに、突堤７を上記アイランド１ａの上に設
けている。この場合も、上記突堤７で、導電性ペースト
３の流れを阻止できるから、先の実施例同様な効果を得
ることができる。FIGS. 3 and 4 show another embodiment of the invention, in which:
Instead of the grooves 2, a jetty 7 is provided on the island 1a. In this case as well, the flow of the conductive paste 3 can be blocked by the jetty 7, so that the same effect as in the previous embodiment can be obtained.

特に、この実施例では上記突堤を設けているので、樹脂
モールドに際しての樹脂収縮による応力が半導体チップ
に過大にかかるのを分散、緩和できる効果がある。因に
、−Ｍにはこの種、樹脂封止型の半導体装置では樹脂の
収縮により、内部に過大の応力を発生し、半導体チップ
と樹脂との間に剥離を生じたり、上記チップ上のパッシ
ベイション膜にクラックを生じる可能性があるのである
。In particular, this embodiment has the above-mentioned jetty, which has the effect of dispersing and alleviating excessive stress applied to the semiconductor chip due to resin contraction during resin molding. Incidentally, in -M, in this type of resin-sealed semiconductor device, excessive stress is generated internally due to contraction of the resin, causing peeling between the semiconductor chip and the resin, and damage to the passivation on the chip. This may cause cracks in the vation membrane.

［発明の効果］ 本発明は、以上詳述したようになり、アイランドに導電
性ペーストを介して半導体チップを取付けるとき、上記
ペーストの拡がりを阻止できるので、リードに対する電
気的短絡や、その他の原因による不良品の発生を少なく
でき、歩留り及び品質を向上させる効果がある。[Effects of the Invention] As described in detail above, the present invention can prevent the spread of the paste when attaching a semiconductor chip to an island via a conductive paste, thereby preventing electrical short circuits to the leads and other causes. This has the effect of reducing the occurrence of defective products due to oxidation and improving yield and quality.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を説明するための縦断側面図
、第２図はそのアイランドの斜視図、第３図及び第４図
は他の実施例の縦断側面図及びそのアイランドの斜視図
、第５図は従来例の縦断側面図である。 １ａ・・・アイランド １ｂ・・・リード ２・・・溝条 ３・・・導電性ペースト ４・・・半導体チップ ５・・・リードワイヤ ６・・・樹脂 ７・・・突堤 代理人　　弁理士　　山　下　積　平 第１ 図 第２ 図 第３図 第４図 第 図Fig. 1 is a vertical side view for explaining one embodiment of the present invention, Fig. 2 is a perspective view of the island, and Figs. 3 and 4 are longitudinal side views of other embodiments and perspective views of the island. FIG. 5 is a longitudinal sectional side view of a conventional example. 1a... Island 1b... Lead 2... Groove 3... Conductive paste 4... Semiconductor chip 5... Lead wire 6... Resin 7... Jetty agent Patent attorney Yama Lower Product Flat 1 Figure 2 Figure 3 Figure 4 Figure

Claims (1)

【特許請求の範囲】[Claims] 　アイランドに導電性ペーストを介して半導体チップを
装着した樹脂封止型の半導体装置において、上記アイラ
ンドの上面には上記チップの輪郭より大きく区画する突
堤あるいは溝条が形成され、上記アイランド上での上記
ペーストの流れを阻止するように構成していることを特
徴とする半導体装置。In a resin-sealed semiconductor device in which a semiconductor chip is attached to an island via a conductive paste, a jetty or a groove is formed on the top surface of the island to define the area larger than the outline of the chip. A semiconductor device characterized by being configured to prevent the flow of paste.
JP2277821A 1990-10-18 1990-10-18 Semiconductor device Pending JPH04154155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2277821A JPH04154155A (en) 1990-10-18 1990-10-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2277821A JPH04154155A (en) 1990-10-18 1990-10-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04154155A true JPH04154155A (en) 1992-05-27

Family

ID=17588731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2277821A Pending JPH04154155A (en) 1990-10-18 1990-10-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04154155A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007134394A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2008124116A (en) * 2006-11-09 2008-05-29 Denso Corp Semiconductor device
JP2014212254A (en) * 2013-04-19 2014-11-13 株式会社デンソー Semiconductor device and semiconductor device manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007134394A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP4738983B2 (en) * 2005-11-08 2011-08-03 ローム株式会社 Semiconductor device
JP2008124116A (en) * 2006-11-09 2008-05-29 Denso Corp Semiconductor device
JP2014212254A (en) * 2013-04-19 2014-11-13 株式会社デンソー Semiconductor device and semiconductor device manufacturing method

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