JPH041507B2 - - Google Patents
Info
- Publication number
- JPH041507B2 JPH041507B2 JP4340483A JP4340483A JPH041507B2 JP H041507 B2 JPH041507 B2 JP H041507B2 JP 4340483 A JP4340483 A JP 4340483A JP 4340483 A JP4340483 A JP 4340483A JP H041507 B2 JPH041507 B2 JP H041507B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- defect
- protective film
- defective
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 230000007547 defect Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000002950 deficient Effects 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は例えばゲートターンオフサイリスタ
（以下GTOと略称する）、トランジスタ、静電誘
導サイリスタなど電流をしや断する機能をもち、
半導体基板の主表面に設けられた複数個に分割さ
れた電極のうち、好ましくない電極を除去する半
導体装置の製造方法に関する。[Detailed Description of the Invention] [Technical Field to Which the Invention Pertains] The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as GTO), a transistor, a static induction thyristor, etc., which has a function of cutting off current,
The present invention relates to a method for manufacturing a semiconductor device in which undesirable electrodes are removed from among a plurality of divided electrodes provided on the main surface of a semiconductor substrate.
第１図に例えば従来のGTOの素子構造の部分
的な断面図を示す。第１図においてＰ型エミツタ
pE、ｎ型ベースnB、ｐ型ベースpB、ｎ型エミツタ
nEの４層からなるシリコン半導体基板１にはpB層
上にゲート電極２とnE層上にカソード電極３とが
設けられ、さらにカソード電極３の上に接触電極
板４が当接するように置かれている。このときゲ
ート電極２とカソード電極３とが接触電極板４を
介して短絡することのないようシリコン基板１の
主表面に高低をつけて、それぞれゲート電極２と
カソード電極３が第１図のごとく配置される。
FIG. 1 shows, for example, a partial cross-sectional view of the element structure of a conventional GTO. In Figure 1, the P-type emitter
p E , n-type base n B , p-type base p B , n-type emitter
A silicon semiconductor substrate 1 consisting of four layers of nE is provided with a gate electrode 2 on the pB layer and a cathode electrode 3 on the nE layer, and a contact electrode plate 4 is provided on the cathode electrode 3. It is placed in At this time, in order to prevent the gate electrode 2 and the cathode electrode 3 from short-circuiting through the contact electrode plate 4, heights are provided on the main surface of the silicon substrate 1. Placed.
このような構造はカソード電極３の下のnE層に
例えば符号Ａで示す欠陥があつた場合は、しや断
信号が欠陥Ａを通つてカソード電極３からゲート
電極２へ流れ、電流しや断が有効に行われなくな
るので、そのようなときは、欠陥ＡのあるnE層に
は主電流を流さないようにするために、欠陥Ａを
もつnE層上のカソード電極（以下不良電極３ａと
略称する）をバイトで切削除去する方法が１つの
対策として特開昭56−51867号公報に記載されて
いる。第２図はシリコン基板１上の不良電極３ａ
をバイト５で機械的に切削する状況を示したもの
である。 In such a structure, if there is a defect indicated by the symbol A in the nE layer below the cathode electrode 3, a failure signal will flow from the cathode electrode 3 to the gate electrode 2 through the defect A, and the current will be suppressed. In such a case, in order to prevent the main current from flowing through the nE layer with the defect A, the cathode electrode (hereinafter referred to as the defective electrode) on the nE layer with the defect A must be 3a) using a cutting tool is described in Japanese Patent Laid-Open No. 56-51867 as one countermeasure. Figure 2 shows a defective electrode 3a on a silicon substrate 1.
This figure shows the situation in which the material is mechanically cut with the cutting tool 5.
しかしながら、この方法は、複雑なまたは微少
なエミツタ形状では、周囲の正常なカソード電極
まで損傷を与え、ひいては半導体装置自体を不良
にしてしまうといる危険性を伴つており、特定の
不良電極だけを、他に影響を及ぼすことなく、し
かも切削残りのないように確実に除去することは
かなり困難であるという欠点をもつている。 However, if the emitter shape is complex or minute, this method carries the risk of damaging surrounding normal cathode electrodes and even making the semiconductor device itself defective. However, it has the disadvantage that it is quite difficult to remove it reliably without affecting other parts and leaving no cutting residue.
本発明の目的は、上述の欠点を除去し、不良電
極だけを確実に取除く方法を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method that eliminates the above-mentioned drawbacks and reliably removes only defective electrodes.
本発明は半導体装置表面全体を保護膜で覆い、
不良電極上の保護膜のみを剥離し、露出した電極
をエツチングし除去することにより達成される。
The present invention covers the entire surface of a semiconductor device with a protective film,
This is achieved by peeling off only the protective film on the defective electrode and etching and removing the exposed electrode.
第３図〜第６図は本発明による方法の手順を示
したものである。
3 to 6 show the steps of the method according to the invention.
まず第３図に示すように、予め不良電極３ａに
は電気的測定によりチエツクしマークが付されて
いる半導体基板１の主表面全体に密着性の良好な
耐薬品性保護膜６を均一に塗布する。この耐薬品
性保護膜としては、例えばフオトレジスト、ポリ
イミド樹脂などが用いられ、塗布後は露光または
加熱により保護膜を硬化させる。なお不良電極に
付すマークは図示してない。 First, as shown in FIG. 3, a chemical-resistant protective film 6 with good adhesion is uniformly applied to the entire main surface of the semiconductor substrate 1, which has been checked and marked by electrical measurement on the defective electrodes 3a in advance. do. As this chemical-resistant protective film, for example, photoresist, polyimide resin, etc. are used, and after coating, the protective film is cured by exposure to light or heating. Note that marks attached to defective electrodes are not shown.
次に第４図に示すようにマークの付されている
不良電極３ａ上の保護膜の部分だけに刃物で傷を
入れてその大部分を除去し、除去した部分の下地
の不良電極３ａを露出させる。このとき正常な電
極３は全て保護膜６で被覆されており、除去され
るべき不良電極３ａのみが窓明けされた状態とな
る。あるいは不良電極３ａ上の保護膜は大きく開
口することなく、刃物で下地の不良電極３ａに達
する傷をつける程度でもよい。続いてこの状態の
半導体基板１を第５図のごとく治具７に乗せたま
ま、エツチング液８を収容した容器９の中に浸漬
する。かくして所定時間後にこれらを容器９から
引揚げると、不良電極３ａの個所のみがエツチン
グ除去されているので、最後に保護膜６を取去れ
ば第６図に示す状態となり、本発明の処理工程を
完了する。 Next, as shown in Fig. 4, only the portion of the protective film on the marked defective electrode 3a is scratched with a knife and most of it is removed, exposing the defective electrode 3a underlying the removed portion. let At this time, all the normal electrodes 3 are covered with the protective film 6, and only the defective electrode 3a to be removed is exposed. Alternatively, the protective film on the defective electrode 3a may be scratched with a knife to the extent that it reaches the underlying defective electrode 3a without having a large opening. Subsequently, the semiconductor substrate 1 in this state is immersed in a container 9 containing an etching solution 8 while being placed on a jig 7 as shown in FIG. When these are pulled out of the container 9 after a predetermined period of time, only the defective electrode 3a has been etched away, so when the protective film 6 is finally removed, the state shown in FIG. 6 is obtained, and the treatment process of the present invention can be carried out. Complete.
なお不良電極２ａ上の保護膜６だけを除去する
方法としては、フオトエツチング法を利用するこ
とも考えられるが、実際上は除去すべき不良電極
は不特定個所に存在するから、フオトマスクを製
作することが甚だ非能率的であつて、フオトエツ
チグ法はこの場合は適切でない。 Note that as a method of removing only the protective film 6 on the defective electrode 2a, it is possible to use a photoetching method, but in practice, since the defective electrode to be removed exists in unspecified locations, a photomask is manufactured. This is extremely inefficient and the photo-etching method is not appropriate in this case.
以上説明したように、本発明の方法によれば、
正常な電極は密着性の良好な保護膜で被覆されて
おり、不良電極のみが確実にエツチング除去され
るので、正常な電極までも損傷を与える危険性は
全くなく、不良電極の一部が残るような不完全さ
もない。また電極形状の如何にかかわらず、複数
個の不良電極が存在しても、除去過程のエツチン
グは一度の処理で済ませることができ、しかもエ
ツチング容器の大きさを適切に選ぶことにより、
同時に多数個の半導体装置を浸漬することができ
るので処理効率が極めて高いなどの多くの利点を
もつている。
As explained above, according to the method of the present invention,
The normal electrodes are covered with a protective film with good adhesion, and only the defective electrodes are reliably etched away, so there is no risk of damaging the normal electrodes, and some of the defective electrodes remain. There is no such imperfection. In addition, regardless of the shape of the electrode, even if there are multiple defective electrodes, the etching process can be completed in a single process, and by choosing the size of the etching container appropriately,
It has many advantages, such as extremely high processing efficiency because a large number of semiconductor devices can be immersed at the same time.
第１図はGTOの部分断面図、第２図は不良電
極の切削状況を示す概念図、第３図〜第５図は本
発明による保護膜の着脱手順を示す工程図、第６
図は完成状態を示す断面図である。
１…半導体基板、２…ゲート電極、３…カソー
ド電極、３ａ…不良電極、４…接触電極板、５…
バイト、６…保護膜、７…治具、８…エツチング
液、９…容器。
Figure 1 is a partial sectional view of the GTO, Figure 2 is a conceptual diagram showing the cutting situation of a defective electrode, Figures 3 to 5 are process diagrams showing the procedure for attaching and removing the protective film according to the present invention, and Figure 6
The figure is a sectional view showing the completed state. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate electrode, 3... Cathode electrode, 3a... Defective electrode, 4... Contact electrode plate, 5...
Bit, 6... Protective film, 7... Jig, 8... Etching liquid, 9... Container.
Claims (1)
この最上層に互に独立して設けられた複数個に分
割された領域とを備える半導体および該各領域に
設けた電極膜とを有する半導体装置を製造するに
あたり、前記分割された領域のうち、欠陥を有す
る領域に属する電極膜を選択除去して、前記欠陥
を有する領域には、電流の導通をなくするための
方法であつて、前記半導体基体の主表面の全面に
わたつて保護膜を被着した後、前記欠陥を有する
領域に属する電極膜上のみの保護膜に電極膜に達
する傷をつけて、この半導体基体を半導体のエツ
チング液に浸漬することにより、前記欠陥を有す
る領域に属する電極膜を溶解除去することを特徴
とする半導体装置の製造方法。1 at least three layers of alternating conductivity types;
In manufacturing a semiconductor device having a semiconductor including a plurality of divided regions provided independently on the uppermost layer and an electrode film provided in each of the regions, among the divided regions, A method for selectively removing an electrode film belonging to a region having a defect to eliminate current conduction in the region having a defect, the method includes covering the entire main surface of the semiconductor substrate with a protective film. After the semiconductor substrate is etched, a scratch is made on the protective film only on the electrode film belonging to the region having the defect, and by immersing the semiconductor substrate in a semiconductor etching solution, the electrode belonging to the region having the defect is removed. A method for manufacturing a semiconductor device, characterized by dissolving and removing a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340483A JPS59169175A (en) | 1983-03-16 | 1983-03-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340483A JPS59169175A (en) | 1983-03-16 | 1983-03-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59169175A JPS59169175A (en) | 1984-09-25 |
| JPH041507B2 true JPH041507B2 (en) | 1992-01-13 |
Family
ID=12662822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4340483A Granted JPS59169175A (en) | 1983-03-16 | 1983-03-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59169175A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112672525B (en) * | 2020-11-12 | 2022-05-17 | 广州广合科技股份有限公司 | Treatment method for incomplete etching in PCB negative film process |
-
1983
- 1983-03-16 JP JP4340483A patent/JPS59169175A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59169175A (en) | 1984-09-25 |
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