JPS59169175A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59169175A
JPS59169175A JP4340483A JP4340483A JPS59169175A JP S59169175 A JPS59169175 A JP S59169175A JP 4340483 A JP4340483 A JP 4340483A JP 4340483 A JP4340483 A JP 4340483A JP S59169175 A JPS59169175 A JP S59169175A
Authority
JP
Japan
Prior art keywords
electrode
protective film
defect
defective
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4340483A
Other languages
Japanese (ja)
Other versions
JPH041507B2 (en
Inventor
Katsuhiro Endo
遠藤 勝弘
Tetsuya Mizuno
水野 鉄哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Corporate Research and Development Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Corporate Research and Development Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4340483A priority Critical patent/JPS59169175A/en
Publication of JPS59169175A publication Critical patent/JPS59169175A/en
Publication of JPH041507B2 publication Critical patent/JPH041507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To effectively remove only an improper electrode without affecting the influence to the other by covering the entire surface of a semiconductor device with a protective film, exfoliating only the film, and etching and removing the exposed electrode. CONSTITUTION:A medicine resistant protective film 6 having good sealability is uniformly coated on the overall main surface of a semiconductor substrate 1. Photoresist or polyimide resin is used as the protective film, it is cured by exposure or heating after coating. A damage is formed by a cutter only on the part of the protective film on the improper electrode 3a, removed, and the electrode 3a is exposed. Only the position of the electrode 3a is etched, and removed to remove the film 6. No possibility of damaging the normal electrode occurs, and no partial remainder of the improper electrode incompletely takes place.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は例えばゲートターンオフサイリスタ(以下GT
Oと略称する)、トランジスタ、静電誘導サイリスクな
ど電流をしゃ断する機能をもち、半導体基板の主表面に
設けられた複数個に分割された電極のうち、好ましくな
い電極を除去する半導体装置の製造方法に関する。
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a gate turn-off thyristor (hereinafter referred to as GT), for example.
Manufacture of semiconductor devices that have the function of cutting off current, such as transistors, electrostatic induction silices (abbreviated as O), and remove undesirable electrodes from among the plurality of divided electrodes provided on the main surface of the semiconductor substrate. Regarding the method.

〔従来技術おその問題点〕[Prior art and its problems]

第1図に例えば従来のGTOの素子構造の部分的な断面
図を示す。第1図においてP型エミッタ(pE)+n型
ベース(nB)、p型ベース(pB)+n型エミッタ・
(no)の4層からなるシリコン早導体基板lにはpB
層上にゲート電極2とnE層上にカソード電極3とが設
けられ、さらにカソード電極3の上に接触電極板4が当
接するように置かれている。このときゲート電極2とカ
ソード電極3とが接触電極板4を介して短絡することが
ないようシリコン基板1の主表面に高低をつけて、それ
ぞれゲート電極2さカソード電極3が第1図のときく配
置される。
FIG. 1 shows, for example, a partial cross-sectional view of the element structure of a conventional GTO. In Figure 1, P type emitter (pE) + n type base (nB), p type base (pB) + n type emitter,
The silicon fast conductor substrate l consisting of four layers (no) has pB
A gate electrode 2 is provided on the layer, and a cathode electrode 3 is provided on the nE layer, and a contact electrode plate 4 is placed on the cathode electrode 3 so as to be in contact therewith. At this time, in order to prevent the gate electrode 2 and the cathode electrode 3 from short-circuiting through the contact electrode plate 4, heights are provided on the main surface of the silicon substrate 1. It is arranged very well.

このような構造ではカソード電極3の下のn2層に例え
ば符号Aで示す欠陥があった場合は、しゃ断信号が欠陥
Aを通ってカソード電極3からゲート電極2へ流れ、電
流しゃ断が有効に行われなくなるので、そのようなとき
は、欠陥AのあるnF、層には主電流を流さないように
するために、欠陥AをもつnF、層上のカソード電極(
以下不良電極3a(!:略称する)をバイトで切削除去
する方法が1つの対策として特開昭56−51867号
公報に記載されている。第2図はシリコン基板l上の不
良電極3aをバイト5で機械的に切削する状況を示した
ものである。
In such a structure, if there is a defect indicated by the symbol A in the n2 layer below the cathode electrode 3, the cutoff signal will flow from the cathode electrode 3 to the gate electrode 2 through the defect A, and the current cutoff will not be performed effectively. In such a case, in order to prevent the main current from flowing through the nF layer with defect A, the cathode electrode (
As one countermeasure, a method of cutting and removing the defective electrode 3a (!: abbreviated as below) with a cutting tool is described in Japanese Patent Laid-Open No. 56-51867. FIG. 2 shows a situation in which a defective electrode 3a on a silicon substrate 1 is mechanically cut with a cutting tool 5. As shown in FIG.

しかしながら、この方法は、複雑なまたは微少なエミッ
タ形状では、周囲の正常なカソード電極才で損傷を与え
、ひいては半導体装置自体を不良にしてしまうという危
険性を伴っており、特定の不良電極だけを、他に影響を
及ぼすことなく、しかも切削残りのないように確実に除
去することはかなり困難であるという欠点をもっている
However, if the emitter shape is complex or minute, this method carries the risk of damaging the surrounding normal cathode electrodes and even making the semiconductor device itself defective. However, it has the disadvantage that it is quite difficult to remove it reliably without affecting other parts and leaving no cutting residue.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述の欠点を除去し、不良電極だけを
確実に取除く方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method that eliminates the above-mentioned drawbacks and reliably removes only defective electrodes.

〔発明の要点〕[Key points of the invention]

本発明は半導体装置表面全体を保護膜で覆い、不良電極
上の保護膜のみを剥離し、露出した電極をエツチングし
除去するこきにより達成される。
The present invention is achieved by covering the entire surface of a semiconductor device with a protective film, peeling off only the protective film on the defective electrode, and etching and removing the exposed electrode.

〔発明の実施例〕[Embodiments of the invention]

第3図〜第6図は本発明による方法の手順を示したもの
である。
3 to 6 show the steps of the method according to the invention.

まず第3図に示すように、予め不良電極3aには電気的
測定によりチェックしマークが付されている半導体基板
1の主表面全体に密着性の良好な耐薬品性保4Iを均一
に塗布する。この耐薬品性保護膜としては、例えばフォ
トレジスト、ポリイミド樹脂などが用いられ、塗布後は
露光または加熱により保称膜を硬化させる。なお不良電
極に付すマークは図示してない。
First, as shown in FIG. 3, a chemical-resistant adhesive 4I with good adhesion is uniformly applied to the entire main surface of the semiconductor substrate 1, which has been previously checked and marked by electrical measurement on the defective electrodes 3a. . As this chemical-resistant protective film, for example, photoresist, polyimide resin, etc. are used, and after coating, the anomalous film is cured by exposure to light or heating. Note that marks attached to defective electrodes are not shown.

次に第4図に示すようにマークの付されている不良電極
3a上の保護膜の部分だけ番こ刃物で傷を入れてその大
部分を除去し、除去した部分の下地の不良電極3aを露
出させる。このとき正常な電極3は全て保護膜6で被覆
されており、除去されるべき不良電極3aのみが窓明け
された状態となる。あるいは不良電極3a上の保護膜は
大きく開口することなく、刃物で下地の不良電極3aに
達する傷をつける程度でもよい。続いてこの状態の半導
体基板1を第5図のととく治具7に乗せたit、エツチ
ング液8を収容した容器9の中に浸漬する。かくして所
定時間後にこれらを容器9から引揚げると、不良電極3
aの個所のみがエツチング除去されているので、最後に
保護膜6を取去れば第6図に示す状態きなり、本発明の
処理工程を完了する。
Next, as shown in Fig. 4, only the marked portion of the protective film on the defective electrode 3a is scratched with a saw blade and most of it is removed, and the defective electrode 3a on the base of the removed portion is removed. expose. At this time, all the normal electrodes 3 are covered with the protective film 6, and only the defective electrode 3a to be removed is exposed. Alternatively, the protective film on the defective electrode 3a may be scratched with a knife to the extent that it reaches the underlying defective electrode 3a without having a large opening. Subsequently, the semiconductor substrate 1 in this state is placed on the etching jig 7 shown in FIG. 5 and immersed in a container 9 containing an etching solution 8. When these are pulled out of the container 9 after a predetermined time, the defective electrodes 3
Since only the portion a has been removed by etching, when the protective film 6 is finally removed, the state shown in FIG. 6 is obtained, and the process of the present invention is completed.

なお不良電極2a上の保護膜6たけを除去する方法とし
ては、フォトエツチング法を利用することも考えられる
が、実際上は除去すべき不良電極は不特定個所に存在す
るから、フォトマスクを製作することが甚だ非能率的で
あって、フォトエッチグ法はこの場合は適切でない。
As a method for removing the protective film 6 on the defective electrode 2a, it is possible to use a photoetching method, but in practice, since the defective electrode to be removed exists in unspecified locations, it is necessary to fabricate a photomask. Photoetching is not suitable in this case as it is extremely inefficient to do so.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の方法によれば、正常な電
極は密着性の良好な保護膜で被覆されており、不良電極
のみが確実にエツチング除去されるので、正常な電極ま
でも損傷を与える危険性は全くなく、不良電極の一部が
残るような不完全さもない。また電極形状の如何にかか
わらず、複数個の不良電極が存在しても、除去過程のエ
ツチングは一度の処理で済ませることができ、しかもエ
ツチング容器の大きさを適切に選ぶことにより、同時に
多数個の半導体装置を浸漬することができるので処理効
率が極めて高いなどの多くの利点をもっている。
As explained above, according to the method of the present invention, normal electrodes are covered with a protective film with good adhesion, and only defective electrodes are reliably etched away, so even normal electrodes are not damaged. There is no risk of exposure, and there are no imperfections that could leave part of the defective electrode. In addition, regardless of the shape of the electrode, even if there are multiple defective electrodes, the etching process can be completed in one process, and by selecting the appropriate size of the etching container, a large number of defective electrodes can be removed at the same time. It has many advantages, such as extremely high processing efficiency because it can immerse many semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はGTOの部分断面図、第2図は不良電極の切削
状況を示す概念図、第3図〜第5図は本発明による保護
膜の着脱手順を示す工程図、第6図は完成状態を示す断
面図である。 1・・・半導体基板、2・・・ゲート電極、3・・・カ
ソード電極、3a・・・不良電極、4・・・接触電極板
、5・・・バイト、6・・・保護膜、7・・・治具、8
・・パエッチング液、9・・・容器。 第1図 第2図 第3図
Figure 1 is a partial cross-sectional view of the GTO, Figure 2 is a conceptual diagram showing the cutting situation of a defective electrode, Figures 3 to 5 are process diagrams showing the procedure for attaching and removing the protective film according to the present invention, and Figure 6 is the completed product. It is a sectional view showing a state. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate electrode, 3... Cathode electrode, 3a... Defective electrode, 4... Contact electrode plate, 5... Bit, 6... Protective film, 7 ...Jig, 8
...Pa etching solution, 9...container. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1)交互に導電型の異なる少くとも3つの層と、この最
上層化互に独立して設けられた複数個に分割された領域
とを備える半導体および該各領域に設けた電極膜とを有
する半導体装置を製造するにあたり、前記分割された領
域のうち、欠陥を有する領域に属する電極膜を選択除去
して、前記欠陥を有する領域には、電流の導通をなくす
るための方法であって、前記半導体基体の主表面の全面
にわたって保護膜を被着した後、前記欠陥を有する領域
番こ属する電極膜上のみの保護膜に電極膜に達する傷を
つけて、この半導体基体を半導体のエツチング液に浸漬
することにより、前記欠陥を有する領域に属する電極膜
を溶解除去することを特徴゛ とする半導体装置の製造
方法。
1) A semiconductor comprising at least three layers of alternating conductivity types and a plurality of divided regions provided independently from each other in the uppermost layer, and an electrode film provided in each region. In manufacturing a semiconductor device, a method for selectively removing an electrode film belonging to a region having a defect among the divided regions to eliminate conduction of current to the region having the defect, the method comprising: After depositing a protective film over the entire main surface of the semiconductor substrate, the protective film is scratched to reach the electrode film only on the electrode film corresponding to the area having the defect, and the semiconductor substrate is etched with a semiconductor etching solution. A method for manufacturing a semiconductor device, characterized in that the electrode film belonging to the region having the defect is dissolved and removed by immersion in a liquid.
JP4340483A 1983-03-16 1983-03-16 Manufacture of semiconductor device Granted JPS59169175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4340483A JPS59169175A (en) 1983-03-16 1983-03-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4340483A JPS59169175A (en) 1983-03-16 1983-03-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59169175A true JPS59169175A (en) 1984-09-25
JPH041507B2 JPH041507B2 (en) 1992-01-13

Family

ID=12662822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4340483A Granted JPS59169175A (en) 1983-03-16 1983-03-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59169175A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112672525A (en) * 2020-11-12 2021-04-16 广州广合科技股份有限公司 Treatment method for incomplete etching in PCB negative film process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112672525A (en) * 2020-11-12 2021-04-16 广州广合科技股份有限公司 Treatment method for incomplete etching in PCB negative film process
CN112672525B (en) * 2020-11-12 2022-05-17 广州广合科技股份有限公司 Treatment method for incomplete etching in PCB negative film process

Also Published As

Publication number Publication date
JPH041507B2 (en) 1992-01-13

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