JPH04141759A - ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置 - Google Patents

３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置

Info

Publication number
JPH04141759A
JPH04141759A JP2263871A JP26387190A JPH04141759A JP H04141759 A JPH04141759 A JP H04141759A JP 2263871 A JP2263871 A JP 2263871A JP 26387190 A JP26387190 A JP 26387190A JP H04141759 A JPH04141759 A JP H04141759A
Authority
JP
Japan
Prior art keywords
input
program
level
buffer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2263871A
Other languages
English (en)
Japanese (ja)
Inventor
Masatoshi Kimura
正俊 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2263871A priority Critical patent/JPH04141759A/ja
Priority to US07/714,872 priority patent/US5248908A/en
Priority to EP91309040A priority patent/EP0479575A2/en
Publication of JPH04141759A publication Critical patent/JPH04141759A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Information Transfer Systems (AREA)
JP2263871A 1990-10-03 1990-10-03 ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置 Pending JPH04141759A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2263871A JPH04141759A (ja) 1990-10-03 1990-10-03 ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置
US07/714,872 US5248908A (en) 1990-10-03 1991-06-13 3-state bidirectional buffer and portable semiconductor storage device incorporating the same
EP91309040A EP0479575A2 (en) 1990-10-03 1991-10-02 3-state bidirectional buffer and portable semiconductor storage device incorporating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2263871A JPH04141759A (ja) 1990-10-03 1990-10-03 ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置

Publications (1)

Publication Number Publication Date
JPH04141759A true JPH04141759A (ja) 1992-05-15

Family

ID=17395403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2263871A Pending JPH04141759A (ja) 1990-10-03 1990-10-03 ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置

Country Status (3)

Country Link
US (1) US5248908A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0479575A2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH04141759A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349683A (en) * 1992-07-16 1994-09-20 Mosel-Vitelic Bidirectional FIFO with parity generator/checker
KR0121105B1 (ko) * 1994-02-04 1997-11-10 문정환 선입선출메모리 버스장치
US5432465A (en) * 1994-05-06 1995-07-11 Windbond Electronics Corp. Integrated circuit switchable between a line driver function and a bidirectional transceiver function during the packaging stage of the integrated circuit
GB2292277B (en) * 1994-08-12 1998-11-18 Icl Systems Ab Bus line buffering
US5517135A (en) * 1995-07-26 1996-05-14 Xilinx, Inc. Bidirectional tristate buffer with default input
US5656959A (en) * 1995-11-24 1997-08-12 International Microcircuits, Inc. Clock synthesizer dual function pin system and method therefor
US5736870A (en) * 1995-12-28 1998-04-07 Intel Corporation Method and apparatus for bi-directional bus driver
US5789944A (en) * 1996-06-28 1998-08-04 Cypress Semiconductor Corp. Asynchronous anticontention logic for bi-directional signals
US5767701A (en) * 1996-06-28 1998-06-16 Cypress Semiconductor Corp. Synchronous contention prevention logic for bi-directional signals
JP3284995B2 (ja) * 1999-01-14 2002-05-27 日本電気株式会社 双方向バスリピータ制御装置
US6580288B1 (en) * 1999-09-09 2003-06-17 International Business Machines Corporation Multi-property microprocessor with no additional logic overhead to shared pins
US6930514B2 (en) * 2002-09-30 2005-08-16 Lsi Logic Corporation Method and apparatus for transferring data between data buses
US7061274B2 (en) * 2003-09-24 2006-06-13 Stmicroelectronics, Inc. Self-programmable bidirectional buffer circuit and method
US7737727B2 (en) * 2007-12-17 2010-06-15 Intersil Americas Inc. Bi-directional buffer for open-drain or open-collector bus
US7692450B2 (en) * 2007-12-17 2010-04-06 Intersil Americas Inc. Bi-directional buffer with level shifting
US7639045B2 (en) * 2008-05-23 2009-12-29 Intersil Americas Inc. Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback
BR112013019308A2 (pt) 2011-02-01 2020-10-27 3M Innovative Propereties Company interface passiva para um dispositivo eletrônico de memória
US9183713B2 (en) 2011-02-22 2015-11-10 Kelly Research Corp. Perimeter security system
US9520878B1 (en) 2014-10-30 2016-12-13 Altera Corporation Methods and apparatus for transmitting a signal in a single direction using bidirectional driver circuits

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173695A (ja) * 1986-01-27 1987-07-30 Nec Corp Ｅｐｒｏｍ集積回路装置
JPS62223898A (ja) * 1986-03-26 1987-10-01 Hitachi Ltd 半導体記憶装置
JPH01116718A (ja) * 1987-10-29 1989-05-09 Mitsubishi Electric Corp メモリカード回路
JPH01118974A (ja) * 1987-10-31 1989-05-11 Toshiba Corp カードモジュール

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180597A (ja) * 1984-09-26 1986-04-24 Hitachi Ltd 半導体記憶装置
US4734885A (en) * 1985-10-17 1988-03-29 Harris Corporation Programming arrangement for programmable devices
US4970692A (en) * 1987-09-01 1990-11-13 Waferscale Integration, Inc. Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
DE3888294T2 (de) * 1987-11-25 1994-06-23 Nippon Electric Co Eingangsschaltung, die in eine Halbleiteranlage eingegliedert ist.
US4829203A (en) * 1988-04-20 1989-05-09 Texas Instruments Incorporated Integrated programmable bit circuit with minimal power requirement
JPH02208889A (ja) * 1989-02-09 1990-08-20 Mitsubishi Electric Corp Ｒｏｍカード

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173695A (ja) * 1986-01-27 1987-07-30 Nec Corp Ｅｐｒｏｍ集積回路装置
JPS62223898A (ja) * 1986-03-26 1987-10-01 Hitachi Ltd 半導体記憶装置
JPH01116718A (ja) * 1987-10-29 1989-05-09 Mitsubishi Electric Corp メモリカード回路
JPH01118974A (ja) * 1987-10-31 1989-05-11 Toshiba Corp カードモジュール

Also Published As

Publication number Publication date
US5248908A (en) 1993-09-28
EP0479575A2 (en) 1992-04-08
EP0479575A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1994-03-09

Similar Documents

Publication Publication Date Title
JPH04141759A (ja) ３ステート双方向バッファ及びこれを用いた携帯型半導体記憶装置
US6381190B1 (en) Semiconductor memory device in which use of cache can be selected
US6788592B2 (en) Memory device which can change control by chip select signal
EP0443775A2 (en) Signature circuit for non-volatile memory device
US5243701A (en) Method of and system for processing data having bit length variable with modes of operation
US5440248A (en) Power-saver differential input buffer
US5426432A (en) IC card
US6243777B1 (en) Circuit for preventing bus contention
KR960005897B1 (ko) 한개의 출력 단자에 대해 두개의 다른 출력 버퍼를 갖는 반도체 메모리 디바이스
KR920008446B1 (ko) 마이크로 프로세서
US5566311A (en) Semiconductor memory controller for reducing pass through current
JPH04205992A (ja) 入力バッファ回路，入出力バッファ回路及び携帯形半導体記憶装置
US8037282B2 (en) Register having security function and computer system including the same
KR920003271B1 (ko) 마이컴의 제어에 의한 메모리 라이트 방지회로
EP0419117A2 (en) Wafer-scale semiconductor device having fail-safe circuit
JPH04172588A (ja) Ｉｃカード
JP7490786B2 (ja) 制御回路及び半導体メモリ
JPH1139212A (ja) マイクロコンピュータ
US6246633B1 (en) Semiconductor memory device permitting stabilized operation and high-speed access
JPH01181146A (ja) シングルチップマイクロコンピュータ
JP4368150B2 (ja) 複合メモリ装置
KR910007400B1 (ko) Dma 제어기와 결합한 인터페이스 회로
JPH07182270A (ja) アドレス・データマルチプレクス制御可能なｒｏｍ内部回路
JPH0478090A (ja) 携帯形半導体記憶装置
JPH0221492A (ja) メモリ回路