JPH04137694A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH04137694A JPH04137694A JP25743290A JP25743290A JPH04137694A JP H04137694 A JPH04137694 A JP H04137694A JP 25743290 A JP25743290 A JP 25743290A JP 25743290 A JP25743290 A JP 25743290A JP H04137694 A JPH04137694 A JP H04137694A
- Authority
- JP
- Japan
- Prior art keywords
- board
- wiring conductor
- forming
- layer
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000007747 plating Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- 239000010419 fine particle Substances 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 9
- 239000011889 copper foil Substances 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 238000007788 roughening Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 19
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052573 porcelain Inorganic materials 0.000 description 3
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 2
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- PUZPDOWCWNUUKD-UHFFFAOYSA-M sodium fluoride Chemical compound [F-].[Na+] PUZPDOWCWNUUKD-UHFFFAOYSA-M 0.000 description 2
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical class Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229940079895 copper edta Drugs 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 235000013024 sodium fluoride Nutrition 0.000 description 1
- 239000011775 sodium fluoride Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は多層配線板の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a multilayer wiring board.
(従来の技術)
一従来、例えば絶縁基板の片面に配線導体を形成して印
刷配線板とし、これを電子部品を表面実装して用いてい
る。(Prior Art) Conventionally, for example, a wiring conductor is formed on one side of an insulating substrate to form a printed wiring board, and electronic components are mounted on the surface of this printed wiring board.
一例として絶縁基板にアルミナ磁器を用い、この表面に
配線導体と抵抗体とを印刷し焼成した厚膜混成集積回路
基板がある。An example is a thick film hybrid integrated circuit board in which alumina porcelain is used as an insulating substrate, wiring conductors and resistors are printed on the surface of the insulating substrate, and then fired.
(発明が解決しようとする課題)
しかし、アルミナ磁器等のセラミックを絶縁基板として
用いると、大面積の基板を製造することが困難である。(Problems to be Solved by the Invention) However, when ceramic such as alumina porcelain is used as an insulating substrate, it is difficult to manufacture a large-area substrate.
そのために、一つの機能を行なわせる回路を、多数枚の
基板で構成しなければならず、製造が困難になる欠点が
ある。また、硬いため、孔明けや切断等の加工もし雌い
欠点かある。Therefore, a circuit that performs one function must be constructed from a large number of substrates, which has the drawback of making manufacturing difficult. Also, because it is hard, it is difficult to process such as drilling or cutting.
本発明の目的は、以上の欠点を改良し、大面積のものが
得られ、製造が容易な多層配線板の製造方法を提供する
ものである。An object of the present invention is to improve the above-mentioned drawbacks, provide a method for manufacturing a multilayer wiring board that can have a large area, and is easy to manufacture.
(課題を解決するための手段)
本発明は、上記の目的を達成するために、基板の片面に
多層に配線導体を形成する多層配線板の製造方法におい
て、
a)片面銅張り樹脂積層板を基板に用い、これをエツチ
ングして第1の配線導体を形成する工程と、
b)白金族元素の微粒子を含む絶縁層を形成する工程と
、
C)孔を形成する工程又は前記絶縁層の表面にめっきレ
ジスト層を形成する工程のどちらか一方を先に他方を後
に行なう工程と、
d)無電解めっき法により前記絶縁層の表面に第2の配
線導体を形成する工程
とを順次行なうことを特徴とする多層配線板の製造方法
を提供するものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a multilayer wiring board in which wiring conductors are formed in multiple layers on one side of a board, including: a) a single-sided copper-clad resin laminate; b) forming an insulating layer containing fine particles of a platinum group element; and c) forming holes or the surface of the insulating layer. d) forming a second wiring conductor on the surface of the insulating layer by electroless plating; The present invention provides a method for manufacturing a multilayer wiring board characterized by:
(作用)
基板に片面銅張り樹脂積層板を用いているために、アル
ミナ磁器等のセラミックに比べて加工し易く、孔明けや
パンチング、断裁加工等が容易で、大面積の多層配線板
を容易に製造できる。(Function) Because the board uses a single-sided copper-clad resin laminate, it is easier to process than ceramics such as alumina porcelain, and it is easy to drill holes, punch, and cut, making it easy to create large-area multilayer wiring boards. can be manufactured.
(実施例) 以下、本発明を実施例に基づいて説明する。(Example) Hereinafter, the present invention will be explained based on examples.
基板1は、第1図に示す通り、絶縁樹脂積層板2−の片
面に銅箔3を張りつけた片面銅張り樹脂積層板を用いる
。この基板1として、例えば、全体の厚さ1.6B、銅
箔3部分の厚35μmの積層板(日立化成工業株式会社
製MCL−E67)を用いる。As shown in FIG. 1, the substrate 1 is a single-sided copper-clad resin laminate in which a copper foil 3 is pasted on one side of an insulating resin laminate 2-. As this substrate 1, for example, a laminate plate (MCL-E67, manufactured by Hitachi Chemical Co., Ltd.) with a total thickness of 1.6 B and a thickness of 3 copper foils of 35 μm is used.
そして、先ず銅箔3にエツチングレジストを印刷してマ
スキングした後、エツチング液によりエツチングレジス
トにより被覆していない銅箔3部分を除去し、さらにエ
ツチングレジストを除去して、第2図に示す通りに第1
の配線導体4を形成する。エツチング液には例えば、比
重40ボーメの塩化第二鉄溶液を用いる。First, an etching resist is printed on the copper foil 3 to mask it, and then the portion of the copper foil 3 that is not covered with the etching resist is removed using an etching solution, and then the etching resist is removed, as shown in FIG. 1st
A wiring conductor 4 is formed. For example, a ferric chloride solution with a specific gravity of 40 Baumé is used as the etching solution.
第1の配線導体4を形成後、第3図に示す通り、この第
1の配線導体4と絶縁樹脂積層板2の表面に白金族元素
の微粒子を含む絶縁層5を形成する。After forming the first wiring conductor 4, as shown in FIG. 3, an insulating layer 5 containing fine particles of a platinum group element is formed on the surfaces of the first wiring conductor 4 and the insulating resin laminate 2.
絶縁層5を形成するには、例えば、白金族元素であり、
めっき触媒としての作用を有するパラジウム微粉末を含
む粘稠なエポキシ樹脂組成物を、目の粗さが40メツシ
ユのステンレススクリーンを用いて基板1の表面全体に
塗布する。そして塗布後、温度150℃で60分間加熱
し、膜厚120μmに絶縁層5を形成する。For forming the insulating layer 5, for example, a platinum group element,
A viscous epoxy resin composition containing fine palladium powder that acts as a plating catalyst is applied to the entire surface of the substrate 1 using a stainless steel screen with a mesh size of 40. After coating, the insulating layer 5 is heated at a temperature of 150° C. for 60 minutes to form an insulating layer 5 with a thickness of 120 μm.
絶縁層5を形成後、その表面に、第4図に示す通り、パ
ラジウム微粉末を含む樹脂層6を積層する。樹脂層6を
形成するには、パラジウム微粉末入りの樹脂をカーテン
コート法により塗布し、温度170℃で90分間加熱し
て硬化し、30μmの厚さにする。After forming the insulating layer 5, a resin layer 6 containing fine palladium powder is laminated on its surface, as shown in FIG. To form the resin layer 6, a resin containing fine palladium powder is applied by a curtain coating method and cured by heating at a temperature of 170° C. for 90 minutes to a thickness of 30 μm.
樹脂層6を形成後、第5図に示す通り、基板1を貫通す
る孔7を設ける。孔7は、例えば、直径0.5ffi1
1程度のドリルを用いて設ける。After forming the resin layer 6, a hole 7 passing through the substrate 1 is provided as shown in FIG. The hole 7 has a diameter of 0.5ffi1, for example.
Install using a drill of about 1 size.
孔7を形成後、第6図に示す通り、樹脂層6の表面の第
2の配線導体を形成する以外の箇所に、めっきレジスト
層8を形成する。めっきレジスト層8は、例えば、エポ
キシ系樹脂の粘稠液をスクリーン印刷法によって印刷し
温度150°Cで30分間加熱処理して形成する。After forming the holes 7, as shown in FIG. 6, a plating resist layer 8 is formed on the surface of the resin layer 6 at locations other than those where the second wiring conductor is to be formed. The plating resist layer 8 is formed, for example, by printing a viscous liquid of an epoxy resin by a screen printing method and heat-treating it at a temperature of 150° C. for 30 minutes.
めっきレジスト層8を形成後、めっきレジスト層8によ
って被覆されていない樹脂層6を租面化す、る、粗面化
は、例えば、無水クロム酸、!酸、フッ化ナトリウムか
らなる酸化力の強い液に基板1を浸漬して行なう。After forming the plating resist layer 8, the resin layer 6 not covered by the plating resist layer 8 is roughened using, for example, chromic anhydride,! This is done by immersing the substrate 1 in a highly oxidizing solution consisting of acid and sodium fluoride.
粗化後、無電解銅めっき処理し、第7図に示す通り、第
2の配線導体9を形成し、同時にこの第2の配線導体9
と第1の配線導体4とを接続する。After roughening, electroless copper plating is performed to form a second wiring conductor 9 as shown in FIG.
and the first wiring conductor 4 are connected.
無電解銅めっき液には、硫酸銅・EDTA・ホルマリン
系のものを用いる。The electroless copper plating solution used is one based on copper sulfate, EDTA, and formalin.
なお、上記の実施例においては、孔7の形成後にめっき
レジスト層8を形成したが、逆に、めっきレジスト層8
を形成後に孔7を形成しても良い。In the above embodiment, the plating resist layer 8 was formed after the holes 7 were formed, but on the contrary, the plating resist layer 8 was formed after the holes 7 were formed.
The hole 7 may be formed after forming the hole 7.
また、樹脂層6は形成しなくても良、い。Further, the resin layer 6 may not be formed.
(発明の効果)
以上の通り、本発明の製造方法によれば、基板として片
面銅張り樹脂積層板を用いているために、孔明は等の加
工が容易で、大面積の多層配線板が容易に得られる。(Effects of the Invention) As described above, according to the manufacturing method of the present invention, since a single-sided copper-clad resin laminate is used as the substrate, it is easy to process wires, etc., and it is easy to manufacture large-area multilayer wiring boards. can be obtained.
第1図〜第7図は本発明の実施例の製造工程を示し、第
1図は基板の断面図、第2図は第1の配線導体を形成し
た基板の断面図、第3図は絶縁層を形成した基板の断面
図、第4図は樹脂層を形成した基板の断面図、第5図は
孔明けした基板の断面図、第6図はめつきレジスト層を
形成した基板の断面図、第7図は第2の配線導体を形成
した基板の断面図を示す。
1・・・基板、 4・・・第1の配線導体、5・・・絶
縁層、 6・・・樹脂層、 7・・・孔、8・・・めっ
きレジスト層、 9・・・第2の配線導体。
特許出願人 日立コンデンサ株式会社
第1
図
第2図
第3図
第4図1 to 7 show the manufacturing process of an embodiment of the present invention, FIG. 1 is a sectional view of the substrate, FIG. 2 is a sectional view of the substrate on which the first wiring conductor is formed, and FIG. 4 is a sectional view of a substrate on which a resin layer is formed; FIG. 5 is a sectional view of a substrate with holes formed thereon; FIG. 6 is a sectional view of a substrate on which a plating resist layer is formed; FIG. 7 shows a cross-sectional view of the substrate on which the second wiring conductor is formed. DESCRIPTION OF SYMBOLS 1... Substrate, 4... First wiring conductor, 5... Insulating layer, 6... Resin layer, 7... Hole, 8... Plating resist layer, 9... Second wiring conductor. Patent applicant Hitachi Capacitor Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
板の製造方法において、 a)片面銅張り樹脂積層板を基板に用い、これをエッチ
ングして第1の配線導体を形成 する工程と、 b)白金族元素の微粒子を含む絶縁層を形成する工程と
、 c)孔を形成する工程又は前記絶縁層の表面にめっきレ
ジスト層を形成する工程のどち らか一方を先に他方を後に行なう工程と、 d)無電解めっき法により前記絶縁層の表面に第2の配
線導体を形成する工程 とを順次行なうことを特徴とする多層配線板の製造方法
。(1) A method for manufacturing a multilayer wiring board in which wiring conductors are formed in multiple layers on one side of a board, including the steps of: a) using a single-sided copper-clad resin laminate as the board and etching it to form a first wiring conductor; b) forming an insulating layer containing fine particles of a platinum group element, and c) forming holes or forming a plating resist layer on the surface of the insulating layer, one of which is performed first and the other after. and d) forming a second wiring conductor on the surface of the insulating layer by electroless plating.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25743290A JPH04137694A (en) | 1990-09-28 | 1990-09-28 | Manufacture of multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25743290A JPH04137694A (en) | 1990-09-28 | 1990-09-28 | Manufacture of multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04137694A true JPH04137694A (en) | 1992-05-12 |
Family
ID=17306285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25743290A Pending JPH04137694A (en) | 1990-09-28 | 1990-09-28 | Manufacture of multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04137694A (en) |
-
1990
- 1990-09-28 JP JP25743290A patent/JPH04137694A/en active Pending
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