JPH10256731A - Manufacture of ceramic multilayer circuit board - Google Patents

Manufacture of ceramic multilayer circuit board

Info

Publication number
JPH10256731A
JPH10256731A JP6040797A JP6040797A JPH10256731A JP H10256731 A JPH10256731 A JP H10256731A JP 6040797 A JP6040797 A JP 6040797A JP 6040797 A JP6040797 A JP 6040797A JP H10256731 A JPH10256731 A JP H10256731A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
plating
ceramic multilayer
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6040797A
Other languages
Japanese (ja)
Inventor
Masaya Koyama
雅也 小山
Noboru Yamaguchi
昇 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP6040797A priority Critical patent/JPH10256731A/en
Publication of JPH10256731A publication Critical patent/JPH10256731A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To eliminate damages to a via by nucleating a plating nucleus on the via exposed with a surface of a ceramic board, then forming a metallic film on the via by an electroless plating method, and then roughing the surface of the ceramic board. SOLUTION: A plating nucleus is nucleated on a via, exposed with a surface of a baked ceramic board. Nucleating liquid used for this contains palladium, so that its pH is preferably 4 to 9. Then, after a metallic film is formed on the via by an electrolessly plating method, it is heat-treated at 300 to 450. Thereafter, the surface of the board formed with the metallic film is roughed by using hydrofluoric acid. Accordingly, since it is roughened after the film has been formed, elution of the glass component in the via is prevented so that no air gap is generated in the via.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、内層導体回路と、
導体ペーストを用いて形成したビアをその内部に形成し
ているセラミック基板の表面に、メッキ法により前記ビ
アと電気的に接続される薄膜金属層を形成して多層配線
板を製造するセラミック多層配線板の製造方法に関す
る。
[0001] The present invention relates to an inner conductor circuit,
Ceramic multilayer wiring for manufacturing a multilayer wiring board by forming a thin film metal layer electrically connected to the via by a plating method on a surface of a ceramic substrate in which a via formed using a conductive paste is formed. The present invention relates to a method for manufacturing a plate.

【0002】[0002]

【従来の技術】電子機器等の小型化、高機能化の進展に
伴って、IC等の電子部品を実装する基板としてセラミ
ック多層配線板が一部実用化されている。セラミック多
層配線板の製造方法としては、焼成したコア基板にペー
ストを用いて導体層と絶縁層を交互に印刷・焼成を繰り
返して製造する厚膜多層法と呼ばれる方法と、グリーン
シートに導体ペーストを印刷したものを積み重ね、プレ
スし、焼成して製造するグリーンシート多層法と呼ばれ
る方法が知られている。どちらの方法の場合も、表面回
路は導体ペーストを使用する厚膜法で形成するのが一般
的であるが、ファインパターンの形成が困難であるとい
う欠点があった。ファインパターンの形成を可能にする
ために、基板表面にスパッタ法で導体層を形成した後、
フォト法で表面回路を形成することが検討されている
が、スパッタ法は量産性に劣るという問題があり、実用
化は部分的なものに止まっている。
2. Description of the Related Art As electronic devices and the like have been reduced in size and advanced in function, ceramic multilayer wiring boards have been partially put into practical use as substrates for mounting electronic components such as ICs. As a method for manufacturing a ceramic multilayer wiring board, there is a method called a thick film multilayer method in which a conductor layer and an insulating layer are alternately printed and fired using a paste on a fired core substrate, and a conductor paste is applied to a green sheet. 2. Description of the Related Art There is known a method called a green sheet multi-layer method in which printed materials are stacked, pressed, and fired to produce them. In either case, the surface circuit is generally formed by a thick film method using a conductive paste, but has the drawback that it is difficult to form a fine pattern. After forming a conductor layer on the substrate surface by sputtering to enable the formation of a fine pattern,
Although formation of a surface circuit by a photo method has been studied, the sputtering method has a problem of inferior mass productivity, and its practical use is limited to a partial one.

【0003】そこで、基板表面に量産性に優れるメッキ
法で導体層を形成した後、フォト法で表面回路を形成す
ることが考えられるが、メッキ法で表面導体層を形成し
てセラミック多層配線板を製造しようとした場合にも解
決しなければならない問題点がある。すなわち、メッキ
法で表面導体層を形成する場合には、セラミック基板と
導体層の密着力を確保するために、フッ酸、溶融アルカ
リなどの薬品を用いて、メッキ前に基板表面の粗面化処
理を行うのが一般的であり、また、無電解メッキ法でメ
ッキを施す場合には、高温、高アルカリの条件でメッキ
するのが一般的であるが、このような過酷な処理をセラ
ミック基板に施した場合に、基板表面に露出しているビ
ア(導体層間を接続するための導体)がダメージを受け
て、接続信頼性が不十分になるという問題がある。この
理由としては、一般にビアは金属成分及びガラス成分を
含む導体ペーストを用いて形成されているので、上記の
ような過酷な処理が施されると、ビア中のガラス成分が
溶出して、ビア中に空隙が発生し、この空隙中に後工程
のメッキ液成分等が侵入、残存するため接続信頼性が不
十分になるものと考えられる。
Therefore, it is conceivable to form a conductor layer on a substrate surface by a plating method which is excellent in mass productivity and then form a surface circuit by a photo method. However, a ceramic multilayer wiring board is formed by forming a surface conductor layer by a plating method. There is a problem that needs to be solved even when trying to manufacture a hologram. In other words, when the surface conductor layer is formed by plating, the surface of the substrate is roughened before plating using a chemical such as hydrofluoric acid or molten alkali in order to secure the adhesion between the ceramic substrate and the conductor layer. In general, the plating is performed under conditions of high temperature and high alkali when plating by electroless plating. In this case, there is a problem that vias (conductors for connecting between conductive layers) exposed on the substrate surface are damaged, and connection reliability becomes insufficient. The reason for this is that the via is generally formed using a conductor paste containing a metal component and a glass component, so that when subjected to such severe processing, the glass component in the via elutes and the via It is considered that voids are generated therein, and plating solution components and the like in a later process enter and remain in the voids, so that connection reliability becomes insufficient.

【0004】[0004]

【発明が解決しようとする課題】本発明は上記の事情に
鑑みてなされたものであって、本発明の目的とするとこ
ろは、内層導体回路と、ガラス成分を含有する導体ペー
ストを用いて形成したビアをその内部に形成していて、
このビアの端部が表面に露出している焼成済みのセラミ
ック基板の表面を粗面化処理した後、メッキ法により前
記ビアと電気的に接続される薄膜金属層をセラミック基
板の表面に形成して多層配線板を製造するセラミック多
層配線板の製造方法であって、ビアがダメージを受ける
ことが少なく、そのため接続信頼性が十分なセラミック
多層配線板を製造することができる製造方法を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to form an inner layer conductor circuit and a conductor paste containing a glass component. With a via in it
After roughening the surface of the fired ceramic substrate in which the ends of the vias are exposed, a thin-film metal layer electrically connected to the vias is formed on the surface of the ceramic substrate by plating. A method for manufacturing a ceramic multilayer wiring board, which manufactures a multilayer wiring board by using a method, wherein a via is less likely to be damaged, and therefore a ceramic multilayer wiring board having sufficient connection reliability can be manufactured. It is in.

【0005】[0005]

【課題を解決するための手段】請求項1に係る発明のセ
ラミック多層配線板の製造方法は、内層導体回路と、ガ
ラス成分を含有する導体ペーストを用いて形成したビア
をその内部に形成していて、このビアの端部が表面に露
出している焼成済みのセラミック基板の表面を粗面化処
理した後、メッキ法により前記ビアと電気的に接続され
る薄膜金属層をセラミック基板の表面に形成して多層配
線板を製造するセラミック多層配線板の製造方法におい
て、セラミック基板の表面に露出しているビア上にメッ
キ核体の核付け処理を行い、次いでビア上に無電解メッ
キ法により金属皮膜を形成した後で、セラミック基板の
表面に対する前記粗面化処理を施すことを特徴とする。
According to a first aspect of the present invention, there is provided a method for manufacturing a ceramic multilayer wiring board, wherein an inner-layer conductive circuit and a via formed by using a conductive paste containing a glass component are formed therein. Then, after roughening the surface of the fired ceramic substrate in which the ends of the vias are exposed on the surface, a thin-film metal layer electrically connected to the via by plating is formed on the surface of the ceramic substrate. In a method for manufacturing a ceramic multilayer wiring board for forming and manufacturing a multilayer wiring board, a nucleating process of a plating nucleus is performed on a via exposed on the surface of the ceramic substrate, and then a metal is formed on the via by an electroless plating method. After forming the coating, the surface roughening treatment is performed on the surface of the ceramic substrate.

【0006】請求項2に係る発明のセラミック多層配線
板の製造方法は、請求項1記載の製造方法において、ビ
ア上に無電解メッキ法により金属皮膜を形成した後に、
セラミック基板を加熱処理してから、粗面化処理を施す
ことを特徴とする。
According to a second aspect of the present invention, there is provided a method of manufacturing a ceramic multilayer wiring board according to the first aspect, wherein a metal film is formed on the via by electroless plating.
After the ceramic substrate is subjected to a heat treatment, a roughening treatment is performed.

【0007】請求項3に係る発明のセラミック多層配線
板の製造方法は、請求項1又は請求項2記載の製造方法
において、メッキ核体の核付け処理に使用する核付け処
理液のpHが4〜9であることを特徴とする。
According to a third aspect of the present invention, there is provided the method for manufacturing a ceramic multilayer wiring board according to the first or second aspect, wherein the pH of the nucleating solution used for nucleating the plating nucleus is 4 or more. -9.

【0008】請求項1〜請求項3に係る発明のセラミッ
ク多層配線板の製造方法では、セラミック基板の表面に
露出しているビア上にメッキ核体の核付け処理を行い、
次いでビア上に無電解メッキ法により金属皮膜を形成し
た後で、セラミック基板の表面に対する粗面化処理を施
すので、粗面化処理の際に、ビア中のガラス成分が溶出
するのが防止されるので、ビア中に空隙が発生せず、従
って、得られるセラミック多層配線板の接続信頼性が十
分なものとなる。
In the method for manufacturing a ceramic multilayer wiring board according to the first to third aspects of the present invention, a plating nucleus is nucleated on a via exposed on the surface of the ceramic substrate,
Then, after forming a metal film on the via by electroless plating, the surface of the ceramic substrate is subjected to a surface roughening treatment, so that the glass component in the via is prevented from being eluted during the surface roughening treatment. Therefore, no void is generated in the via, and the connection reliability of the obtained ceramic multilayer wiring board is sufficient.

【0009】請求項2に係る発明のセラミック多層配線
板の製造方法では、ビア上に金属皮膜を形成した後で、
加熱処理を施すと、ビアの導体と無電解メッキ法で形成
した金属皮膜との間に拡散現象が生じ、ビアの導体と金
属皮膜とを強固に結合することができ好ましい。なお、
確実に拡散現象が生じさせるには、この加熱処理は30
0〜450℃の加熱処理であることが好ましい。
In the method for manufacturing a ceramic multilayer wiring board according to the second aspect of the present invention, after forming a metal film on the via,
Heat treatment is preferable because a diffusion phenomenon occurs between the conductor of the via and the metal film formed by the electroless plating method, so that the conductor of the via and the metal film can be firmly bonded. In addition,
To ensure that the diffusion phenomenon occurs, this heat treatment should be performed for 30 minutes.
The heat treatment is preferably performed at 0 to 450 ° C.

【0010】請求項3に係る発明のセラミック多層配線
板の製造方法では、メッキ核体の核付け処理に使用する
核付け処理液のpHが4〜9であるので、核付け処理の
際に、ビア中のガラス成分が溶出するのが防止されるの
で、ビア中の空隙の発生がより確実に防止される。
In the method for manufacturing a ceramic multilayer wiring board according to the third aspect of the present invention, since the pH of the nucleating solution used for the nucleating process of the plating nucleus is 4 to 9, Since the glass component in the via is prevented from being eluted, the generation of voids in the via is more reliably prevented.

【0011】[0011]

【発明の実施の形態】内層導体回路と、ガラス成分を含
有する導体ペーストを用いて形成したビアをその内部に
形成していて、このビアの端部が表面に露出している焼
成済みの多層化したセラミック基板を使用する。セラミ
ック基板材料としては、特に限定するものではないが、
ビアを形成する導体ペーストと同時焼成可能なホウケイ
酸ガラス等のガラスセラミック材料が好ましい。また、
導体ペーストに含有する導体成分としては、銀、パラジ
ウム、銅等を例示できるが、電気抵抗の点で銀を主成分
とすることが好ましい。そして、導体ペースト中には焼
成時にセラミックとの密着性を高めるためにガラス系成
分を含んでいる。また、内層導体回路の形成について
は、導体ペーストを使用する厚膜法で形成するのが簡便
であるが、スパッタ法、メッキ法等の薄膜法で形成して
もよい。
BEST MODE FOR CARRYING OUT THE INVENTION A fired multilayer in which an inner conductor circuit and a via formed using a conductor paste containing a glass component are formed therein, and the end of the via is exposed on the surface. A ceramic substrate is used. The ceramic substrate material is not particularly limited,
A glass ceramic material such as borosilicate glass that can be co-fired with the conductive paste forming the via is preferred. Also,
Examples of the conductor component contained in the conductor paste include silver, palladium, and copper, but it is preferable that silver is the main component in terms of electric resistance. The conductive paste contains a glass component in order to enhance the adhesion to the ceramic during firing. Further, the inner conductor circuit is preferably formed by a thick film method using a conductor paste, but may be formed by a thin film method such as a sputtering method or a plating method.

【0012】上記の焼成済みのセラミック基板の表面に
露出しているビア上にメッキ核体の核付け処理を行う
が、核付け処理に使用する核付け液はパラジウムを含ん
でいて、そのpHが4〜9であることが好ましい。pH
が4〜9の範囲内であると、核付け処理の際のビア中の
ガラス成分の溶出が抑制されるからである。そして、ビ
ア上にメッキ核体の核付け処理を行うに際しては、ビア
上のみに選択的に核付けができる核付け処理を使用する
と、ビア以外のセラミック基板表面にメッキ核体が付着
しないので好ましいが、ビア以外のセラミック基板の表
面に核付けがされないようにレジスト等を用いてビアの
部分だけを露出させるような方法でビア上のみに核付け
するようにしてもよい。
The plating nucleus is nucleated on the via exposed on the surface of the fired ceramic substrate. The nucleating liquid used for the nucleating treatment contains palladium, and the pH of the nucleating solution is palladium. It is preferably from 4 to 9. pH
Is within the range of 4 to 9, elution of the glass component in the via at the time of the nucleating process is suppressed. When performing the nucleating process of the plating nucleus on the via, it is preferable to use a nucleating process that can selectively nucleate only on the via, since the plating nucleus does not adhere to the surface of the ceramic substrate other than the via. However, nucleation may be performed only on the via by using a resist or the like to expose only the via portion so that nucleation is not performed on the surface of the ceramic substrate other than the via.

【0013】次いで、ビア上のみに無電解メッキ法によ
り金属皮膜を形成した後で、セラミック基板の表面に粗
面化処理を施す。無電解メッキ法により形成する金属皮
膜の材質としては、ニッケル、パラジウム等が例示でき
る。そして、このような金属皮膜を形成した後で、30
0〜450℃の加熱処理を施すと、ビアの導体と無電解
メッキ法で形成した金属皮膜との間に拡散現象が生じ、
ビアの導体と金属皮膜とを強固に結合することができ好
ましい。
Next, after forming a metal film only on the via by electroless plating, the surface of the ceramic substrate is subjected to a surface roughening treatment. Examples of the material of the metal film formed by the electroless plating method include nickel and palladium. After forming such a metal film, 30
When a heat treatment of 0 to 450 ° C. is performed, a diffusion phenomenon occurs between the conductor of the via and the metal film formed by the electroless plating method,
It is preferable because the conductor of the via and the metal film can be firmly bonded.

【0014】次いで、金属皮膜を形成したセラミック基
板の表面にフッ酸、リン酸、溶融アルカリなどの薬品を
用いて、粗面化処理を施し、次いで、無電解メッキ又は
電解メッキ法によりビアと電気的に接続される薄膜金属
層をセラミック基板の表面に形成して多層配線板を製造
する。ビア上に金属皮膜を形成した後で、粗面化処理を
施すので、粗面化処理の際に、ビア中のガラス成分が溶
出するのが防止され、ビア中に空隙が発生せず、従っ
て、得られるセラミック多層配線板の接続信頼性が十分
なものとなる。フッ酸及び溶融アルカリはビア中のガラ
ス成分を溶出させる0程度がリン酸に比べて大きいの
で、粗面化処理に使用する薬品としてはリン酸が好まし
い。なお、粗面化処理後の薄膜金属層の形成について
は、無電解メッキ法により導電性を示す厚み以上であっ
て、3μm以下の厚みの下地金属層を形成した後、電解
メッキ法により所定厚みの薄膜金属層を形成する方法で
行うと、所定厚みの薄膜金属層の形成を全て無電解メッ
キで行った場合に比べ、無電解メッキを短時間で終える
ため、無電解メッキ工程でのビア中のガラス成分の溶出
が抑制され、ビア中の空隙の発生がより確実に防止され
る。
Next, the surface of the ceramic substrate on which the metal film has been formed is subjected to a surface roughening treatment using a chemical such as hydrofluoric acid, phosphoric acid, or a molten alkali. A thin-film metal layer to be electrically connected is formed on the surface of the ceramic substrate to manufacture a multilayer wiring board. After the metal film is formed on the via, the surface roughening treatment is performed, so that the glass component in the via is prevented from being eluted during the surface roughening treatment, and no void is generated in the via, and therefore, Thus, the connection reliability of the obtained ceramic multilayer wiring board becomes sufficient. Since hydrofluoric acid and molten alkali have a value of about 0 that elutes the glass component in the vias is larger than phosphoric acid, phosphoric acid is preferable as a chemical used for the surface roughening treatment. In addition, about the formation of the thin film metal layer after the surface roughening treatment, after forming a base metal layer having a thickness of not less than the thickness showing conductivity by electroless plating and not more than 3 μm, a predetermined thickness is formed by electrolytic plating. When the method of forming a thin film metal layer is performed, the electroless plating is completed in a short time, compared with the case where all of the formation of the thin film metal layer of a predetermined thickness are performed by electroless plating. Of the glass component is suppressed, and the generation of voids in the via is more reliably prevented.

【0015】[0015]

【実施例】以下、本発明を実施例及び比較例に基づいて
説明する。なお、本発明は下記の実施例に制限されな
い。
The present invention will be described below based on examples and comparative examples. In addition, this invention is not limited to a following example.

【0016】(実施例1)ホウケイ酸鉛系ガラスとアル
ミナ粉末とを主成分としたグリーンシートに導体層間を
接続するためのビアホールを打ち抜いて形成した。次い
で、このグリーンシートに対し、ホウケイ酸鉛系ガラス
を含む銀ペーストを用いて、内層導体回路の印刷及びビ
アホール内へのペースト充填を行った。次いで、このグ
リーンシートを4枚積層し、プレスした後、900℃の
酸化雰囲気で焼成して一体化したセラミック基板を得
た。このセラミック基板表面に露出しているビア上に中
性タイプの核付け液(上村工業社製、商品名アクタスM
PD−38、pH6.9)を用い、70℃、5分間パラ
ジウムの核付け処理を行った。この核付け液を使用した
場合はビア上のみに選択的に核付けを行うことができ
た。
(Example 1) Via holes for connecting conductive layers were formed by punching a green sheet containing lead borosilicate glass and alumina powder as main components. Next, using a silver paste containing lead borosilicate glass, printing of the inner conductor circuit and filling of the paste into the via hole were performed on the green sheet. Next, four green sheets were laminated and pressed, and then fired in an oxidizing atmosphere at 900 ° C. to obtain an integrated ceramic substrate. A neutral type nucleating liquid (trade name Actus M, manufactured by Uemura Kogyo Co., Ltd.)
Using PD-38, pH 6.9), palladium nucleation treatment was performed at 70 ° C. for 5 minutes. When this nucleating solution was used, nucleation could be selectively performed only on the via.

【0017】核付け処理後、弱酸性タイプの無電解ニッ
ケルメッキ液(上村工業社製、商品名ニムデンNPR、
pH4.6)を用い、85℃、15分間のメッキ条件で
厚み3μmのニッケルメッキ皮膜をビア上に形成した。
得られたセラミック基板を180℃の熱リン酸に2分間
浸漬し、セラミック基板の表面を粗面化した。この後、
セラミック基板表面に、キャタリスト処理(奥野製薬社
製、商品名OPC−80M)を室温で5分行い、続いて
アクセレーター処理(奥野製薬社製、商品名OPC50
0MX1,2)を35℃で5分行って、パラジウムの核
付け処理を行い、次いで無電解銅メッキ液に浸漬し、膜
圧1μmの下地金属層(導電性を示すに十分な厚み)を
形成した後、電流密度2A/dm2 、メッキ時間15分
で電解銅メッキ法を行い、トータル膜厚10μmの薄膜
金属層(銅メッキ層)を形成した。次いで、薄膜金属層
に外層導体回路を形成してセラミック多層配線板を得
た。得られたセラミック多層配線板の断面を観察したと
ころ、ビア中の空隙の発生は観察されなかった。従っ
て、接続信頼性が十分なセラミック多層配線板を作製で
きたと評価した。
After the nucleation treatment, a weakly acidic type electroless nickel plating solution (trade name Nimden NPR, manufactured by Uemura Kogyo Co., Ltd.)
Using a pH of 4.6), a 3 μm thick nickel plating film was formed on the via under plating conditions of 85 ° C. for 15 minutes.
The obtained ceramic substrate was immersed in hot phosphoric acid at 180 ° C. for 2 minutes to roughen the surface of the ceramic substrate. After this,
Catalyst treatment (Okuno Pharmaceutical Co., Ltd., product name OPC-80M) is performed on the surface of the ceramic substrate at room temperature for 5 minutes, followed by accelerator treatment (Okuno Pharmaceutical Co., Ltd., product name OPC50).
0MX1, 2) at 35 ° C. for 5 minutes to nucleate palladium, and then immersed in an electroless copper plating solution to form a base metal layer (thickness sufficient to show conductivity) with a film pressure of 1 μm. Thereafter, electrolytic copper plating was performed at a current density of 2 A / dm 2 and a plating time of 15 minutes to form a thin metal layer (copper plated layer) having a total film thickness of 10 μm. Next, an outer conductor circuit was formed on the thin metal layer to obtain a ceramic multilayer wiring board. Observation of the cross section of the obtained ceramic multilayer wiring board showed no generation of voids in the vias. Therefore, it was evaluated that a ceramic multilayer wiring board with sufficient connection reliability could be manufactured.

【0018】(比較例1)核付け処理を行ったビア上へ
のニッケルメッキ皮膜の形成を行わずに、セラミック基
板の表面を粗面化処理を行うようにした以外は、実施例
1と同様にして、セラミック多層配線板を得た。得られ
たセラミック多層配線板の断面を観察したところ、ビア
の表面から深さ約20μmの部分に空隙の発生が観察さ
れ、ビアがダメージを受けているのが確認された。従っ
て、接続信頼性が不十分なセラミック多層配線板しか作
製できていないと評価した。
Comparative Example 1 Same as Example 1 except that the surface of the ceramic substrate was roughened without forming a nickel plating film on the nucleated via. Thus, a ceramic multilayer wiring board was obtained. When the cross section of the obtained ceramic multilayer wiring board was observed, the occurrence of a void was observed at a depth of about 20 μm from the surface of the via, and it was confirmed that the via was damaged. Therefore, it was evaluated that only a ceramic multilayer wiring board having insufficient connection reliability could be manufactured.

【0019】(実施例2)核付け処理を行ったビア上へ
のニッケルメッキ皮膜の形成を、中性タイプの無電解ニ
ッケルメッキ液(奥野製薬社製、商品名トップケミアロ
イ66、pH6.5)を用い、65℃、15分間のメッ
キ条件で厚み2μmのニッケルメッキ皮膜を形成した以
外は、実施例1と同様にして、セラミック多層配線板を
得た。得られたセラミック多層配線板の断面を観察した
ところ、ビア中の空隙の発生は観察されなかった。従っ
て、接続信頼性が十分なセラミック多層配線板を作製で
きたと評価した。
(Example 2) The formation of a nickel plating film on a nucleated via was performed by using a neutral type electroless nickel plating solution (trade name: Top Chemical Alloy 66, manufactured by Okuno Pharmaceutical Co., Ltd., pH 6.5). ), A ceramic multilayer wiring board was obtained in the same manner as in Example 1 except that a nickel plating film having a thickness of 2 μm was formed under plating conditions of 65 ° C. for 15 minutes. Observation of the cross section of the obtained ceramic multilayer wiring board showed no generation of voids in the vias. Therefore, it was evaluated that a ceramic multilayer wiring board with sufficient connection reliability could be manufactured.

【0020】(実施例3)核付け処理を行ったビア上へ
の無電解メッキ法による金属皮膜の形成を、中性タイプ
の無電解パラジウムメッキ液(奥野製薬社製、商品名ム
デンノーブル、pH6.5)を用い、55℃、20分間
のメッキ条件で厚み2μmのパラジウムメッキ皮膜を形
成した以外は、実施例1と同様にして、セラミック多層
配線板を得た。得られたセラミック多層配線板の断面を
観察したところ、ビア中の空隙の発生は観察されなかっ
た。従って、接続信頼性が十分なセラミック多層配線板
を作製できたと評価した。
Example 3 The formation of a metal film on a nucleated via by an electroless plating method was performed using a neutral type electroless palladium plating solution (Mudden Noble, product name, manufactured by Okuno Pharmaceutical Co., Ltd., pH 6.0). Using 5), a ceramic multilayer wiring board was obtained in the same manner as in Example 1, except that a 2 μm-thick palladium plating film was formed under the plating conditions of 55 ° C. and 20 minutes. Observation of the cross section of the obtained ceramic multilayer wiring board showed no generation of voids in the vias. Therefore, it was evaluated that a ceramic multilayer wiring board with sufficient connection reliability could be manufactured.

【0021】(実施例4)核付け処理を行ったビア上へ
の無電解メッキ法による金属皮膜の形成をした後で、セ
ラミック基板の表面を粗面化する前に、窒素雰囲気下
で、350℃でアニール処理した以外は、実施例1と同
様にして、セラミック多層配線板を得た。得られたセラ
ミック多層配線板の断面を観察したところ、ビア中の空
隙の発生は観察されなかった。また、XMA分析でニッ
ケルと銀の拡散層の存在が確認された。従って、ビアの
導体と金属皮膜とが強固に結合していて、且つ、接続信
頼性が十分なセラミック多層配線板を作製できたと評価
した。
(Embodiment 4) After a metal film is formed on the nucleated via by an electroless plating method, and before the surface of the ceramic substrate is roughened, it is heated in a nitrogen atmosphere at 350.degree. A ceramic multilayer wiring board was obtained in the same manner as in Example 1 except that the annealing treatment was performed at ℃. Observation of the cross section of the obtained ceramic multilayer wiring board showed no generation of voids in the vias. XMA analysis confirmed the presence of a nickel and silver diffusion layer. Therefore, it was evaluated that a ceramic multilayer wiring board in which the conductor of the via was firmly bonded to the metal film and the connection reliability was sufficient was produced.

【0022】(実施例5)核付け処理を行ったビア上へ
の無電解メッキ法による金属皮膜の形成をした後で、セ
ラミック基板の表面を粗面化する前に、窒素雰囲気下
で、350℃でアニール処理した以外は、実施例3と同
様にして、セラミック多層配線板を得た。得られたセラ
ミック多層配線板の断面を観察したところ、ビア中の空
隙の発生は観察されなかった。また、XMA分析でパラ
ジウムと銀の拡散層の存在が確認された。従って、ビア
の導体と金属皮膜とが強固に結合していて、且つ、接続
信頼性が十分なセラミック多層配線板を作製できたと評
価した。
(Embodiment 5) After a metal film is formed on the nucleated via by an electroless plating method, and before the surface of the ceramic substrate is roughened, it is heated in a nitrogen atmosphere at 350.degree. A ceramic multilayer wiring board was obtained in the same manner as in Example 3 except that the annealing treatment was performed at ℃. Observation of the cross section of the obtained ceramic multilayer wiring board showed no generation of voids in the vias. In addition, XMA analysis confirmed the presence of a palladium and silver diffusion layer. Therefore, it was evaluated that a ceramic multilayer wiring board in which the conductor of the via was firmly bonded to the metal film and the connection reliability was sufficient was produced.

【0023】[0023]

【発明の効果】請求項1〜請求項3に係る発明のセラミ
ック多層配線板の製造方法では、ビア上にメッキ核体の
核付け処理を行い、次いでビア上に無電解メッキ法によ
り金属皮膜を形成した後で、粗面化処理を施すので、粗
面化処理の際にビア中のガラス成分が溶出するのが防止
される。従って、請求項1〜請求項3に係る発明のセラ
ミック多層配線板の製造方法によれば、ビア中に空隙が
発生していない、接続信頼性が優れたセラミック多層配
線板を製造することが可能になる。
In the method for manufacturing a ceramic multilayer wiring board according to the first to third aspects of the present invention, a nucleating treatment of a plating nucleus is performed on a via, and then a metal film is formed on the via by an electroless plating method. After the formation, the roughening treatment is performed, so that the glass component in the via is prevented from being eluted during the roughening treatment. Therefore, according to the method for manufacturing a ceramic multilayer wiring board according to the first to third aspects of the present invention, it is possible to manufacture a ceramic multilayer wiring board having no connection gap and excellent connection reliability. become.

【0024】請求項2に係る発明のセラミック多層配線
板の製造方法では、ビア上に金属皮膜を形成した後で、
加熱処理を施すので、ビアの導体と無電解メッキ法で形
成した金属皮膜との間に拡散現象が生じる。従って、請
求項2に係る発明のセラミック多層配線板の製造方法に
よれば、上記の効果に加えて、ビアの導体と金属皮膜と
がより強固に結合したセラミック多層配線板を製造する
ことがが可能になる。
In the method for manufacturing a ceramic multilayer wiring board according to the second aspect of the present invention, after forming a metal film on the via,
Since the heat treatment is performed, a diffusion phenomenon occurs between the conductor of the via and the metal film formed by the electroless plating method. Therefore, according to the method for manufacturing a ceramic multilayer wiring board of the invention according to claim 2, in addition to the above effects, it is possible to manufacture a ceramic multilayer wiring board in which the conductor of the via and the metal film are more firmly bonded. Will be possible.

【0025】請求項3に係る発明のセラミック多層配線
板の製造方法では、メッキ核体の核付け処理に使用する
核付け処理液のpHが4〜9であるので、核付け処理の
際に、ビア中のガラス成分が溶出するのが防止される。
従ってこの製造方法によれば、ビア中の空隙の発生がよ
り確実に防止される。
In the method for manufacturing a ceramic multilayer wiring board according to the third aspect of the present invention, the pH of the nucleating solution used for the nucleating process of the plating nucleus is 4 to 9, so that the Elution of the glass component in the via is prevented.
Therefore, according to this manufacturing method, generation of a void in the via is more reliably prevented.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 内層導体回路と、ガラス成分を含有する
導体ペーストを用いて形成したビアをその内部に形成し
ていて、このビアの端部が表面に露出している焼成済み
のセラミック基板の表面を粗面化処理した後、メッキ法
により前記ビアと電気的に接続される薄膜金属層をセラ
ミック基板の表面に形成して多層配線板を製造するセラ
ミック多層配線板の製造方法において、セラミック基板
の表面に露出しているビア上にメッキ核体の核付け処理
を行い、次いでビア上に無電解メッキ法により金属皮膜
を形成した後で、セラミック基板の表面に対する前記粗
面化処理を施すことを特徴とするセラミック多層配線板
の製造方法。
An internal conductor circuit and a via formed using a conductive paste containing a glass component are formed therein, and the end of the via is exposed on the surface of the fired ceramic substrate. A method for producing a multilayer wiring board, comprising: forming a thin-film metal layer electrically connected to the via by plating on the surface of the ceramic substrate after the surface is roughened; Performing a nucleating treatment of a plating nucleus on the via exposed on the surface of the substrate, and then forming a metal film on the via by an electroless plating method, and then performing the surface roughening treatment on the surface of the ceramic substrate. A method for manufacturing a ceramic multilayer wiring board, comprising:
【請求項2】 ビア上に無電解メッキ法により金属皮膜
を形成した後に、セラミック基板を加熱処理してから、
粗面化処理を施すことを特徴とする請求項1記載のセラ
ミック多層配線板の製造方法。
2. After forming a metal film on the via by an electroless plating method, heat-treating the ceramic substrate,
2. The method for manufacturing a ceramic multilayer wiring board according to claim 1, wherein a roughening treatment is performed.
【請求項3】 メッキ核体の核付け処理に使用する核付
け処理液のpHが4〜9であることを特徴とする請求項
1又は請求項2記載のセラミック多層配線板の製造方
法。
3. The method for producing a ceramic multilayer wiring board according to claim 1, wherein the pH of the nucleating solution used for the nucleating process of the plating nucleus is 4 to 9.
JP6040797A 1997-03-14 1997-03-14 Manufacture of ceramic multilayer circuit board Withdrawn JPH10256731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6040797A JPH10256731A (en) 1997-03-14 1997-03-14 Manufacture of ceramic multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6040797A JPH10256731A (en) 1997-03-14 1997-03-14 Manufacture of ceramic multilayer circuit board

Publications (1)

Publication Number Publication Date
JPH10256731A true JPH10256731A (en) 1998-09-25

Family

ID=13141303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6040797A Withdrawn JPH10256731A (en) 1997-03-14 1997-03-14 Manufacture of ceramic multilayer circuit board

Country Status (1)

Country Link
JP (1) JPH10256731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018037842A1 (en) * 2016-08-22 2018-03-01 株式会社村田製作所 Ceramic substrate, and module with built-in electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018037842A1 (en) * 2016-08-22 2018-03-01 株式会社村田製作所 Ceramic substrate, and module with built-in electronic component
CN109565939A (en) * 2016-08-22 2019-04-02 株式会社村田制作所 Ceramic substrate and module having built-in electronic parts
JPWO2018037842A1 (en) * 2016-08-22 2019-06-20 株式会社村田製作所 Ceramic substrate and electronic component built-in module
US11246215B2 (en) 2016-08-22 2022-02-08 Murata Manufacturing Co., Ltd. Ceramic substrate and electronic component-embedded module
CN109565939B (en) * 2016-08-22 2022-04-05 株式会社村田制作所 Ceramic substrate and electronic component built-in module
US11553592B2 (en) 2016-08-22 2023-01-10 Murata Manufacturing Co., Ltd. Ceramic substrate and electronic component-embedded module

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