JPH0964541A - Production of multilayered ceramic wiring board - Google Patents

Production of multilayered ceramic wiring board

Info

Publication number
JPH0964541A
JPH0964541A JP21890795A JP21890795A JPH0964541A JP H0964541 A JPH0964541 A JP H0964541A JP 21890795 A JP21890795 A JP 21890795A JP 21890795 A JP21890795 A JP 21890795A JP H0964541 A JPH0964541 A JP H0964541A
Authority
JP
Japan
Prior art keywords
ceramic
wiring board
conductor
outer layer
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP21890795A
Other languages
Japanese (ja)
Inventor
Masaya Koyama
雅也 小山
Noboru Yamaguchi
昇 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP21890795A priority Critical patent/JPH0964541A/en
Publication of JPH0964541A publication Critical patent/JPH0964541A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To produce a ceramic multilayered wiring board excellent in the reliability of connection between the wiring conductor of the outer layer formed by a thin film method and a conductor of via part formed by a thick film method. SOLUTION: The wiring conductor of the outer layer is formed by a thin film method on the surface of a ceramic board where the wiring conductor of the inner layer is formed by a thick film method and integrated. In such a method for producing a ceramic multilayered wiring board, the surface of a ceramic board is roughened using heated phosphoric acid prior to formation of the wiring conductor of the outer layer. In this production method, the temperature of phosphoric acid for roughening the surface of the ceramic board is set in the range of 140-360 deg.C.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品として利
用されるセラミック多層配線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ceramic multilayer wiring board used as an electronic component.

【0002】[0002]

【従来の技術】従来のセラミック多層配線板における外
層の配線導体の形成法としては、内部の配線導体の形成
法と同様に、導体ペーストを印刷、焼成する厚膜法が一
般的であった。しかし、厚膜法の場合は微細な回路を形
成することが困難であり、またガラスフリットを構成成
分として含有するため半田付け性の点でも問題があっ
た。そこで、蒸着、スパッタリング、めっき等の薄膜法
で外層の配線導体を形成する方法が検討されていて、例
えば特開平6−104569号に開示されている。この
方法では微細な回路を形成することが可能となり、ま
た、半田付け性の問題も解消することができる。しか
し、薄膜法で外層の配線導体を形成した場合には、外層
の配線導体とビア部(内部の配線の一部)を形成してい
る厚膜法による導体との接続信頼性に問題がありその改
善が求められているのが現状である。
2. Description of the Related Art As a method of forming a wiring conductor of an outer layer in a conventional ceramic multilayer wiring board, a thick film method of printing and firing a conductor paste is generally used as in the method of forming an internal wiring conductor. However, in the case of the thick film method, it is difficult to form a fine circuit, and since the glass frit is contained as a constituent component, there is a problem in solderability. Therefore, a method of forming a wiring conductor of an outer layer by a thin film method such as vapor deposition, sputtering or plating has been studied, and is disclosed in, for example, Japanese Patent Laid-Open No. 6-104569. With this method, a fine circuit can be formed, and the problem of solderability can be solved. However, when the outer layer wiring conductor is formed by the thin film method, there is a problem in connection reliability between the outer layer wiring conductor and the conductor formed by the thick film method forming the via portion (a part of the inner wiring). At present, the improvement is required.

【0003】[0003]

【発明が解決しようとする課題】本発明は上記のような
事情に鑑みてなされたものであって、その目的とすると
ころは、薄膜法で外層の配線導体を形成する方法であっ
て、外層の配線導体とビア部を形成している厚膜法によ
る導体との接続信頼性に優れたセラミック多層配線板を
製造することができるセラミック多層配線板の製造方法
を提供することである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is a method of forming a wiring conductor of an outer layer by a thin film method. (EN) A ceramic multilayer wiring board manufacturing method capable of manufacturing a ceramic multilayer wiring board excellent in connection reliability between a wiring conductor of (1) and a conductor forming a via portion by a thick film method.

【0004】[0004]

【課題を解決するための手段】請求項1に係る発明のセ
ラミック多層配線板の製造方法は、内部の配線導体を厚
膜法で形成して一体化したセラミック基板の表面に薄膜
法で外層の配線導体を形成するセラミック多層配線板の
製造方法において、外層の配線導体を形成する前に、前
記セラミック基板の表面を加熱リン酸を用いて粗面化処
理することを特徴とする。
According to a first aspect of the present invention, there is provided a ceramic multilayer wiring board manufacturing method, wherein an inner wiring conductor is formed by a thick film method and integrated on a surface of a ceramic substrate to form an outer layer by a thin film method. In the method for manufacturing a ceramic multilayer wiring board for forming a wiring conductor, the surface of the ceramic substrate is roughened with hot phosphoric acid before the wiring conductor of the outer layer is formed.

【0005】請求項2に係る発明のセラミック多層配線
板の製造方法は、請求項1記載の製造方法において、セ
ラミック基板の表面を粗面化処理する加熱リン酸の温度
が140〜360℃であることを特徴とする。
The method for manufacturing a ceramic multilayer wiring board according to a second aspect of the present invention is the method according to the first aspect, wherein the temperature of the heated phosphoric acid for roughening the surface of the ceramic substrate is 140 to 360 ° C. It is characterized by

【0006】[0006]

【発明の実施の形態】以下、本発明の実施の形態を説明
する。
Embodiments of the present invention will be described below.

【0007】本発明では、内部の配線導体を厚膜法で形
成して一体化したセラミック基板を使用する。ここでい
う厚膜法は導体ペーストを印刷、焼成して配線導体を形
成する方法であり、導体ペーストとしては、タングステ
ンペースト、銀ペースト、銅ペースト等を使用すること
ができる。また、一体化したセラミック基板を得る方法
としては、例えばコージェライト等のガラスセラミック
のグリーンシートを用いて一体化する方法、アルミナ等
の高温焼成タイプのセラミックのグリーンシートを用い
て一体化する方法や焼成によりセラミック絶縁膜となる
ペーストを使用する厚膜印刷多層法(特開平6−104
569号に開示されている方法)等が例示でき、特に限
定はない。
In the present invention, a ceramic substrate is used in which internal wiring conductors are formed by a thick film method and integrated. The thick film method here is a method of printing and firing a conductor paste to form a wiring conductor, and as the conductor paste, a tungsten paste, a silver paste, a copper paste, or the like can be used. Further, as a method of obtaining an integrated ceramic substrate, for example, a method of integration using a glass ceramic green sheet such as cordierite, a method of integration using a high temperature firing type ceramic green sheet such as alumina, or A thick film printing multilayer method using a paste which becomes a ceramic insulating film by firing (Japanese Patent Laid-Open No. 6-104)
No. 569) and the like, and there is no particular limitation.

【0008】本発明では、上記の一体化したセラミック
基板の表面に薄膜法で外層の配線導体を形成する前に、
このセラミック基板の表面に加熱リン酸を用いて粗面化
処理を施す。その際に、セラミック基板の表面には厚膜
法で形成された内部配線の一部であるビア部が露出して
おり、このビア部も加熱リン酸により粗面化処理が施さ
れる。そのため、粗面化処理を施した後で外層の配線導
体を薄膜法で形成すると、外層の配線導体とビア部を形
成している厚膜法による導体とが、アンカー効果により
強固に接続されるので、接続信頼性に優れたセラミック
多層配線板が得られる。なお、粗面化処理をフッ酸を用
いて行うと、基板表面にフッ酸が残存した場合に、じわ
じわとエッチングが進行したり、薄膜法による金属皮膜
を腐食するおそれがあるので好ましくない。
In the present invention, before forming the outer layer wiring conductor on the surface of the above-mentioned integrated ceramic substrate by the thin film method,
The surface of this ceramic substrate is roughened by using hot phosphoric acid. At that time, a via portion, which is a part of the internal wiring formed by the thick film method, is exposed on the surface of the ceramic substrate, and the via portion is also roughened by hot phosphoric acid. Therefore, when the outer layer wiring conductor is formed by the thin film method after the roughening treatment, the outer layer wiring conductor and the thick film method conductor forming the via portion are firmly connected by the anchor effect. Therefore, a ceramic multilayer wiring board having excellent connection reliability can be obtained. Note that it is not preferable to perform the surface roughening treatment using hydrofluoric acid, because if hydrofluoric acid remains on the substrate surface, the etching may gradually progress and the metal film formed by the thin film method may be corroded.

【0009】本発明の加熱リン酸により粗面化処理の条
件については、特に限定するものではないが、加熱リン
酸の温度を140〜360℃とすることが望ましい。1
40℃未満の場合は粗面化が不十分となり、360℃を
越えると粗面化が過度になり基板強度が低下する問題が
生じやすくなるからである。
The conditions for the surface roughening treatment with the heated phosphoric acid of the present invention are not particularly limited, but the temperature of the heated phosphoric acid is preferably 140 to 360 ° C. 1
When the temperature is lower than 40 ° C., the surface roughening is insufficient, and when the temperature is higher than 360 ° C., the surface roughening becomes excessive and the substrate strength tends to be lowered.

【0010】[0010]

【実施例】以下、本発明を実施例及び比較例に基づいて
説明する。
The present invention will be described below based on examples and comparative examples.

【0011】(実施例)ホウケイ酸鉛系ガラスとアルミ
ナ粉末とを主成分としたグリーンシートに層間接続のた
めのビアホールを打ち抜き、ガラスフリットを含有する
銀ペーストを用いて内層回路パターンの印刷及びビアホ
ール内へのペースト充填を行った。(但し、最上層に使
用するグリーンシートには回路パターンの印刷を行わ
ず、ビアホール内へのペースト充填のみを行った。)次
いでこのグリーンシートを3枚積層し、プレスした後、
900℃の酸化雰囲気で焼成して一体化したセラミック
基板を得た。こうして得られたセラミック基板を180
℃の熱リン酸に5分間浸漬し、銀ペーストを焼成した導
体よりなるビア部の表面及びセラミック基板の表面を粗
面化処理した。この後、セラミック基板の表面に核付け
処理を行った後、無電解銅めっき液にセラミック基板を
浸漬し、膜厚10μmの銅めっき層を形成し、さらに、
この銅めっき層上にエッチングレジストを付与し、エッ
チング法で外層回路を形成して、4層構成(内層回路が
2層、外層回路が2層)のセラミック多層配線板を得
た。なお、このセラミック多層配線板は外層回路と内層
回路が256個のビア部を介して接続されていてる導通
回路を備えるよう作製した。
(Example) A via hole for interlayer connection was punched out in a green sheet mainly composed of lead borosilicate glass and alumina powder, and an inner circuit pattern was printed and a via hole was formed by using a silver paste containing glass frit. The inside was filled with paste. (However, the circuit pattern was not printed on the green sheet used for the uppermost layer, and only the paste was filled in the via holes.) Then, three green sheets were laminated and pressed,
By firing in an oxidizing atmosphere at 900 ° C., an integrated ceramic substrate was obtained. 180 thus obtained ceramic substrate
The surface of the via portion and the surface of the ceramic substrate made of a conductor obtained by firing a silver paste was roughened by immersing in hot phosphoric acid at ℃ for 5 minutes. After that, after performing a nucleating treatment on the surface of the ceramic substrate, the ceramic substrate is immersed in an electroless copper plating solution to form a copper plating layer having a film thickness of 10 μm.
An etching resist was applied on the copper plating layer, and an outer layer circuit was formed by an etching method to obtain a ceramic multilayer wiring board having a four-layer structure (two layers of inner layer circuit and two layers of outer layer circuit). The ceramic multilayer wiring board was manufactured so as to have a conduction circuit in which the outer layer circuit and the inner layer circuit were connected via 256 via portions.

【0012】(比較例)実施例で作製した、焼成して一
体化したセラミック基板に対して、熱リン酸による粗面
化処理を施さないようにした以外は前記の実施例と同様
にしてセラミック多層配線板を得た。
(Comparative Example) A ceramic was prepared in the same manner as in the previous example except that the ceramic substrate integrated by firing was not subjected to surface roughening treatment with hot phosphoric acid. A multilayer wiring board was obtained.

【0013】実施例及び比較例で得られたセラミック多
層配線板について下記の方法で接続信頼性の試験を行っ
た。得られた結果を表1に示す。表1の結果から実施例
のセラミック多層配線板は比較例のセラミック多層配線
板に比べ接続信頼性が優れていることが確認された。
The ceramic multilayer wiring boards obtained in Examples and Comparative Examples were tested for connection reliability by the following method. The results obtained are shown in Table 1. From the results in Table 1, it was confirmed that the ceramic multilayer wiring board of the example had better connection reliability than the ceramic multilayer wiring board of the comparative example.

【0014】(接続信頼性の試験方法)セラミック多層
配線板に対し、〔(室温、5分)→(125℃、30
分)→(室温、5分)→(−55℃、30分)→(室
温)〕を1サイクルとするヒートサイクル処理を行い、
所定のサイクル数を終了した後で、外層回路と内層回路
が256個のビア部を介して接続されていてる導通回路
について、その両端間の電気抵抗を4端子法で測定し、
抵抗変化率を算出する。施したサイクル数と抵抗変化率
の関係を表に集計して、接続信頼性を評価する。なお、
抵抗変化率の小さいものが接続信頼性が良好なものであ
る。
(Test method for connection reliability) For a ceramic multilayer wiring board, [(room temperature, 5 minutes) → (125 ° C., 30
Min) → (room temperature, 5 minutes) → (−55 ° C., 30 minutes) → (room temperature)] as one cycle,
After completing the predetermined number of cycles, the electrical resistance between both ends of the conductive circuit in which the outer layer circuit and the inner layer circuit are connected via 256 via portions is measured by the four-terminal method,
Calculate the rate of resistance change. The relationship between the number of cycles applied and the resistance change rate is tabulated and the connection reliability is evaluated. In addition,
The one with a small resistance change rate has a good connection reliability.

【0015】[0015]

【表1】 [Table 1]

【0016】[0016]

【発明の効果】請求項1及び請求項2に係る発明のセラ
ミック多層配線板の製造方法によれば、薄膜法で外層の
配線導体を形成する方法であって、外層の配線導体とビ
ア部を形成している厚膜法による導体との接続信頼性に
優れたセラミック多層配線板を製造することができる。
According to the method for manufacturing a ceramic multilayer wiring board of the present invention as defined in claims 1 and 2, a method for forming an outer layer wiring conductor by a thin film method is provided, in which the outer layer wiring conductor and the via portion are formed. It is possible to manufacture a ceramic multilayer wiring board having excellent connection reliability with the conductor by the formed thick film method.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 内部の配線導体を厚膜法で形成して一体
化したセラミック基板の表面に薄膜法で外層の配線導体
を形成するセラミック多層配線板の製造方法において、
外層の配線導体を形成する前に、前記セラミック基板の
表面を加熱リン酸を用いて粗面化処理することを特徴と
するセラミック多層配線板の製造方法。
1. A method for manufacturing a ceramic multilayer wiring board, wherein an inner wiring conductor is formed by a thick film method to form an integrated ceramic substrate, and an outer wiring conductor is formed on the surface of the ceramic substrate by a thin film method.
A method for manufacturing a ceramic multilayer wiring board, characterized in that the surface of the ceramic substrate is roughened with hot phosphoric acid before forming the outer layer wiring conductor.
【請求項2】 セラミック基板の表面を粗面化処理する
加熱リン酸の温度が140〜360℃であることを特徴
とする請求項1記載のセラミック多層配線板の製造方
法。
2. The method for producing a ceramic multilayer wiring board according to claim 1, wherein the temperature of the heated phosphoric acid for roughening the surface of the ceramic substrate is 140 to 360 ° C.
JP21890795A 1995-08-28 1995-08-28 Production of multilayered ceramic wiring board Withdrawn JPH0964541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21890795A JPH0964541A (en) 1995-08-28 1995-08-28 Production of multilayered ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21890795A JPH0964541A (en) 1995-08-28 1995-08-28 Production of multilayered ceramic wiring board

Publications (1)

Publication Number Publication Date
JPH0964541A true JPH0964541A (en) 1997-03-07

Family

ID=16727190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21890795A Withdrawn JPH0964541A (en) 1995-08-28 1995-08-28 Production of multilayered ceramic wiring board

Country Status (1)

Country Link
JP (1) JPH0964541A (en)

Similar Documents

Publication Publication Date Title
JP2989975B2 (en) Method for manufacturing aluminum nitride substrate
JPS6342879B2 (en)
JP2000182883A (en) Manufacture of laminated ceramic electronic component
JPH0964541A (en) Production of multilayered ceramic wiring board
JPS63144554A (en) Manufacture of thick-film hybrid integrated circuit substrate
JP2001015895A (en) Wiring board and its manufacture
JP2842711B2 (en) Circuit board
JP4595183B2 (en) Ceramic electronic component and method for manufacturing the same, multilayer ceramic electronic component and method for manufacturing the same
JP2734404B2 (en) Ceramic wiring board and method of manufacturing the same
JPH10256731A (en) Manufacture of ceramic multilayer circuit board
JP2012049187A (en) Ceramic multi-layer substrate and manufacturing method of the same
JP3089961B2 (en) Copper metallization of ceramic substrates
JP2002016329A (en) Wiring board and its manufacturing method
JPH09260847A (en) Ceramic multilayered wiring board manufacturing method
JPH0555750A (en) Multilayer printed circuit board and manufacture of the same
JP3284868B2 (en) Copper metallization of ceramic substrates
JP2931910B2 (en) Circuit board
JP2000030971A (en) Chip type electronic component and its manufacture
JP2842710B2 (en) Circuit board
JPH02284499A (en) Partially multilayered ceramic printed wiring board
JPS63275196A (en) Manufacture of circuit substrate
JPH0151075B2 (en)
JPS6052095A (en) Multilayer circuit board and method of producing same
JPS61121389A (en) Ceramic wiring board
JPS60154595A (en) Method of producing multilayer circuit board

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20021105