JPH04132414A - Prevention circuit for unstable setting - Google Patents

Abstract

PURPOSE:To prevent unstable setting due to chattering by applying exclusive NOR to N-bit data of a shift register so as to discriminate whether or not the N-bit data of the shift register are coincident. CONSTITUTION:The circuit is provided with a clock generating circuit 2, an N-bit shift register 3 sampling the logical setting state with a clock from the circuit 2 and storing the data, and an exclusive NOR circuit 9 discriminating whether or not data stored in the shift register 3 are all coincident with each other, a gate circuit 7 controlling the block or passing of the clock from the generating circuit 2 with an output of the circuit 9, and a latch circuit 8 latching and outputting the data at the final stage of the shift register 3 with a clock passing through the gate circuit. In this case, when a switch 1 is set to a low level at a time t1, the setting content by a setting section 10 changes with chattering, and 0s and 1s exist in mixture in an output of the shift register 3 and an output of the exclusive NOR circuit 9 goes to '0'. Thus, unstable setting due to chattering is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic holding circuit for a digital circuit, and particularly to a circuit for preventing unstable setting in logic setting.

[Conventional technology]

Logic holding circuits provide signals of different levels. That is, this type of logic holding circuit has a configuration in which a DC signal of logic level "1" or "O-P" is applied to an operating digital circuit using a switch or the like.

(Problems to be Solved by the Invention) Conventional logic setting circuits perform logic setting using continuous DC level signals.In other words, if the setting signal is continuously "0" or "1", there is no problem. There isn't.

Incidentally, the digital circuit to be set may be manually set using a toggle switch or the like.

An example of such a logic setting circuit is shown in the third circle. FIG. 3 shows a case where the setting section 10 is provided with the logic setting switch 1, and the section to be set 20 includes a digital circuit whose logic should be set. In such a case, there is a problem that the logic setting becomes unstable due to chattering the moment the switch 1 is activated.

An object of the present invention is to provide an unstable setting prevention circuit for avoiding the above-mentioned problems.

[Means to solve the problem]

The present invention is an unstable setting prevention circuit that prevents instability of logic settings caused by a changeover switch, and includes a generator circuit that generates a clock, and N bits that sample logic settings using the clock from the generator circuit and store data. a shift register, a determination circuit that determines whether all data stored in the shift register match, and a gate circuit that controls blocking or passing of the clock of the generation circuit using the output of the determination circuit; The device is characterized in that it has a holding port which holds and outputs the data of the final stage of the shift register using the clock that has passed through the gate circuit.

In the present invention described above, the determination circuit performs an exclusive NOR operation on the N-bit data of the shift register and determines whether the N-bit data of the shift register match. suitable.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. 1st
The unstable setting prevention circuit shown in the figure includes a setting section 10 and a set section 20.

The set section 20 includes an 8-bit shift register 3 that samples logic settings with a clock and stores digital data, and an exclusive NOR circuit that determines whether all outputs of the shift register 3 match.
:hereinafter referred to as EX-NOR circuit) 9 and this EX
-The clock control NAND circuit 7 that blocks the clock from the output clock generation circuit 2 of the NOR circuit 9 and the final data of the shift register 3 are
The output flip-flop (FF) 8 performs retiming using a clock controlled by the output of the R circuit 9.

The EX-NOR circuit 9 includes an AND circuit 4, a NOR circuit 5, and an OR circuit 6.

Then, in the set section 20, the Q of the shift register 3 is
The output terminals are connected to input terminals of AND circuit 4 and NOR circuit 5, respectively. The Q output terminal of the final stage is further connected to the D input terminal of the flip-flop 8.

In the EX-NOR circuit 9, AND circuit 4 and N
The output terminal of OR circuit 5 is connected to the input terminal of OR circuit 6. The output terminal of the OR circuit 6 is connected to the NAND circuit 7.
is connected to the other input terminal of The output terminal of the NAND circuit 7 is the clock input terminal CL of the flip-flop 8.
It is connected to the.

The setting section 10 is provided with a logic setting switch 1 and a sampling clock generation circuit 2. The logic setting switch 1 is connected to the input terminal of the shift register 3. The clock generation circuit 2 is connected to the clock input terminal CK of the shift register 3 and one input terminal of the clock control NAND circuit 7.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG. FIG. 2 is a time chart showing when the logic setting switch 1 is operated from high level to low level.

The sampling clock generation circuit 2 generates a clock having a shorter period than the chuck ring generated by the switch operation. First, when the setting section 10 is set to a high level, the logic setting switch l is set to the high level as shown in FIG.
As shown in a), it is set to a high level. This setting information (logical setting) is input to the shift register 3,
The data is sampled and stored using the clock from the sampling clock generation circuit 2 as shown in FIG. 2(b).

The data in the shift register 3 after sampling is shown in FIG. 3(C). In this case, all Q outputs of the shift register 3 are "1". Therefore, the output of the EX/NOR circuit 9 is "1" as shown in FIG. 2(d).

As a result, as shown in Figure 2 (el), NANDAN
The clock from the D-circuit lock generation circuit 2 is passed through and inputted to the clock input terminal CL of the flip-flop 8. With this clock, the flip-flop 8 correctly takes in the final data of the shift register 3, retimes it, and outputs it.

The Q output of the flip-flop 8 is shown in FIG. 2(f).

When switch 1 starts to operate to low level at time t,
The setting contents by the setting unit 10 change by chucking, and the output of the shift register 3 becomes a mixture of "1" and "°O" as shown in FIG. 2(C). EX-NO
The output of the R circuit 9 becomes "0" as shown in the second diagram. Therefore, in order to prevent the NANDAND circuit from locking, the flip-flop 8 holds the data before chucking, that is, "1".As a result, the Q output of the flip-flop 8 is as shown in FIG. As shown in (f), it is kept in a high state.

When chatter stops occurring at time 1t, all outputs of the shift register 3 become “
0'', and the output of the EX-NOR circuit 9 is as shown in Figure 2 (d
) as shown in ``1''. Therefore, NANDA
Passing the ND circuit lock, the Pfronop 8 retimes the data in the final stage of the shift register 3, and
Change the output to low as shown in Figure 2).

The above embodiment deals with the case where the logic setting switch 1 is set from high to low, but even when the logic setting switch 1 is set from low to high, unstable setting due to chuckling can be prevented for the same reason.

〔Effect of the invention〕

As explained above, according to the present invention, when the logic setting is changed using the switch/7 switch, it is possible to prevent unstable setting due to the chuck ring.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
A time chart illustrating the operation when the switch in FIG. 1 is set from a high level to a low level. FIG. 3 is a circuit diagram showing an example of a logic setting prevention circuit. 1...Logic setting switch 2...Sampling clock generation circuit 3...8-bit shift register 4...AND circuit 5...NOR circuit 6...OR circuit 7...NANDAND D circuit・Flip-flop 9...EX-NOR circuit 10...Setting section 20...Setting section agent Patent attorney Yoshiyuki Iwasa

Claims (2)

[Claims] (1) An unstable setting prevention circuit that prevents unstable logic settings caused by a changeover switch, which includes a generator circuit that generates a clock, and an N-bit circuit that samples the logic settings using the clock from the generator circuit and stores data. a shift register; a determination circuit that determines whether all data stored in the shift register match; a gate circuit that uses the output of the determination circuit to control blocking or passing of the clock of the generation circuit; An unstable setting prevention circuit comprising: a holding circuit that holds and outputs data in the final stage of the shift register using a clock that has passed through a gate circuit. (2) The determination circuit according to claim 1, wherein the determination circuit performs an exclusive NOR operation on the N-bit data of the shift register, and determines whether the N-bit data of the shift register match. Unstable setting prevention circuit.