KR940008663B1 - Cyclic permutable cordward data detection circuit - Google Patents

Abstract

The cyclic permutable cordward data detecting circuit in a cable communication system, for preventing a repeated cyclic permutable cordward data detection and for reducing load of a processor includes a divider, a latch clock generator, a clock supply controller, a first serial and parallel converter, a first latch, a buffer, a comparator, a second latch, a valid bit signal generator, a tri-state buffer and a clock holder.

Description

Cyclic repeat codeword data detection circuit

1 is a conventional CPC data detection circuit diagram.

2 is a waveform diagram of operating parts of FIG.

3 is a CPC data detection circuit diagram according to the present invention.

4 is an operation waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10: frequency divider 20: first shift register

30: first latch 40: buffer

50: comparator 60, 80, 90: flip-flop

70: second shift register 100: latch clock generating means

110: clock supply control unit 120: clock holding means

The present invention relates to a Cyclic Permutable Cordward (CPC) data detection circuit in a wired communication system. In particular, the present invention relates to a CPC data which prevents detection of duplicate CPC data when the same data is duplicated and input after detecting CPC data. It relates to a detection circuit.

Conventionally, as shown in FIG. 1, when the power is turned on, the flip-flop 6 is cleared so that the flip-flop 6 outputs a low signal to the output terminal Q. When the low signal output to the output terminal Q of the flip-flop 6 is applied to the reset terminal R of the second shift register 7 through the AND gate AN4, the second shift register 7 is applied. Is reset to output the low signal to the output terminal Q4. The low signal output from the second shift register 7 is inverted through the inverter I4 and applied to one terminal of the AND gates AN1 and AN3 and the NAND gate NA1, respectively. At this time, the clock signal of 32KHZ as shown in FIG. 2 (a) generated from a clock generator (not shown) is divided by the divider 1, and the first clock signal 16KHZ as shown in FIG. The second clock signal TC as shown in FIG. 2C is output. The first clock signal 16KHZ output from the divider 1 is applied to the clock terminal cp of the first shift register 2 through an AND gate AN1, and the second clock signal TC is NAND. It is applied to the clock terminal cp of the latch 3 through the gate NA1. In addition, the 32KHZ clock signal generated from the clock generator is inverted through the inverter I1 and applied to one terminal of the shift register AN2. As a result, the shift register AN2 is logically summed with the second clock signal TC output from the divider 1 and is output. The OR-signal output from the shift register AN2 is applied to the clock terminal cp of the flip-flop 6 through the shift register AN3. At this time, the first shift register 2 which inputs CPC data as shown in FIG. 2 (d) from the processor is shifted by the first clock signal 16KHZ and outputs 8 bits of the output terminals Q ₀ -Q ₇ . Output parallel data.

The latch 3 for inputting the parallel data output from the first shift register 2 is latched by the second clock signal TC input through the NAND gate NA1, and outputs the NAND gate NA1. It will latch on this rising edge. Data latched to the output terminals Q ₀ -Q ₇ of the latch 3 is stored in the buffer 4. In this case, when the second clock signal TC is inverted through the inverter I2 in the frequency divider 1 and a signal such as the second diagram 2e is applied to the enable terminal EN of the comparator 5, the comparator (5) is enabled and the previous state latched from the latch (3) input to the current CPC data and the input terminal (B) shifted in the first shift register (2) input to the input terminal (A) Compare the CPC data. At this time, if the two data are the same, the comparator 50 outputs a "low" signal as shown in FIG. 2 (2g), and if the two data are different, it outputs a "high" signal as shown in FIG. . Since the two data are the same, the low signal output from the comparator 5 is inverted through the inverter I3 and applied to the data terminal D of the flip-flop 6. The flip-flop 6 which inputs the inverted high signal through the inverter I3 is latched in synchronization with a clock signal such as the second diagram 2f output through the AND gate AN3. The high signal latched by the flip-flop 7 is input to the second shift register 7 and converted into parallel data, and the same data is continuously repeated five times compared to the CPC data input from the comparator 5. Since the output of the comparator 5 is in the low state, the output terminal Q4 of the second shift register 7 is in the high state. Since the high signal output to the output terminal Q4 of the second shift register 7 is inverted through the inverter I4 and applied to the AND gates AN1 and AN #, the first shift register 2 and the latch 3 are applied. ), The clock supply of the flip-flop 6 is cut off.

At this time, the processor generates a second control signal at a predetermined period to enable the three-state buffer B1 and checks the inverted output of the bit bit in the inverter I4. Therefore, the processor reads the CPC data stored in the buffer 4 by determining that the Belize bit is valid data when the Belize bit is low. The processor resets the second shift register 7 by reading the CPC data from the buffer 4 and generating a first control signal. However, the comparator 5 outputs a high signal when the data is different while repeatedly comparing the CPC data input from the comparator 5 five times. When the output of the comparator 5 becomes a high signal, the output of the flip-flop 6 goes low to reset the second shift register 7. When the shift register 6 is reset, the output of the output terminal Q4 goes low and is inverted through the inverter I4 to become a high signal. Therefore, the processor senses that the shift register 6 is not valid data, thereby detecting the CPC data of the buffer 4. Will not be read.

In the conventional CPC data detection circuit, if the CPC data is detected more than a certain number of times, the CPC data is determined to be a valid data. There was a problem that the load of the increased.

It is therefore an object of the present invention to provide a CPC data detection circuit which reduces the load on the processor.

Another object of the present invention is to provide a CPC data detection circuit for preventing duplicate detection of the same CPC data.

The present invention for achieving the above object divides the system clock signal and outputs the first clock signal and the second clock signal (TC), and the inverted system clock signal outputted from the divider 10 Latch clock generating means for outputting a latch clock signal in logical combination with a first clock signal, a first clock signal and a second clock signal TC which are outputs of the division means, and a latch clock signal output from the latch clock generating means. Clock supply control means for controlling the supply by means of a beaded bit signal, and inputting serial CPC data to the output terminals Q ₀ -Q ₇ by the first clock signal supplied from the clock supply control means. A first serial / parallel conversion means for converting and outputting parallel data, and parallel data output from the first serial / parallel conversion means to be latched in synchronization with the second clock signal TC inverted by the clock supply control means; The first latch means, A buffer means for storing a signal output from the first latch means, a parallel CPC data converted by the first serial / parallel conversion means, and data latched by the latch means to detect whether the data is equal or not; Means, a second latch means for inverting the data comparison detection signal output from the comparison means and latching the latch by the latch clock signal output from the latch clock generation means, and a signal latched by the second latch means Belize bit signal generating means for converting into 8-bit parallel data by the second clock signal TC output from the dividing means and outputting a bead bit signal, and a bead output from the bead bit signal generating means. A tri-state buffer that inputs a bit signal and buffers the output by a second control signal output from the processor, and a data comparison detection signal output from the comparison means And a clock hold means for holding the second clock signal TC supplied to the second serial / parallel means to prevent duplicate detection of CPC data by the latch clock signal outputted from the latch clock fish means. It is characterized by.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a CPC data detection circuit diagram according to the present invention, which divides a 32KHZ clock signal generated from a clock generator (not shown) and outputs a first clock signal 16KHZ and a second clock signal TC ( 10) and the inverter (I1) and the AND gate (AN2) invert the clock signal of 32KHZ and logically combines the first clock signal (16KHZ) output from the divider (10) to provide a latch clock signal. The first clock signal (16KHZ) and the second clock signal (TC), which are outputs of the divider 10, are composed of an output latch clock means 100, an AND gates AN1 and AN3, and a NAND gate NA1. And the clock supply control means 110 for controlling the supply of the latch clock signal output from the latch clock generation unit 100 by a beaded bit signal, and the serial CPC data to be input to the clock supply control means 110. ) converted into parallel data of 8 bits to the output terminals (Q ₀ -Q ₇₎ by a first clock signal (16KHZ) supplied by the output A second clock signal TC inverted by the clock supply control unit 110 by inputting the first serial / parallel conversion means comprising the first shift register 20 and the parallel data output from the first serial parallel means; Latches latched in synchronism with the first latch 30, a buffer 40 for storing signals latched by the first latch 30, and a second clock signal TC output from the divider 10. Inverter I2 for inverting and applying the enable signal of the comparator 5 and parallel CPC data converted by the first serial / parallel conversion means when the enable signal output from the inverter I2 is supplied. A comparator 50 for detecting whether the data is identical by comparing the data latched by the first latch 30, an inverter I3 for inverting and outputting a comparison output signal output from the comparator 50, and the inverter The latch output from the latch clock generation unit 100 outputs the comparison output signal inverted and output from (I3). A second latch means comprising a flip-flop 60 latched by a clock signal, and a second clock signal TC output from the divider 10 by inputting a signal latched by the flip-flop 60. A second serial / parallel conversion means comprising a second shift register 70 for converting 8-bit parallel data and outputting a valid data detection signal to an output terminal Q4, and outputted from the second shift register 70; Inverter I4 which inverts the valid data detection signal and outputs the bead bit signal, and tri-state which buffers and outputs the bead bit signal output from the inverter I4 by buffering the second control signal output from the processor. A latch composed of a buffer B1, flip-flops 80 and 90, and an AND gate AN5-AN6 and receiving a comparison output signal inverted from the inverter I3 and output from the latch clock generation unit 100. After CPC data is detected by the clock signal, The clock holding means 120 for holding the second clock signal TC supplied to the second shift register 70 until the CPC data is input, and the signal latched by the first latch 30 are received. Exclusive orifice EX1 for detecting that the CPC data is not input and outputting the reset signal of the second shift register 70.

4 is an operation waveform diagram of each part of FIG.

Hereinafter, an operation of an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

Since the flip-flop 60 is cleared when the power is turned on, the flip-flop 60 outputs a low signal to the output terminal Q, and the power supply signal is set through the AND gate AN6. Is applied to the terminal PRE to preset the flip-flop 90 to output a high signal to the output terminal (Q). When the low signal output to the output terminal Q of the flip-flop 60 is applied to the reset terminal R of the second shift register 70 through an AND gate AN4, the second shift register 70 is applied. Is reset to output the low signal to the output terminal Q4. The low signal output from the second shift register 70 is inverted through the inverter I4 to be a terminal of the clear terminal CL, the AND gates AN1, AN3, and the NAND gate NA1 of the flip-flop 90. Each is applied. At this time, the 32KHZ clock signal generated from the clock generator not shown in FIG. 4A is divided by the divider 10 so that the first clock signal 16KHZ and the first clock signal shown in FIG. The second clock signal TC as shown in FIG. 4C is output. The first clock signal 16KHZ output from the divider 1 is applied to the clock terminal CP of the first shift register 20 through an AND gate AN1 and the second clock signal TC is NAND. It is applied to the clock terminal CP of the first latch 30 through the gate NA1. In addition, the clock signal of 32KHZ generated from the clock generator is inverted through the inverter I1 and applied to one terminal of the AND gate AN2. As a result, the AND gate AN2 is output in combination with the second clock signal TC output from the divider 10. The AND-output signal from the AND gate AN2 is applied to the clock terminal CP of the flip-flop 60 through the AND gate AN3. At this time, the first shift register 20 for inputting CPC data as shown in FIG. 4D from the processor is shifted by the first clock signal 16KHZ and outputs 8 bits of output terminals Q ₀ -Q ₇ . Output parallel data. The first latch 30 for inputting the parallel data output from the first shift register 20 is latched by the second clock signal TC input through the NAND gate NA1. The output is latched at the rising edge. Data latched to the output terminals Q ₀ -Q ₇ of the first latch 30 are stored in the buffer 40. In this case, when the second clock signal TC output from the divider 10 is inverted through the inverter I2 and a signal such as FIG. 4E is applied to the enable terminal EN of the comparator 50. The comparator 50 is enabled and latched at the first latch 30 inputted to the current CPC data inputted to the input terminal B and the current CPC data shifted from the first shift register 20 inputted to the input terminal A. Compare the output CPC data of the previous state. At this time, if the two data are the same, the comparator 50 outputs a "low" signal as shown in FIG. 4 (4g), and if the two data are different, it outputs a "high" signal as shown in FIG. 4 (4g). . Since the two data are the same, the low signal output from the comparator 50 is inverted through the inverter I3 and applied to the data terminal D of the flip-flop 60.

The flip-flop 60 inputting the inverted high signal through the inverter I3 is latched in synchronization with a clock signal such as the fourth diagram 4f output through the AND gate AN3. The high signal latched by the flip-flop 60 is input to the second shift register 70 and converted into parallel data by the second clock signal output from the divider 10. When the CPC data is repeatedly compared five times and the same data continues, the output of the comparator 50 is in a low state, so the output terminal Q4 of the second shift register 70 is in a high state. Since the high signal outputted to the output terminal Q4 of the second shift register 70 is inverted through the inverter I4 and a low signal is applied to the AND gates AN1 and AN3, the first shift register 20 and the first signal are output. The clock supply of the first latch 30 and the flip-flop 60 is cut off. In addition, the low signal inverted through the inverter I4 is applied to the clear terminal CL of the flip-flop 90 to clear the flip-flop 90. When the flip-flop 90 is cleared, the low signal is output to the output terminal Q to block the second clock signal supplied to the second shift register 70. At this time, the processor generates a second control signal at a predetermined period to enable the three-state buffer B1 and checks the bead bit inverted and output from the inverter I4. Accordingly, the processor reads the CPC data stored in the buffer 40 by determining that the bead bit is valid data when the bead bit is low. The processor resets the second shift register 70 by reading the CPC data from the buffer 40 and generating a first control signal. After performing the above operation, if the current data inputted to the comparator 50 and the data of the previous state are the same, the comparator 50 outputs a low signal. Since the low signal output from the comparator 50 is inverted through the inverter I3 and applied to the data terminal D of the flip-flop 80, the flip-flop 80 is output through the AND gate AN3. The high signal is output to the output terminal Q by being latched by the clock signal as shown in FIG. Since the high signal output from the flip-flop 80 is applied to the set terminal PRE of the flip-flop 90 through the AND gate AN6, the flip-flop 90 receives the low signal to the output terminal Q. The output block cuts the second clock signal supplied to the clock terminal CP of the second shift register 70. When the clock signal supplied to the clock terminal CP of the flip-flop 90 is blocked, the operation of the second shift register 70 is stopped. When the operation of the second shift register 70 is stopped, the signal of the output terminal Q4 of the second shift register 70 goes low. As a result, the bead bit signal inverted through the inverter I4 becomes high, so that the processor does not read CPC data stored in the buffer 40. However, when new data is input while iteratively comparing the CPC data input to the comparator 50, the comparator 50 outputs a high signal. The high signal output from the comparator 5 is inverted through the inverter I3 and thus becomes a low signal and applied to the data terminal D of the flip-flop 80. As a result, the flip-flop 80 outputs a low signal to the output terminal Q to preset the flip-flop 90, so that the flip-flop 90 outputs a high signal. When the flip-flop 90 outputs a high signal, the second clock signal output from the divider 10 is supplied to the clock terminal CP of the second shift register 70. In this state, if the same data is detected by repeatedly comparing the current data input from the comparator 50 with the data of the previous state five times, since the bead bit goes low as described above, the processor generates a second control signal. Is generated to enable the tri-state buffer B1 to detect new CPC data stored in the buffer 40.

When 00 or FF, which is not used for CPC data detection, is input, the output of the exclusive oracle EX1 becomes a low signal. The low signal of the exclusive oragate EX1 is applied to the reset terminal R of the second shift register 70 through an AND gate AN4 to reset the second shift register 70. Prevent CPC data detection.

As described above, if the CPC data is detected more than a certain number of times in the wired communication system, it is determined that the data is valid. This has the advantage of reducing the load on the processor.

Claims (2)

In the CPC data detection circuit of a wired communication system, a divider means for dividing a system clock signal to output a first clock signal and a second clock signal TC, and inverting the system clock signal to divide the system clock signal. A latch clock generating means for logically combining the first clock signal outputted from the first clock signal and outputting the latch clock signal, the first clock signal and the second clock signal TC which are outputs of the division means, and the latch clock generating means outputted from the latch clock generating means. Clock supply control means for controlling the supply of the latch clock signal by the beaded bit signal, and inputting serial CPC data to the output terminals Q ₀ -Q ₇ by the first clock signal supplied from the clock supply control means. A first serial / parallel conversion means for converting and outputting 8-bit parallel data and parallel data output from the first serial / parallel conversion means to synchronize with the second clock signal TC inverted by the clock supply control means; Latching 1 latch means, buffer means for storing the signal output from the first latch means, parallel CPC data converted by the first serial / parallel conversion means and data latched by the latch means are compared or not. Comparison means for detecting a state, second latch means for inverting the data comparison detection signal output from the comparison means, and latching it by the latch clock signal output from the latch clock generation means, and latching in the second latch means. A beaded bit signal generating means for converting an 8-bit parallel data into a parallel bit data by the second clock signal TC outputted from the dividing means and outputting a beaded bit signal, and the beaded bit signal generating means A three-state buffer for inputting the beaded bit signal outputted from the buffered output by the second control signal outputted from the processor, and the data ratio A clock holding means for receiving the detection signal and holding the second clock signal TC supplied to the second serial / parallel means in order to prevent duplicate detection of CPC data by the latch clock signal output from the latch clock generating means; Circuit characterized in that the configuration. 2. The exclusive oragate of claim 1, further comprising: receiving an latched signal from the first latching means, detecting an unused CPC code to generate a reset signal of the second serial / parallel means; And EX1).