KR920000412B1 - Frequency discrimination circuit - Google Patents

Abstract

The circuit checks that the frequency of input ring signal is in the predetermined frequency range to generate a ring enable signal for the system. The circuit includes a ring input signal control circuit (1) for digitizing analog ring input signal (Rin), a random counter (7) for counting the frequency of the input ring signal to generate address signals, a complex logic unit (11) for generating upper and lower frequency limit signals according to the upper and lower frequency limit control signals, a first clock signal generator (100) for providing clock signal (CK) to the random counter (7) , a first data signal generator (10) for generating a first data signal using the limit signals; a second data signal generator (103) for generating a second data signal by inverting the output signal of the ring input signal processing circuit (1).

Description

Frequency selection circuit

1 is a frequency selection circuit diagram according to the present invention.

2 is a detailed view of a ring input circuit used in FIG.

3 is a waveform diagram of a ring enable signal according to Rin '.

* Explanation of symbols for the main parts of the drawings

1: ring input circuit 7: random counter

11: Composite Logic 16,17,26: D-Flip Flop

100: first clock signal generator 101: first data signal generator

102: second clock signal generator 103: second data signal generator

104: half cycle signal generator 105: ring enable signal generator

The present invention relates to a frequency sorting circuit for generating a signal for enabling a system when a signal inputted by a user is set within a frequency range desired by a user.

In order to operate a system, a user had to apply an input signal directly to the system or receive an enable signal from another system. For example, in the conventional telephone, in order to enable the ring circuit, a hysteresis characteristic according to the increase or decrease of the power supply voltage is used, and thus the user cannot select a desired frequency.

Accordingly, an object of the present invention is to provide a frequency selection circuit for generating an enable signal of a system when an input signal comes within a set frequency range after setting a frequency range desired by a user.

In order to achieve the above object, the present invention provides a ring input signal processing means for generating an analog large ring input signal (Rin) as a small digital signal (Rin ') through a Schmitt trigger, and when the power supply voltage becomes an operation start voltage. Random counter means for generating a predetermined counter output, combined logic for setting the upper and lower limit levels of the input frequency, and signals for controlling the lower and upper limit frequencies are generated so that the digital signal Rin ' If it is between the lower limit, it consists of a control means for generating a ring enable signal for system operation.

Hereinafter, the technical configuration of the present invention will be described in detail with reference to the accompanying drawings.

와 Rin'이 하이상태일 경우 하이상태의 링인에블 신호(REN)를 발생시키는 역할을 한다.FIG. 1 is a detailed diagram of a frequency selection circuit according to the present invention. In FIG. 1, reference numeral 1 is a ring input signal processing circuit, and the random counter 7 is operated by an operation bias voltage VEN to provide a plurality of addresses. Generating signals Fψ-En and Fψ-Fn, and reference numeral 100 denotes a NOR gate 8 and 9 and a NAND gate 10 for providing an output signal CK to the random counter 7. The first clock signal generation unit 101 is configured to logically combine the upper limit frequency signal fUDL, the lower limit frequency signal fUDL, and the inhibit signal INH generated by the composite logic 11 to generate the first data signal. The first data signal generator includes the NOR gates 30, 31, 32, 33, 34, and 35, the inverter 33, and the flip-flop 16. Reference numeral 102 denotes a second clock generator, 103 denotes a second data signal generator, 104 denotes a semi-period signal generator, and 105 denotes a ring enable signal generator. As shown in FIG. 1, the analog ring input signal Rin is applied to the ring input circuit 1, and is then converted into a predetermined digital signal Rin 'by the ring input circuit 1 to generate an AND gate. As input to (2), the ring input circuit 1 will be described later. The output terminal of the AND gate 2 is connected to one input terminal of the NOA gate 3, and the output terminal of the NOGATE 3 is connected to the inverter 4, and these logic circuits disable the frequency selection circuit. In other words

When Rin 'and Rin' are high, the ring in enable signal REN is generated.

ψ-

,Fψ-Fn)를 제공하고, 복합로직(11)의 출력신호(FUDL,FLDL,F11,INH,Fn-2

Fn)중 Fn-2와 Fn를 익스클루시브오아(exclusive OR)한 신호(Fn-2

Fn)로서 D- 입력을 공급받는다.On the other hand, the operation start voltage VEN is inverted by the inverter 5 and then connected to the reset terminal RST of the random counter 7 via the ora gate 6 and at the same time the NAND and the NAND gates 8 and 9. It is connected to the clock terminal CK of the random counter 7 via the gate 10. The random counter 7 is composed of n + 1 D-flip flops, and 2 (n) to the complex logic 11. +1 address signals (

ψ-

, Fψ-Fn) and the output signals of the composite logic 11 (FUDL, FLDL, F11, INH, Fn-2)

Signal Fn-2 and Exclusive OR of Fn-2 and Fn (Fn-2

Fn) is supplied with the D- input.

Fn)단자를 갖는바, 이 복합로직(11)은 랜덤카운터(7)의 출력을 산출하여 필요한 주파수를 제어할 수 있는 롬(ROM)으로 구성될 수 있다.The composite logic 11 has select terminals (FDHψ-FDHn-1, FDLψ-FDLn-1) capable of controlling n lower limit frequencies and upper limit frequencies, respectively, and the above-described output signals (FUDL, FLDL, F11, INH, Fn-). 2-

Having a terminal Fn), the complex logic 11 may be configured as a ROM capable of controlling the required frequency by calculating the output of the random counter 7.

The composite logic 11 is connected to the noar gates 12 and 13 for generating a low signal by logically combining the signals output from the output terminal F11 whenever the random counter 7 starts counting and reset. An output terminal of the noah gate 12 is connected to an oragate 14 for logically combining the lower limit frequency signal FLDL and the output signal of the noah gate 12, and the output of the oragate 14 is an exclusive oragate ( It is connected to one terminal of the 15) and the D-flip flop (16).

On the other hand, whether the signal Rin 'is changed from the high state to the low state or the low to high state, a plurality of logic gates 18-24 for inputting the input of the flip-flop 17 to only the signal that changes from low to high ) Is connected to the D-input terminal of the flip-flop 17, the inverter 25 is connected to the clock terminal CK thereof, and the D-flip-flop 26 and the ex-closure are connected to the output terminal of the D-flop flop 17. The sheave oA gate 27 and the AND gate 28 are connected to make the signal FLC high by a half period of the clock fs whenever the signal Rin 'rises from a low state to a high state.

The output terminal of the AND gate 28 is connected to the NOA gate 32 via the inverter 29 and the NOA gates 30 and 31 for inhibiting the upper limit frequency, and the NOA gate to which the inverter 33 is connected. An output terminal of the (32) is connected to the N-gates (34, 35) for providing a D- input to the D-flop flop (16), the D-flop flop (16) is a positive clock (CK) terminal is the inverter 36 It is connected to the output terminal of the exclusive oragate 15 via.

FIG. 2 is a detailed view of the ring input circuit 1 used in FIG. This ring input circuit converts the analog ring input signal b as shown in FIG. 2A into a digital signal. Since the input of the ring circuit is very large, in order to use this input in the MOS circuit, a component element capable of withstanding surge voltage must be used. That is, the ring input signal b (FIG. 2A) is converted into a ring signal through the capacitor 101, the resistor 102, the protective diode 103, and the resistor 104, and then through the diodes 105 and 106, the MOS transistor ( 107-109). A bias voltage Vb is applied to the gates of the transistors 017 and 108, and an inverter 110 is connected to the gate terminal of the transistor 109 to form a Schmitt trigger, and the signal from the inverter 110 is inverted to signal Rin '. Is connected to the inverter 111 for generating ().

The operation of the present invention configured as described above will be described.

First, when the frequency selection circuit is enabled, that is, when the frequency selection enable signal FDE is set low, when the power supply voltage becomes the operation start voltage VEN, the operation start voltage detection circuit (not shown) Becomes high and is inverted low by the inverter 5 and is applied to the reset terminal RST of the random counter 7 through the ora gate 6 to release the reset of the random counter 7. In addition, the output signal of the inverter is applied to the NAND gate 10 through the NOA gates 8 and 9, and a high state signal is applied to the input of the NAND gate 10 so that the clock terminal of the random counter 7 ( Fs is applied to CK).

ψ,

ψ-Fn,Fn)을 받아서 정해진 카운터 출력이 발생할때만(즉 클럭주기만큼) 하이상태의 출력을 발생시키게 되는바, 피이드백 되는 Fn-2

Fn값과 클럭에 대한 랜덤카운터(7)의 출력을 산출하여 필요한 주파수를 조절하게 된다.At this time, the composite logic 11 outputs the random counter 7

ψ,

ψ-Fn, Fn) generates a high-state output only when a predetermined counter output occurs (that is, by a clock cycle).

The output of the random counter 7 for the Fn value and the clock is calculated to adjust the required frequency.

When an output signal is generated from the random counter 7 (the count starts), whenever the counter is reset, the prohibit terminal INH of the compound logic 11 goes high and the low signal is transmitted through the noah gate 35. Is provided to the D-input terminal of the D-flop flop 16 so that there is no output of the D-flop flop 16.

However, when the prohibition terminal INH goes high and the clock goes high from the 11th, the output terminal F11 of the compound logic 11 outputs a high state signal and is applied to the noar gate 12. If the node goes low and the initial value of the ring input (Rin ') is low, nodes ② and ③ remain low.

In this state, the low signal of the node No. 1 is inverted high by the inverter 21 and applied to one input terminal of each of the AND gates 22 and 23. However, since node # 3 and the ring input signal Rin 'are low, the outputs of the respective AND gates 22 and 23 are simultaneously low. Therefore, the D-input of the D-flip-flop 17, which is the output of the exclusive oar gate 24, goes low and becomes the Rin 'input itself. However, if the initial value of Rin' is high, the nodes ② and ③ Becomes high, so the D-input of the D-flop flop 17 becomes the opposite waveform to the Rin 'input. This is to ensure that the input of the D-flip-flop 17 only enters the signal that changes from low to high, whether the Rin 'signal changes from high to low or from low to high.

Each time the ring signal Rin 'rises from low to high, the signal FLC goes high by half a period of the clock fs. This signal passes through the random counter 7 through the oragate 6. Reset, provide a clock signal to the D-flip flop 16 through the inverter 29, the exclusive oar gate 15 and the inverter 36, enter the noa gate 30, and then change to a high state. The node ④, which has disabled the upper limit frequency fDUL, is set to the low state and inputted to the noah gate 32. Therefore, the upper limit frequency (fUDL) value can pass through node ⑤. This is done after the first signal Rin 'is risen so that the output values corresponding to each of the upper and lower limits can be applied to the system.

A process for generating the ring enable signal REN will be described in more detail with respect to the upper limit frequency fUDL, the lower limit frequency fLDL, the ring signal Rin ', and the FLC signal.

First, as shown in FIG. 3A, when the ring signal Rin 'is between the upper limit frequency fUDL and the lower limit frequency fLDL, when the FLC signal becomes high (that is, when the first Rin ° rises), the composite logic ( Since the prohibition signal INH of 11) becomes high and is input to the noar gate 35, the noar gate 35 outputs a low signal and provides the signal to the D-input of the D-Plip flop 16. Then, after the upper limit frequency signal fUDL goes high, the D-input of the D-flop flop 16 goes high. After the upper limit frequency signal fUDL becomes high, when the ring signal Rin 'rises a second time and the FLC becomes high again, the output of the flip-flop 16 becomes high. This high state signal is applied to one input terminal of the noah gate 3. At this time, the NOA gate 3 outputs a low state signal through the output terminal thereof and applies it to the inverter 4. The inverter 4 inverts the low signal to a high signal to generate a ring enable signal REN.

When the ring signal Rin 'is caught by the lower limit frequency signal fLDL as shown in FIG. 3b, after the upper limit frequency signal fUDL becomes high, the lower limit frequency signal is performed before the ring signal Rin' performs the second rising. When (fLDL) is output from the fLDL terminal of the compound logic 11, the output of the NOA gate 35 goes low, so the D-input of the flip-flop 16 goes low again, so the second ring signal Rin ' Since the low signal is generated at the output terminal of the D-flip-flop 16 when R1 is risen, the ring enable signal REN goes low.

On the other hand, when the ring signal (Rin ') is in the upper limit frequency, as shown in Figure 3c, if the ring signal (Rin') becomes high again before the upper limit frequency (fUDL) becomes high state, the random counter (7) by the FLC signal Since the reset is applied to the upper limit frequency fUDL, the upper limit frequency fUDL does not come out, and the ring enable signal REN is kept low.

,Rin'=high일 경우), 동작개시전압(VEN)이 하이상태가 되고나면 복합로직(11)의 출력(f11)은 하이이므로 ①번 노드에는 로우신호가 출력된다. 이 로우신호는 인버터(21)에 의해 하이상태로 반전되어 ⑥번 노드는 하이상태가 된다. 따라서, 앤드게이트(2)의 3입력단자에는 모두 하이신호가 인가되므로 앤드게이트(2)는 하이신호를 발생시켜 노아게이트(3)에 인가한다. 이때 노아게이트(3)의 출력은 로우상태가 되는바, 이 로우상태의 신호는 인버터(4)에 의해 하이상태로 반전되므로 링인에이블 신호(REN)는 하이가 된다.Then, when disabling the frequency selection circuit (

When RIN '= high), when the operation start voltage VEN becomes high, the output signal f11 of the composite logic 11 is high, so a low signal is output to node ①. This low signal is inverted to a high state by the inverter 21, and node ⑥ is brought to a high state. Therefore, since the high signal is applied to all three input terminals of the AND gate 2, the AND gate 2 generates a high signal and applies it to the NOA gate 3. At this time, the output of the NOA gate 3 is in a low state. Since the low state signal is inverted to a high state by the inverter 4, the ring enable signal REN becomes high.

The ring input circuit shown in FIG. 2 is a circuit for converting an analog Rin 'input into a digital signal. Since the ring input is very large, a Schmitt trigger circuit is used for the MOS circuit and a protection diode is used to withstand the surge voltage. Configured to accept ring input. When the ring input b (Fig. 2a) is applied, the current Irin determines the bias voltage Vb and the sizing of the MOS transistors 107, 108, and 109 so that the current Irin is 20 mu A, and the ring input signal b is increased. Therefore, when the ring potential becomes VDD, it is necessary to adjust the threshold voltage of the inverter 110 so that the level of Rin 'is changed.

For example, when the power supply voltage VDD = 6.8 and Rin'g = 3.4V, the level of Rin 'changes, and the level of the input b at that time is about 17V. In this case, since the transistor 109 is turned off, the level of Rin'g rises to the level of the power supply voltage VDD and the current Irin becomes 0.1 mu A. This waveform is shown in Figures 2a, b, and c.

The present invention operating as described above has a feature that the user can easily generate the enable signal of the system when the input signal is within the selected frequency range to determine the desired frequency range.

Claims (1)

Ring input signal control circuit 1 for converting the analog ring input signal Rin into the digital signal Rin 'by the Schott-triggered operation, and: It operates by the operation start voltage VEN to count the frequency signals A random counter 7 for generating an address signal (Fψ = Fn, Fψ-Fn) of the random signal; and the random counter by a plurality of lower limit frequency and upper limit frequency control signals (FDHψ-FDH3-1, FDLψ-FDLn-1). A complex logic means 11 for calculating the output of (7) and generating the required lower limit frequency signal fLDL, upper limit frequency signals fUDL, f11, and prohibition signal INH; and clocking the random counter 7. A first clock signal generator 100 comprising the noar gates 8 and 9 and the end gate 10 to provide a signal CK, and an upper limit frequency fUDL generated by the combined logic means 11; In order to generate the first data signal by logically combining the lower limit frequency signal fLDL and the prohibition signal INH, the nodal gates 30, 31, 32, 34 and 35 A first data signal generator 101 composed of a rotor 33 and a flip-flop 16, the operation start voltage VEN, a frequency signal f11 of the combined logic means 11, and a lower limit frequency signal fLDL. And a second clock signal generator 102 comprising the noar gates 12 and 13, the oragate 14, the exclusive oragate 15, and the inverters 29 and 36, for the logical combination thereof. And gates 18, 22, 23, noah gates 19 and 20, inverters 21 and exclusive oar gates for inverting the signal output from the input signal processing circuit 1 to generate a second data signal. Inverter 25 for receiving the second data signal generator 103 and the second data signal and the frequency clock signal fs so as to generate a signal FLC in a high state by a half cycle of a clock. ), The half-cycle signal generator 104 comprising the flip-flops 17 and 26, the exclusive oragate 27 and the AND gate 28, and the first data signal and the ring input signal Rin '. ) Is configured by a control means comprising a ring enable signal generator 105 comprising an AND gate 2, a no gate 3, and an inverter 4 to generate a ring enable signal REN by logical combination. And a ring enable signal for system operation when the signal Rin is between an upper limit and a lower limit of the frequency.

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