JPH05291900A - Comparator circuit - Google Patents

Abstract

PURPOSE:To prevent spike noise even when plural input signals are simultaneously changed by providing a control circuit operated to close a gate of a latch circuit when one of the plural input signals is changed to the comparator circuit. CONSTITUTION:An output of a comparator 1 having plural input signals is used for a data input of a latch circuit 2 setting the said output to a through state of a latch state. Furthermore, signals Ao, Bo,...An, Bn, A>B, A<B, A=B being inputs to the comparator 1 are inputted to a gate input terminal of the latch circuit 2 through inverting delay circuits 3-9, EXOR circuits 10-16 and an AND circuit 17. When the signal Bn is changed, an output S4 of the EXOR circuit 13 goes to 0 and an output of the ANd circuit 17 also goes to 0. Then the latch circuit 2 is latched till an output of an inverting delay circuit 6 goes to 0, after the change in the signal An is finished, the output latch state is released and the latch circuit 2 is set in the through-state and a clear value after the change is outputted, then no spike noise is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly to a digital signal comparator circuit.

[0002]

2. Description of the Related Art Generally, a digital signal comparator circuit compares two arbitrary input signals among a plurality of different input signals and outputs them. In this case, when a plurality of different input signals change at the same time, spike noise may occur in the output signal due to a slight shift in the input timing.

For example, in the conventional comparator circuit shown in FIG. 3A, different inputs A _n and B _n are compared with each other, and A _o > B _o , A _o <B _o , A _o = B _o . Correspondingly 0
Alternatively, 1 is output, but when the input signal changes as shown in FIG. 3B, spike noise as shown in the figure is mixed in the output signal.

However, in order for a circuit including such a comparator circuit to operate stably as a whole, a clear signal without spike noise is required as the output of the comparator circuit. Conventionally, in order to prevent this spike noise, the output is used in a disabled state when the input changes.

[0005]

The conventional comparator circuit described above has input signals A _n , B _n , A> B, A <B, as shown in the timing chart of FIG.
When A = B change simultaneously, outputs A _o > B _o , A _o <which originally do not expect change due to the change time difference
Spike noise may occur at B _o , A _o = B _o, and the circuit at the subsequent stage of the comparator circuit may malfunction.

In order to prevent this spike noise, conventionally,
A circuit that uses the output as a disabled state when the input signal changes is used, but in this circuit, a different control signal must be used for control each time the input signal changes, and the circuit configuration is It gets complicated.

An object of the present invention is to provide a comparator circuit capable of preventing spike noise even when a plurality of input signals change simultaneously.

[0008]

SUMMARY OF THE INVENTION A comparator circuit according to the present invention comprises a comparator for comparing two arbitrary signals among a plurality of input signals to be input, and a latch circuit for inputting an output signal of the comparator as a data input. And a control circuit which receives the plurality of input signals and operates to close the gate of the latch circuit when any one of the plurality of input signals changes.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of this embodiment. Referring to FIG. 1, in the present embodiment, the output of the comparator 1 having a plurality of input signals is used as the data input of the latch circuit 2 which is brought into the through state or the holding state. Further, the signals A _o , B _o , ..., _An , B _n , A> B, A <B, which are the input data of the comparator 1,
A = B is an inverting delay circuit 3, 4, 5, 6, 7, 8, 9, E
XOR circuits 10, 11, 12, 13, 14, 15, 1
6, the gate input terminal of the latch circuit 2 is input through the AND circuit 17.

The operation of this embodiment will be described below with reference to the timing chart of FIG. The digital signal comparator circuit compares and outputs arbitrary two inputs of a plurality of different input signals. In this case, if a plurality of different input signals change at the same time, spike noise may occur due to a slight shift in input timing. On the other hand, in this embodiment, in the state before the input change, the EXOR circuits 10, 11, 12, 13, 14,
Outputs 15 and 16 of S1, S2, S3, S4, S5, S
Since 6 and S7 are both 1, the latch 2 circuit is in the through state. However, as shown in FIG. 2, the output S4 of the EXOR circuit 13 becomes 0 when the signal B _n changes, and accordingly As a result, the output of the AND circuit 7 becomes 0. Then, the latch circuit 2 is held until the output of the inverting delay circuit 6 becomes zero. That is, the comparator circuit is in the output holding state for the delay time of the inverting delay circuit. Then, when the output holding state is released after the change of the signal A _n is finished next, the latch circuit 2 becomes the through state and the clear value after the change is output, so that spike noise does not occur. Here, regarding the time of the output holding state, the inverting delay circuit 3,
Since it can be adjusted by 4, 5, 6, 7, 8, and 9, it may be appropriately adjusted according to the magnitude of the deviation of the input timing.

The EXOR circuits 10, 11, 12, 1
Replace 3, 14, 15, 16 with EXNOR circuit and AND
Similar effects can be obtained by replacing the circuit 17 with a NOR circuit.

[0012]

As described above, the comparator circuit of the present invention uses a comparator for comparing any two signals among a plurality of input signals to be input and an output signal of the comparator as a data input. A latch circuit and a control circuit which controls an operation of the latch circuit by receiving an input signal input to the comparator circuit as an input, and when any one of a plurality of input signals to the comparator is changed,
The control circuit is configured to close the latch circuit.

Thus, according to the present invention, spike noise, which is likely to occur in the output signal when a plurality of input data signals input to the comparator circuit simultaneously change, can be easily prevented without using a new control signal. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the embodiment shown in FIG.

FIG. 3A is a block diagram showing a configuration of a conventional comparator circuit. FIG. 5B is a timing chart of each signal for explaining the operation of the comparator circuit shown in FIG.

[Explanation of symbols]

1 Comparator 2 Latch Circuit 3, 4, 5, 6, 7, 8, 9 Inversion Delay Circuit 10, 11, 12, 13, 14, 15, 16 EXO
R circuit 17 AND circuit

Claims (2)

[Claims] 1. A comparator for comparing two arbitrary signals of a plurality of input signals to be input, a latch circuit for receiving an output signal of the comparator as a data input, and a plurality of input signals for inputting the plurality of input signals, A comparator circuit comprising: a control circuit that operates to close the gate of the latch circuit when any one of a plurality of input signals changes. 2. A comparator for comparing two arbitrary signals of a plurality of input signals to be input, and a signal of each of the plurality of input signals and a signal obtained by delaying and inverting the respective signals. And a control circuit comprising an AND circuit having an output signal of the exclusive OR circuit as an input, an output signal of the comparator as a data input, and an output of the AND circuit as a gate A comparator circuit comprising a latch circuit as an input.