JPH0254340A - Preventing circuit for erroneous setting action - Google Patents

Abstract

PURPOSE:To prevent the erroneous logical setting actions when a substrate is loaded and unloaded by deciding the data stored in a shift register and using this deciding output to control the prevention and the transmission of a clock. CONSTITUTION:A logical setting switch 1 is set at L and this setting information is inputted to a shift register SR 3. Then the setting information is sampled by a clock received from a clock generating circuit 2 and stored. The Q outputs of FF1-FFn of the SR 3 are all set at 0 with the output of an EX.NOR circuit 9 set at 1 respectively. Thus a NAND circuit 7 transmits the clock to input it to an FF 8. The FF 8 fetches correctly the final data on the SR 3 and then outputs it after retiming. When the extraction of a substrate 10 out of a connection state between both substrates 10 and 20 is started, the setting contents of the substrate 10 are changed by the chattering. The output of the circuit 9 is set at 0 and the circuit 7 prevents the clock. While the FF 8 holds the data obtained before the chattering is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic setting circuit for a digital circuit, and particularly to a circuit for preventing incorrect setting in logic setting.

[Conventional technology]

Normally, this type of logic setting circuit has a configuration in which a DC signal of logic level "1" or "O" is applied to an operating digital circuit using a switch or the like.

[Problem to be solved by the invention]

Conventional logic setting circuits pose no problem if they are only used for setting digital circuits on the same board. That is, if the connection between the boards is fixed by wiring and cannot be divided, it is sufficient to provide a simple DC level logic setting.

However, if the digital circuit to be set is on another board and the settings are to be made from one place through inter-board wiring,
The following problems arise.

In FIG. 2, a setting board 10 is provided with a switch for logic setting, a board 20 to be set has a digital circuit for which logic is to be set, and the logic setting 10 and the logic setting target 20 are connected by a connector (not shown). This shows a case where the board is connected and the board can be easily inserted and removed.

In such a case, there is a problem that the logic setting becomes unstable due to the chuck ring at the moment when the board is inserted or removed.

An object of the present invention is to provide an erroneous setting prevention circuit for avoiding the above-mentioned problems.

[Means to solve the problem]

The erroneous setting prevention circuit of the present invention includes a shift register that samples logic settings using a clock and stores data, which is composed of multiple stages of flip-flops, and checks whether all data stored in each flip-flop of this shift register matches. a gate circuit that controls blocking or passage of the clock using the output of this determination circuit; and a gate circuit that uses the clock that has passed through this gate circuit to hold the data of the flip-flop in the final stage of the shift register. The device is characterized by comprising a holding circuit that outputs the data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The erroneous setting prevention circuit of this embodiment is provided on a board (substrate to be set) 20 on which a digital circuit whose logic is to be set is provided.

This incorrect setting prevention circuit consists of a shift register 3 that samples logic settings using a clock and stores digital data, and an exclusive NOR circuit that determines whether all outputs of the shift register 3 match.
, hereinafter referred to as EX-NOR circuit)9, and this EX-
A clock control NAND circuit 7 that blocks the clock with the output of the NOR circuit, and an output flip-flop (FF) 8 that retimes the final data of the shift register 3 with a clock controlled by the output of the EX-NOR circuit 9. It is made up of.

The shift register 3 is composed of flip-flops FF, FFZ, .
It is composed of an R circuit 5 and an OR circuit 6.

Each flip-flop FF of shift register 3.

~FF, the Q output of AND circuit 4 and NOR circuit 5
The Q outputs of the final stage flip-flops FF and 1 are further connected to the zero input of the flip-flop 8.

Setting board 10 that can be inserted and removed via a connector (not shown)
A logic setting switch 1 and a sampling clock generation circuit 2 are provided. Logic setting switch 1
is the first stage OF of shift register 3 via the connector.
The clock generation circuit 2 can be connected to the clock input CK of each flip-flop of the shift register 3 and one input of the clock control NAND circuit 7 via a connector.

In the EX-NOR circuit 9, AND circuit 4 and N
The output of the OR circuit 5 is connected to the input of the OR circuit 6, and the output of the OR circuit 5 is connected to the input of the OR circuit 6.
The output of the R circuit 6 is connected to the other input of the NAND circuit 7. The output of the NAND circuit 7 is connected to the clock input CK of the flip-flop 8.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG. Note that FIG. 3 is based on the board 10 with the logic setting switch 1 set to the low level.
The name is a time chart that explains the operation when inserted and removed from the i20.

The sampling clock generation circuit 2 is designed to generate a clock having a cycle shorter than the time required for inserting and removing the board (10 ktlz or less).

First, the operation of the erroneous setting prevention circuit in a state where the setting board 10 is inserted into the setting target board 20 will be explained.

The logic setting switch 1 is set to a low level as shown in FIG. 3(a), and this setting information (logic setting) is input to the shift register 3, and the clock (third The data is sampled and stored according to Figure (b)). The data in the shift register 3 after sampling is shown in FIG. 3(C). In this case, each flip-flop FF, ~FF of the shift register 3
The Q outputs on fi are all 0'', so EX
-The output of the NOR circuit 9 is 1" as shown in FIG. 3(d).
becomes. As a result, the NAND circuit 7 passes the clock from the clock generation circuit 2 and the flip-flop 8
(FIG. 3(e)). With this clock, flip-flop 8 moves shift register 3
The final data (data of clock FFn) is taken in correctly, retimed, and output. The Q output of the flip-flop 8 is shown in FIG. 3(f).

From the state where the boards 10 and 20 are connected, FIG. 3(a)
When the board 10 is started to be pulled out at time t1 as shown in FIG.
The settings made by the setting board 10 change due to chatter. Since the clock is also cut off as shown in FIG. 3(b), the inside of the shift register 3 stops with a mixture of l" and 0" as shown in FIG. 3(c), and the EX-NOR circuit 9 The output of the ? . Therefore, the Q output of the flip-flop 8 is kept low as shown in FIG. 3(f).

Conversely, even when the setting board 10 is started to be inserted at time t2 as shown in FIG. 3(a), the setting contents of the setting board 10 are changed by the chuck ring as shown in FIG. 3(b). do. Therefore, in shift register 3, the third
As shown in FIG. 3(C), "1" and "0" are mixed, and as shown in FIG. 3(d), the output of EX-NOR circuit 9 cannot be set to "1", and NAND circuit 7 is The clock is blocked. In this state, the flip-flop 8 remains at "0" as shown in FIG. 3(f).

When all the data in the shift register 3 becomes the same data "0", the EX/NOR circuit 9 is activated as shown in FIG. 3(d).
The output becomes "1", and a clock (FIG. 3(e)) is input to the output flip-flop 8 via the NAND circuit 7. At this time, the setting content by the logic setting switch 1 is "0", and the output of the flip-flop 8 is as shown in FIG.
f), it is 0''.

As described above, according to this embodiment, the output of the flip-flop 8 remains at a low level regardless of whether the board 10 is inserted or removed, and no error in logic setting occurs when the board 10 is inserted or removed.

In the above embodiment, the board 10 with the logic setting switch 1 set to the low level is inserted or removed.
igh) Even when inserting or removing the board 10 set at the same level, errors in logic setting can be similarly prevented.

〔Effect of the invention〕

As explained above, according to the present invention, the settings set by switches etc. on a separate board do not change even if the board is inserted or removed, that is, it is possible to prevent incorrect logical settings when inserting or removing the board. be.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the erroneous setting prevention circuit of the present invention, Fig. 2 is a diagram showing a conventional logic setting circuit, and Fig. 3 explains the operation when a board set to low level is inserted or removed. This is a time chart. l...Logic setting switch, sampling clock generation circuit, shift register, AND circuit, NOR circuit, OR circuit, NANDAND D circuit flip-flop, EX-NOR circuit, setting board, setting board

Claims (1)

[Claims] (1) A shift register consisting of multiple stages of flip-flops that samples the logic settings using a clock and stores the data, and a judgment circuit that determines whether all the data stored in each flip-flop of this shift register matches. a gate circuit that controls blocking or passing of the clock using the output of this determination circuit; and a holding circuit that holds and outputs the data of the flip-flop in the final stage of the shift register using the clock that has passed through the gate circuit. An erroneous setting prevention circuit characterized by comprising: