KR100438535B1 - Output selection circuit for communication system - Google Patents

Abstract

The present invention relates to a technique for more stably and reliably performing a function of selecting an output terminal of one block that is normally operating among two identical output terminals of one hardware block and matching with an opposite single structure hardware block. The present invention selects one of the output terminals to be selected by receiving information such as PBA demounting / mounting, power fail, function fail, etc. from the PBAs 12A and 12B having the same function. An output stage selector 11 for outputting a signal and feeding the selection signal back to the input stage such that the selection signal is not changed by external factors; A plurality of first function PBAs 12A and 12B which perform the same first function; It is achieved by the second functional PBA 13 which provides the same input signal to the first functional PBA 12A, 12B and is selectively matched with any one of the output terminals thereof to perform the second function. .

Description

OUTPUT SELECTION CIRCUIT FOR COMMUNICATION SYSTEM}

The present invention relates to a technique for matching input / output between different hardware blocks in a communication system. Particularly, an output terminal of one block that is normally operating among two identical output terminals of one hardware block is selected to be matched with an opposite single structure hardware block. An output stage selection circuit of a communication system is adapted.

Signal data is transmitted and received between a plurality of hardware functional blocks in a digital communication system. In such a system, various means may be applied to improve the reliability of the communication system. In particular, if one of the different hardware blocks is composed of PBA (Printed Board Assembly) of multiple configuration, and the other is composed of PBA of single configuration, the other single structure is selected by selecting one PBA output terminal. Must match the PBA.

However, in the output port selection circuit according to the prior art, one of the PBA output terminals of a plurality of configurations is selected according to processor control, PBA removal / mounting, power fail, function fail, and the like so as to match with the PBA of the opposite single structure. However, when the unselected PBA is removed / mounted, the previously selected output stage is released and a malfunction occurs in which the output stage of the newly mounted PBA is selected.

Accordingly, an object of the present invention is to select an appropriate output stage according to a PBA function error, power error, and PBA demounting / mounting condition among two outputs of the same structure installed in one hardware block, and match it with the other single structure hardware block, and select circuit It is to provide an output terminal selection circuit of a communication system for feeding back the output signal of the input signal to the input terminal so that the selection output is not changed by external factors.

1 is a block diagram of an output stage selection circuit of a communication system according to the present invention;

FIG. 2 is a detailed circuit diagram of an output terminal selector in FIG. 1. FIG.

*** Description of the symbols for the main parts of the drawings ***

11: Output stage selector 12A, 12B: PBA for first function

13: PBA for the second function 21: Processor

22: driver

1 is an exemplary block diagram of an output terminal selection circuit of a communication system according to the present invention. As shown therein, the PBA is removed / mounted from a plurality of first-function PBAs 12A and 12B having the same function. And an output stage selector 11 that receives information such as power fail and function fail, and outputs a selection signal to select one output terminal, and feeds the selection signal to the input terminal so that the selection signal is not changed by external factors. )Wow; A plurality of first function PBAs 12A and 12B which perform the same first function; A second function PBA 13 for providing the same input signal to the first function PBA 12A, 12B and selectively matching with one of the output terminals thereof to perform a second function, When described in detail with reference to Figure 2 attached to the operation of the present invention configured as described above are as follows.

In general, in a digital communication system, a hardware function block receives a synchronization clock signal from an external source and uses it as an operation clock. The hardware function block reports a state in each block and receives PBA function control data through an interface with a block control processor.

In addition, it transmits and receives data in correspondence with other hardware function blocks for communication data processing. In this case, when the other function block has a different hardware configuration form, for example, as shown in FIG. If it consists of one function PBA 12A, 12B, and the other consists of one 2nd function PBA 13, the output data of the 2nd function PBA 13 will be used for the 1st function. The input data of the PBA 12A, 12B is provided to each input terminal, and the output data of the first functional PBA 12A, 12B is wired to the input terminal of the second functional PBA 13.

In other words, the first function PBA 12A, 12B having a plurality of configurations accepts and processes input from the second function PBA 13 as it is. However, the output ports include two output ports OUTPUT_A, Since one of the (OUTPUT_B) must be selected and outputted, the output end selector 11 is required.

Therefore, these same constituent blocks, i.e., the first functional PBAs 12A and 12B, respectively output their state information to the output end selector 11 side, and the output end selector 11 has their input states. In response to the determination, the select signals SEL_A and SEL_B are output such that the output port of the PBA in a good state is selected among the first functional PBAs 12A and 12B.

The selection signals SEL_A and SEL_B are changed by the control of the output terminal selector 11, by the removal / mounting of the PBA 12A and 12B, or by the power fail. This is caused by PBA function fail.

2 illustrates an embodiment of the output stage selector 11, which will be described in more detail with reference to the operation of the output stage selector 11.

The processor 21 collects all information related to the states in the first functional PBA 12A and 12B, that is, information such as power fail, whether or not to be mounted or mounted, a function alarm, and the like. Selection signals SEL_A and SEL_B for selecting a good PBA output terminal from among (12B) are output as follows.

When all of the first functional PBAs 12A and 12B are in a normal state, all input signals of the NOA gates NOR1 and NOR2 are input as "low", and "high" is applied to their output terminals. Is output.

However, when a power fail occurs, a detach / mount alarm occurs, or a function alarm occurs among the first functional PBAs 12A and 12B, a corresponding input among the inputs of the noar gates NOR1 and NOR2 is generated. Since the signal is supplied "high" and "low" is output from the corresponding noah gate, the selection signal is output from the positive edge triggered flip-flop FF1 so that the PBA of the normal counterpart is selected.

In addition, in order to enable the output terminal of the first function PBA 12A, 12B to be stably selected, the selection signals SEL_A and SEL_B output from the flip-flop FF1 are converted into a three-state buffer BUF1. Feedback to the input of BUF2. In addition, when the processor 21 arbitrarily adjusts the selection signals SEL_A and SEL_B, the three-state buffer BUF1 enters a high impedance state according to the write enable state of the processor 21. , (BUF2) was used.

When the three-state buffers BUF1 and BUF2 are disabled, high is supplied to one input terminal of the AND gates AD1 and AD2 by the pull-up resistors R1 and R2, respectively. The output value of the flip-flop FF1 only by the alarm signal output from the first function PBA 12A, 12B, i.e., the output signals of the NOA gates NOR1 and NOR2. ), ( ) Is determined and one of the selection signals SEL_A and SEL_B is selected.

For example, an abnormality occurs in the first functional PBA 12A so that "low" is output from the noar gate NOR1, while the first functional PBA 12B operates normally and the noar gate NOR2. Outputs the output terminal of the flip-flop FF1 when " high " High) is output from the processor 21 so that the output port OUTPUT_B of the first function PBA 12B is selected irrespective of the value input to the input terminal D of the flip-flop FF1. .

Of course, in the opposite case to the above, the output terminal of the flip-flop FF1 ( In this case, since "low" is outputted, the output port OUTPUT_A of the first function PBA 12A is selected.

If both of the first functional PBAs 12A and 12B operate normally, " high " is output from the output force terminals of the NORG gates NOR1 and NOR2, thereby providing the flip-flop FF1. "High" is supplied to the set terminal SET and the clear terminal CLR. Accordingly, when the flip-flop FF1 is in an initial state and "high" is output to its output terminal Q, or the input data D value and the output Q value are different from each other, the exclusive oar gate At EX-OR, an interrupt signal IRQ is generated, at which time the processor 21 changes its input data D value to bring the interrupt signal IRQ to normal.

However, when both of the first functional PBAs 12A and 12B operate abnormally, " low " is output from the output force terminals of the NOA gates NOR1 and NOR2, respectively, so that the flip-flop FF1 Are supplied to the set terminal (SET) and the clear terminal (CLR). As a result, the output terminal ( ), ( ) Is outputted to both the " low " and the selection signals SEL_A and SEL_B of the first function PBAs 12A and 12B are also supplied as " low ". As a result, the output ports OUTPUT_A and OUTPUT_B of the first functional PBAs 12A and 12B are all disabled to enter a high impedance state.

Thus, the output terminal of the flip-flop (FF1) ( ), ( In the case of outputting "low" at all outputs, " low " is output at the output terminal Q of the flip-flop FF2. At this time, the buffers BUF1 and BUF2 are output by the output signal of the AND gate AD3. Transitions to the disabled state and becomes a high impedance state, so that the state change of the first functional PBAs 12A and 12B can be accepted.

Thereafter, when any one of the first functional PBAs 12A and 12B is converted to the normal state, the output port returned to the normal state is enabled by the above process.

Meanwhile, a process of selecting the output ports OUTPUT_A and OUTPUT_B under the control of the processor 21 will be described below.

When all of the first functional PBAs 12A and 12B operate normally to output “high” at both the AND gates AD1 and AD2, the output terminal of the flip-flop FF1 ( ), ( ) Outputs different values, and the values of the set terminal SET and the clear terminal CLR of the flip-flop FF1 are different from each other based on the output value, and thus have an output port that is not selected. Regardless of the state change of the PBA 12A, 12B, a constant output is always maintained.

In this state, when the processor 21 transitions the write enable value from "high" to "low" to select the output port of the first functional PBA 12A, 12B, thereby the buffer (BUF1) and (BUF2) become a high impedance state. Accordingly, the output of the flip-flop FF1 ( ), ( Value is set according to the states of the first functional PBA 12A, 12B, and when they are all normal, the first functional PBA 12A, 12B is selected by the selection data of the processor 21 and the shift clock signal. Output ports (OUTPUT_A) and (OUTPUT_B) can be changed in synchronization with the internal clock.

When the write operation of the processor 21 is completed, the write enable value is kept high again and the shift clock is also blocked to output the output ports OUTPUT_A and OUTPUT_B of the PBAs 12A and 12B for the first function. ) Can be selected according to their condition.

Meanwhile, the process of selecting the output ports OUTPUT_A and OUTPUT_B when the first functional PBAs 12A and 12B operate normally will be described below.

When none of the first functional PBAs 12A and 12B is present, an output terminal thereof is selected when the state of the mounted PBA is normally operated. However, when both of the first functional PBAs 12A and 12B are mounted and normally supplied with power, the flip-flop FF1 outputs two outputs in an initial unstable state. ), ( ) Becomes both "high", the output ports OUTPUT_A and OUTPUT_B of the first function PBA 12A and 12B are disabled, but the selected values are buffers BUF1 and BUF2. The set terminal SET and the clear terminal CLR of the flip-flop FF1 are fed back to the input terminal of N, and the values of the set terminal SET and the clear terminal CLR become "high". ), ( ) Is selected differently and only one of the two output ports (OUTPUT_A) and (OUTPUT_B) is enabled.

Meanwhile, the operation of selecting the output ports OUTPUT_A and OUTPUT_B according to the removal / mounting of the first functional PBAs 12A and 12B, the power fail, and the function fail will be described below.

When the PBA with the output port selected is disconnected, the input is "high" by the pull-up resistor (R1) or the pull-up resistor (R2), a power failure signal is input "high" from the selected PBA, or a malfunction is performed on the selected PBA. When the alarm signal is output as "high", a "low" is output from the corresponding noa gate among the noah gates NOR1 and NOR2, whereby the set terminal SET or the clear terminal (F1) of the flip-flop FF1 is output. The "low" signal is supplied to the CLR to select the output port of the PBA that does not generate an alarm.

Thereafter, as in the above description, even if the state of the non-selected PBA is changed, the selected state of the output port is maintained. However, when an alarm occurs in the PBA in which the output port is selected, "low" is output from any one of the NOR gates NOR1 and NOR2, whereby the set terminal SET or the clear terminal of the flip-flop FF1 is output. To " low " ), ( If "high" is outputted in any one of the Ns), it is fed back to the input of the buffer BUF1 or BUF2 so that a normal PBA is selected.

When the selection of the output ports OUTPUT_A and OUTPUT_B is changed as described above, the state recorded by the processor 21 is compared with the output value of the flip-flop FF1 as described above, and the values thereof are opposite to each other. The interrupt signal IRQ is generated from the exclusive oragate EX-OR and transmitted to the microprocessor 21 so that the microprocessor 21 can recognize the fact.

As described in detail above, the present invention provides an output port selection circuit having a simple configuration according to a PBA function error, a power error, and a PBA demounting / mounting state among two PBA output ports having the same structure installed in one hardware block. By selecting the output port to be matched with the opposing unitary hardware block, there is an effect to improve the stabilization and reliability of the communication system.

Claims (3)

PBAs 12A and 12B having the same function are inputted with information such as PBA demounting / mounting, power fail, function fail, and the like, and a selection signal is output so that either output terminal is selected and the selection signal is selected. An output stage selector 11 for feeding back to the input stage such that the selection signal is not changed by external factors; A plurality of first function PBAs 12A and 12B which perform the same first function; A second function PBA 13 for providing the same input signal to the first function PBA 12A, 12B and selectively matching with any one of the output terminals thereof to perform a second function. Output stage selection circuit of the communication system. 2. The output terminal selector 11 according to claim 1, wherein the output terminal selector 11 outputs a signal of a predetermined logic when the functional state, power state, and mounting state of the first functional PBAs 12A and 12B are all normal. Gates NOR1 and NOR2; The input data D is input from the processor 21, the output signals of the NOA gates NOR1 and NOR2 are input to the set terminal SET and the clear terminal CLR, and accordingly, the first function PBA ( And a flip-flop (FF1) for outputting the selection signals (SEL_A) and (SEL_B) of 12A) and (12B). 3. The apparatus of claim 2, further comprising: three-state buffers BUF1 and BUF2 that are in a high impedance state according to the write enable state of the processor 21 and have a pull-up resistor at the output terminal; A feedback loop for feeding back the selection signals SEL_A and SEL_B to input terminals of the three-state buffers BUF1 and BUF2; An AND gate AD1 for combining the output signal of the tri-state buffer BUF1 and the output signal of the NOR gate NOR1 to the set terminal SET of the flip-flop FF1; And an AND gate AD2 for outputting the output signal of the tri-state buffer BUF2 and the output signal of the NOR gate NOR2 to the clear terminal CLR of the flip-flop FF1. An output stage selection circuit of a communication system.