JPH05207532A - Line setting control circuit - Google Patents
Line setting control circuitInfo
- Publication number
- JPH05207532A JPH05207532A JP30865791A JP30865791A JPH05207532A JP H05207532 A JPH05207532 A JP H05207532A JP 30865791 A JP30865791 A JP 30865791A JP 30865791 A JP30865791 A JP 30865791A JP H05207532 A JPH05207532 A JP H05207532A
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- setting
- register
- line setting
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Exchange Systems With Centralized Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は回線設定制御回路に関
し、特に通信機などに用いる回線設定制御回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line setting control circuit, and more particularly to a line setting control circuit used in a communication device or the like.
【0002】[0002]
【従来の技術】従来、この種の回線設定制御回路は図2
に示す構成である。図2は従来例における構成を示すブ
ロック図である。複数の入力信号と複数の出力信号との
間をレジスタ22からの設定データ信号により接続を行
なう回線設定部21と、設定データ信号を生成し出力す
る制御部24と、制御回路24からの設定データ信号を
保持する編集用のレジスタ23とから構成されている。2. Description of the Related Art Conventionally, this kind of line setting control circuit is shown in FIG.
The configuration is shown in. FIG. 2 is a block diagram showing the configuration of a conventional example. A line setting unit 21 for connecting a plurality of input signals and a plurality of output signals with a setting data signal from a register 22, a control unit 24 for generating and outputting a setting data signal, and setting data from the control circuit 24. It is composed of an editing register 23 for holding a signal.
【0003】制御回路24で生成された設定データ信号
は、レジスタ23で一旦保持され、制御回路24からの
制御により編集され、最後に読出されて確認されてか
ら、制御回路24からのデータシフト信号201により
レジスタ22へ移される。回線設定部21の回線設定
は、このレジスタ22の動作用の設定データ信号により
行なわれ、この設定データ信号はデータシフト信号20
1により、次々にレジスタ23の設定データ信号に設定
内容が更新される。The setting data signal generated by the control circuit 24 is temporarily held in the register 23, edited by the control of the control circuit 24, and finally read and confirmed, and then the data shift signal from the control circuit 24. It is moved to the register 22 by 201. The line setting of the line setting unit 21 is performed by the setting data signal for the operation of the register 22, and the setting data signal is the data shift signal 20.
By 1, the set contents are updated to the set data signal of the register 23 one after another.
【0004】[0004]
【発明が解決しようとする課題】このように従来例にお
いては、編集用のレジスタのデータを動作制御用のレジ
スタにシフトしているために、制御部からは動作制御用
のレジスタの状況、即ち現在設定されている回線接続の
状況がわからず、このために、例えばデータシフト時の
転送誤り、あるいは動作制御用のレジスタの障害によ
り、制御部の認識と異なる回線設定がなされていてもそ
れを検出できないという問題がある。As described above, in the conventional example, since the data of the register for editing is shifted to the register for operation control, the status of the register for operation control, I do not know the status of the line connection that is currently set.For this reason, even if a line setting different from that recognized by the control unit is set due to a transfer error at the time of data shift or a failure in the register for operation control, There is a problem that it cannot be detected.
【0005】[0005]
【課題を解決するための手段】本発明の回線設定制御回
路は、複数の入力信号と複数の出力信号との間を設定デ
ータ信号により接続を行なう回線設定部と、それぞれ内
容の異なる2つの前記設定データ信号を入力し選択信号
により一方を選択し前記回線設定部へ出力する選択回路
と、2つの前記設定信号をそれぞれ一時保持し前記選択
回路へ出力する2つのレジスタと、前記設定データ信号
を生成し前記2つのレジスタの一方を交互に選択し入力
すると共に前記選択信号を出力する制御回路とを備えて
いる。A line setting control circuit according to the present invention comprises a line setting section for connecting a plurality of input signals and a plurality of output signals by setting data signals, and two line setting units each having different contents. A selection circuit that inputs a setting data signal, selects one of them according to a selection signal, and outputs the selected setting signal to the line setting unit; two registers that temporarily hold the two setting signals and output them to the selecting circuit; A control circuit for generating and alternately selecting and inputting one of the two registers and outputting the selection signal.
【0006】[0006]
【実施例】次に本発明の一実施例について図を参照して
説明する。図1は本実施例の構成を示すブロック図であ
る。制御回路5により生成された設定データ信号は、レ
ジスタ選択信号102,103により選択されたレジス
タ3,4の一方のレジスタへ入力される。レジスタ3,
4に保持された設定データ信号は、選択回路2により一
方が選択され、回線設定部1へ入力されて回線接続指定
を行なう。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. The setting data signal generated by the control circuit 5 is input to one of the registers 3 and 4 selected by the register selection signals 102 and 103. Register 3,
One of the setting data signals held in 4 is selected by the selection circuit 2 and input to the line setting unit 1 to specify the line connection.
【0007】制御回路5は、例えばレジスタ選択信号1
02によりレジスタ3を選択し、生成した設定データ信
号を入力し、これを編集している時は、選択信号101
は通常レジスタ4を選択し、レジスタ4の保持する回線
データ信号を動作用として回線設定部1へ出力する。そ
して次にレジスタ3の設定データ信号が動作用として選
択された時は、セレクタ4に新しい設定データ信号が入
力される。又制御回路5はレジスタ3,4が保持してい
る各設定デタ信号を随時読出して設定内容を確認するこ
とができる。The control circuit 5 is, for example, a register selection signal 1
The register 3 is selected by 02, the generated setting data signal is input, and when this is being edited, the selection signal 101
Normally selects the register 4 and outputs the line data signal held in the register 4 to the line setting unit 1 for operation. Then, when the setting data signal of the register 3 is selected next for operation, a new setting data signal is input to the selector 4. Further, the control circuit 5 can read each setting data signal held in the registers 3 and 4 as needed to confirm the setting contents.
【0008】[0008]
【発明の効果】以上説明したように本発明は、回線設定
の設定データ内容を随時読出して確認することができる
ので、回線設定の指定誤りを防止、あるいは指定誤りを
早期に発見修正することがでる。このために回線設定の
信頼性を向上させる効果がある。As described above, according to the present invention, since the setting data contents of the line setting can be read out and confirmed at any time, the designation error of the line setting can be prevented or the designation error can be detected and corrected early. Out. Therefore, there is an effect of improving the reliability of the line setting.
【図1】本発明の一実施例の構成を示すブロック図であ
る。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
【図2】従来例の構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of a conventional example.
1 回線設定部 2 選択回路 3,4 レジスタ 5 制御回路 1 line setting unit 2 selection circuit 3 and 4 register 5 control circuit
Claims (1)
を設定データ信号により接続を行なう回線設定部と、そ
れぞれ内容の異なる2つの前記設定データ信号を入力し
選択信号により一方を選択し前記回線設定部へ出力する
選択回路と、2つの前記設定信号をそれぞれ一時保持し
前記選択回路へ出力する2つのレジスタと、前記設定デ
ータ信号を生成し前記2つのレジスタの一方を交互に選
択し入力すると共に前記選択信号を出力する制御回路と
を備えることを特徴とする回線設定制御回路。1. A line setting section for connecting a plurality of input signals and a plurality of output signals by setting data signals, and two setting data signals having different contents respectively, and one of them is selected by a selecting signal. A selection circuit for outputting to the line setting unit, two registers for temporarily holding the two setting signals and outputting to the selection circuit, and a circuit for generating the setting data signal to select one of the two registers alternately. A line setting control circuit, comprising: a control circuit that inputs and outputs the selection signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30865791A JPH05207532A (en) | 1991-11-25 | 1991-11-25 | Line setting control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30865791A JPH05207532A (en) | 1991-11-25 | 1991-11-25 | Line setting control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05207532A true JPH05207532A (en) | 1993-08-13 |
Family
ID=17983720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30865791A Withdrawn JPH05207532A (en) | 1991-11-25 | 1991-11-25 | Line setting control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05207532A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0918497A (en) * | 1995-07-04 | 1997-01-17 | Nec Corp | Data setting system |
-
1991
- 1991-11-25 JP JP30865791A patent/JPH05207532A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0918497A (en) * | 1995-07-04 | 1997-01-17 | Nec Corp | Data setting system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH05207532A (en) | Line setting control circuit | |
US5157696A (en) | Digital signal time difference correcting circuit | |
US5426766A (en) | Microprocessor which holds selected data for continuous operation | |
JPS6214860B2 (en) | ||
JPH0315982A (en) | Logical simulation system | |
JP2000259559A (en) | Serial interface circuit | |
JPH06324113A (en) | Semiconductor integrated circuit | |
JP2552027B2 (en) | I / O controller number setting method | |
JPS5851353A (en) | Program control circuit | |
JPH0383296A (en) | Shift circuit | |
JPH0572615B2 (en) | ||
JP2897774B2 (en) | Output select circuit | |
JP2785287B2 (en) | Test access circuit | |
JPH02249332A (en) | Redundancy system selection circuit | |
JP2644572B2 (en) | Frame overhead processing circuit | |
JP3157662B2 (en) | LSI diagnostic control circuit | |
JPH04310124A (en) | Register file | |
JPH0668055A (en) | Digital signal processor | |
JP2749417B2 (en) | Priority control circuit | |
JPH04264918A (en) | Shift calculation circuit | |
JPS59108128A (en) | Adjusting circuit of timing | |
JPH0424741B2 (en) | ||
JPS59148949A (en) | Branch discriminating circuit of electronic computer | |
JPS6223248A (en) | Data transmission equipment | |
JPS6243222B2 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |