JPH0424741B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field This invention relates to a data transmission device, and particularly to a data transmission device that selectively transmits data transmitted at arbitrary time intervals to one of a plurality of parallel transmission paths. The present invention relates to a data transmission device.

2. Description of the Related Art A processing device such as an electronic computer connects a plurality of processing units through communication using digital signals to perform data processing. In this way, when processing is distributed and processed by a plurality of processing units, the contents of data processing in each processing unit are generally different, and the data required for each processing and the results obtained are also different.

Problems to be Solved by the Invention When combining the above-mentioned plurality of processing unit groups,
If the processing units that require data exchange are wired for each data process and an input/output port is provided, the hardware becomes extremely complex, resulting in larger equipment and higher costs. It was hot.

Therefore, the main object of the present invention is to be able to transmit different types of data groups using the same data transmission path, and to identify the destination of the data by a part of the data or an identifier attached to the data. It is an object of the present invention to provide a data transmission device that can reduce the amount of hardware wiring and selectively transmit data to a desired transmission path.

Means for Solving the Problems The present invention is a data transmission device in which each device is provided in parallel, holds data from the subsequent stage in response to outputting a transmission permission signal to the subsequent stage, and receives transmission permission from the previous stage. Depending on the signal given,
a plurality of output side data transmission lines that output data;
In response to outputting a transmission permission signal to the subsequent stage, a transmission permission signal is given from the previous stage after receiving data from the latter stage and a part of the data or an identifier for specifying a transmission path associated with the data. an input-side data transmission line that outputs data and an identifier to the previous stage according to the input data transmission line; a determination means that determines whether a transmission permission signal is output from each of the plurality of output-side data transmission lines; and at least one corresponding to the identifier. The data output from the input data transmission path is output to the corresponding output data transmission path in response to the determination means determining that the transmission permission signal is output from the output data transmission path. and a control means for controlling.

Effect: The data transmission device according to the present invention outputs a transmission permission signal to a subsequent stage to hold data and a part of the data or an identifier attached to the data, and a plurality of output side data provided in parallel. In response to determining that a transmission permission signal is being output from at least the output side data transmission path corresponding to the identifier among the transmission paths, data from the input side data transmission path is transmitted to the corresponding output side data transmission path. can be output to. Therefore, even if different types of data are transmitted to the input data transmission path, the output data transmission path can be selected according to the identifier and the data can be transmitted. There is no need to provide ports or special wiring.

Embodiment FIG. 1 is a schematic block diagram of an apparatus for branching data into two and transmitting the data according to an embodiment of the present invention.

First, with reference to FIG. 1, an example in which data is transmitted by branching to two transmission paths will be briefly described. The data transmission lines 1, 100, and 200 used in the embodiment shown in FIG. 1 each have a line signal for transmitting data and a UK signal that indicates whether the preceding data transmission line is empty or not. ing.
Further, in this embodiment, an identifier transmission line 2 is provided in parallel with the data transmission line 1. Identifier transmission path 2
is for transmitting an identifier called a tag.
This identifier indicates which of the two data transmission paths 100 and 200 the data transmitted to the data transmission path 1 should be transmitted to.

Now, when data transmission paths 100 and 200 are both empty and data transmission is possible, UK signals 10a and 20a are applied to control units 10 and 20, respectively. When the UK signals 10a and 20a are input, the control units 10 and 20 determine that the data transmission paths 100 and 200 are empty, respectively, and provide determination signals 10b and 20b to the AND gate 4, respectively. The AND gate 4 has a control unit 10,
When the discrimination signals 10b and 20b indicating that the data transmission lines 100 and 200 are empty are inputted from the data transmission line 20, the AK signal is applied to the data transmission line 1 and the identifier transmission line 2.

The identifier transmission path 2 provides the identifier decoder 3 with an identifier indicating that the data transmitted to the data transmission path 1 should be transmitted to the data transmission path 100, for example. The identifier decoding section 3 decodes the identifier transmitted from the identifier transmission path 2, and supplies a control signal 10c to the control section 10 to activate it. Thereby, data transmitted from the data transmission path 1 is transmitted to the data transmission path 100 via the control section 10. Conversely, from identifier transmission path 2 to data transmission path 2
When the identifier decoding unit 3 is given an identifier indicating that data should be transmitted to 00, the identifier decoding unit 3 supplies a control signal 20c to the control unit 20 to activate it, and the data is transmitted to the data transmission path 1. Data is transmitted to the data transmission path 200 via the control unit 20.

If one of the data transmission paths 100 and 200, for example, the data transmission path 100, is transmitting data, the UK signal 10a is not given to the control unit 10. For this reason, the control unit 10
determines that the data transmission line 100 is transmitting, and applies a low level signal to one input terminal of the AND gate 4. Therefore, the AND gate 4 is closed and the Ak signal is no longer applied to the data transmission path 1 and the identifier transmission path 2. That is, if data is being transmitted on either data transmission path 100 or 200, the data transmitted to data transmission path 1 will not be transmitted.

FIG. 2 is a specific circuit diagram of an embodiment in which data is divided into two branches. First, the configuration will be explained with reference to FIG. Data from the data transmission line 1 shown in FIG. 1 mentioned above is given to the register 4.
This register 4 constitutes a first storage means for temporarily storing n-bit data. Further, the identifier transmitted from the identifier transmission path 2 shown in FIG. C elements (Coincidence Elements) 6 and 7 are pulse signals C ₀
The writing of data to the register 4 is controlled based on this.

One control section 10 includes a register 11 and a C element 12.
and 13, an OR gate 14, and a D-type flip-flop 15. Further, the other control section 20 includes a register 21 and C elements 22 and 23.
and OR gate 24 and D type flip-flop 2
It consists of 5. Registers 11 and 21 constitute a second storage means for temporarily storing the n-bit data stored in register 4 described above. C element 1
C elements 2 and 13 control the writing of data to the register 11, and C elements 22 and 23 control the writing of data to the register 21. D type flip-flop 15 and 2
5 transfers the data stored in the register 4 to the register 11 on the control unit 10 side based on the identifier decoded by the above-mentioned D type flip-flop 5.
This selects whether to write to the register 21 of the control section 20 or to write to the register 21 of the control section 20.

Next, the operation of the data transmission device shown in FIG. 2 will be explained. In the initial state, the reset signal is applied to C elements 6, 7, 12, 13, 22 and 2.
3 and initial resets them, and also initial resets the D type flip-flops 15 and 25 via OR gates 14 and 24, respectively. D type flip-flop 15 and 25
As a result of the initial reset,
Both Q ₁ and Q ₂ outputs are “L”. Also,
Since C elements 12, 13, 22 and 23 have also been reset, their respective _Q1 outputs are at "L".

The Q ₁ output of C element 12 and the Q ₁ output of C element 22 are each given to AND gate 8 . AND
Since the two inputs of gate 8 are at "L", it outputs an AK signal at H level. When this AK signal is "H", no data is stored in the registers 11 and 21, indicating that data transmission is possible. That is, if the _Q1 output of each C element 12, 22 is "L", it indicates that no data is stored in the corresponding register 11, 21, respectively.

In this state, data is input to register 4,
An identifier is applied to a D type flip-flop 5 and a pulse signal C ₀ is applied to a C element 6. At this time, the _Q2 output of the C element 7 is at "H" due to the initial reset. Pulse signal C ₀ is “H”
When this happens, the _Q1 output of the C element 6 becomes "H".
Since the AK signal of the C element 7 is "H", the pulse signal C ₀ is transmitted to the Q ₁ output of the C element 7 . Then, the register 4 stores the data at the timing when the _Q1 output of the C element 7 rises to "H". The _Q1 output of C element 7 is about to be transmitted to C elements 12 and 22, but the output of D type flip-flop 15 is
_Q1 output and D type flip-flop 25
Since the Q ₂ output is “L” due to the initial reset, the Q ₁ output of C element 7 is output from C elements 12 and 22.
input is not allowed.

On the other hand, it is assumed that the identifier given along with the data indicates, for example, "1" in order to transmit the data to the data transmission path 100. The D type flip-flop 5 has an identifier set to "1", and at the timing when the Q1 output of the C element ₇ rises to "H", the Q output is set to "H" and the output is set to "L". When the Q output of the D-type flip-flop 5 becomes "H", the D-type flip-flop 15 is set at the rising edge, its _Q1 output becomes "H", and the output of the D-type flip-flop 25 becomes "H".
_Q2 output still holds "L".

_Q1 of D type flip-flop 15 is “H”
As a result, the _Q1 output of C element 7 becomes
Q ₁ of the C element 12 that receives the AK signal that has become “H”
transmitted to the output. Then, the data transmission line 100
When the transmission permission signal UK12 from the
The _Q1 output of the C element 13 becomes "H". and,
At the rising timing, the data stored in the register 4 is stored in the register 11 and transmitted to the data transmission line 100.

On the other hand, since the _Q2 output of the D type flip-flop 25 is "L", the C element 22
The “H” _Q1 output from C element 2 is not permitted and is not transmitted to C element 23. Therefore, since no pulse signal is given to the register 21, the data stored in the register 4 is not stored in the register 21. In this way, when the identifier becomes "1", the data stored in the register 4 is transmitted to the data transmission path 100 via the register 11, but not to the data transmission path 200.

As described above, when the Q ₁ output of the C element 13 becomes "H", the Q ₂ output becomes "L". Then, the OR gate 14 resets the D type flip-flop 15 by the "L" level of the _Q2 output of the C element 13. When the D type flip-flop 15 is reset, its _Q1 output becomes "L", so the _Q1 output of the C element 12 becomes "L". At this time, since the _Q1 output of the C element 22 is also "L",
AND gate 8 outputs an "H" AK signal.
This allows the transmission of the following data.

Next, in order to transmit the input data to the data transmission path 200, when the identifier becomes "0", the D type flip-flop 25 is set,
The Q ₁ output of C element 7 is transmitted to C elements 22 and 23, a pulse signal is given to register 21, and the data stored in register 4 is stored in register 21 and transmitted to data transmission line 200.

Note that in the above explanation, data from data transmission path 1 is transmitted only to either data transmission path 100 or 200, but data may be transmitted to both data transmission paths 100 and 200 at the same time. It is possible. In that case, the output of either Q or Q of the D-type flip-flop 5 may be commonly provided as the clock pulse for the D-type flip-flops 15 and 25.

FIG. 3 is a schematic block diagram of an embodiment in which data is divided into four branches and transmitted. The example shown in Figure 3 is
The example shown in FIG. 1 above has two data transmission paths 1.
00, 200, but four data transmission lines 100, 200, 200,
When both 300 and 400 are in an idle state, it is possible to branch to one to four transmission paths for transmission. For this purpose, the control units 10, 20, 30 and 40 correspond to the data transmission paths 100, 200, 300 and 400, respectively.
is provided. Further, the identifier decoding unit 3 has four data transmission paths 100, 200, 300 and 400.
In order to branch and transmit the data, identification signals specifying each are given to the control units 10, 20, 30 and 40. In addition, all data transmission paths 1
An AND gate 80 is provided to determine whether each of 00, 200, 300, and 400 is vacant.

In the embodiment shown in FIG. 3, when the AND gate 80 determines that each of the data transmission lines 100, 200, 300, and 400 is in an empty state, a signal indicating this is transmitted to the data transmission line 1 and the identifier transmission line. Path 2 is given. Then, from the identifier transmission path 2 to the identifier decoding section 3, an identification signal indicating to which data transmission path the data should be transmitted is given to one of the control sections 10, 20, 30, and 40. For example, when an identification signal is given to the control section 30, the control section 30 transmits data from the data transmission path 1 to the data transmission path 300. Further, for example, when an identification signal is given to the control sections 20 and 40, the control section 20 transmits the data from the data transmission path 1 to the data transmission path 200, and the control section 40 transmits the data to the data transmission path 400. Transmit.

FIG. 4 is a specific circuit diagram of an embodiment in which data is divided into four branches and transmitted. In this embodiment, the identifier is included as part of the data and consists of 2 bits in order to identify the four data transmission paths.
This 2-bit identifier is given to the identifier decoding section 50. The identifier decoding unit 50 generates four identification signals DC1, DC2,
Outputs DC3 and DC4. These identification signals DC1 to DC4 are respectively sent to the control unit 1.
0, 20, 30 and 40.

The control units 10 and 20 are constructed in the same manner as the embodiment shown in FIG. 2 described above. Similarly, the control section 30 is composed of a register 31, C elements 32 and 33, an OR gate 34, and a D type flip-flop 35. Similarly, the control section 40 also includes a register 41, C elements 42 and 43, an OR gate 44, and a D type flip-flop 45. Additionally, a four-input AND gate 80 is provided to enable data transmission when any of the four transmission paths are idle. The 4-input AND gate 80 is given the Q ₁ output of the C element 12, the Q ₁ output of the C element 22, the Q ₁ output of the C element 32, and the Q ₁ output of the C element 42, and their outputs are When both are "L", an "H" AK signal is given to the C element 7.

In the four-branch data transmission device configured as described above, when the pulse signal C ₀ is applied to the C element 6,
The pulse signal is transmitted to the C element 7, and the pulse signal is given to the register 4. The register 4 stores data at the timing of the rise of the pulse signal. Of the data stored in register 4,
The 2-bit identifier is given to the identifier decoding section 50 and is identified. Then, when the identification signal DC4 is output from the identifier decoding section 50 and applied to the D type flip-flop 45, this D type flip-flop 45 is set and the C element 7 is set.
The pulse signal outputted from the C elements 42 and 43 is transmitted to the C elements 42 and 43, and the pulse signal is given to the register 41. As a result, the data stored in register 4 is stored in register 41 and transmitted to data transmission path 400.

Further, when an identifier for selecting the data transmission path 300 is given, the identifier decoding section 50 outputs an identification signal DC3, and the data stored in the register 4 by the control section 30 is transmitted to the data transmission path 300. Ru. Thereafter, in the same manner, the data transmission path 20
When an identifier for transmitting data to 0 is given to the identifier decoding section 50, an identification signal DC2 is outputted, and the data stored in the register 4 is transmitted to the data transmission path 200 by the control circuit 20. When an identification signal for transmitting data to the data transmission path 100 is given to the identifier decoding section 50, an identification signal DC1 is output, and the data stored in the register 4 by the control circuit 10 is transferred to the data transmission path 100.
transmitted to.

Note that in the above description, four transmission lines 100,
Although data can be transmitted to any one of 200, 300, and 400, the present invention is not limited to this, and it is also possible to transmit data to two or more transmission paths in parallel. In that case, the identifier decoder 50 may be configured so that the identifier decoder 50 can simultaneously output identification signals for identifying a plurality of transmission paths to which transmission is desired.

FIG. 5 is a specific circuit diagram of another embodiment in which data is divided into four branches and transmitted. In the embodiment shown in FIG.
AND gates 16, 26, 36 and 46 are provided, respectively, and the identification outputs DC1 to DC4 of the identifier decoding section 50 are applied to the AND gates 16, 26, 3, respectively.
6 and 46, and the _Q1 output of C element 7 is applied to the other input terminal.

The AND gates 16, 26, 36, and 46 are provided in this way, for example, in the data transmission line 10.
This is to enable data to be transmitted continuously from 0 to 0. That is, in the embodiment shown in FIG. 4, when data is transmitted sequentially from transmission path 100 to 400, the identifier decoding unit 50 outputs identification outputs DC1 to DC based on the identifier included in the data.
D type flip-flops 15, 25, 35 and 45 can be set sequentially to output 4 sequentially.

However, the D type flip-flop 15,2
5, 35, and 45 are reset after transmitting data to their respective transmission lines. However, when data is continuously transmitted to the data transmission path 100, for example, the identification output DC1 continues to be at the "H" level. For this reason, D
The type flip-flop 15 is reset after transmitting the first data, and at this time the identification output
Since DC1 maintains "H", even if the next data is to be transmitted to the data transmission line 100, the D type flip-flop 15 cannot be set.

Therefore, in the embodiment shown in FIG. 5, the clock input side of the D-type flip-flop 15 is
An AND gate 16 is provided, and the identification output DC1 is applied to one input terminal of the AND gate 16, and the pulse signal from the C element 7 is applied to the other input terminal, so that the identification output DC1 remains "H". However, the AND gate 16 is opened by the pulse signal from the C element 7, and the D type flip-flop 1 is opened.
5 can be set. Therefore, even when data is continuously transmitted to the data transmission line 100, the D-type flip-flop 15 is reset every time one piece of data is transmitted.
When a pulse signal is input to the C element 6 to transmit the next data, the pulse signal is applied to the AND gate 16 via the C element 7, so the D type flip-flop 15 is set and the continuous Then, data can be transmitted to the data transmission path 100.

FIG. 6 is a detailed circuit diagram of another embodiment in which data is divided into four branches and transmitted. The embodiments shown in FIGS. 4 and 5 described above can transmit input data not only to one data transmission path but also to multiple data transmission paths, such as data transmission paths 100 and 200, simultaneously. However, in the embodiment shown in FIG. 6, data can be transmitted only through one data transmission path that is in an empty state. The data transmission device shown in this embodiment includes a register 4 for storing data and a C element 60 for controlling writing of data to this register 4 in the same manner as in FIGS. 4 and 5 described above.
and an identifier decoding section 50 for identifying the identifier, and control circuits 10 to 40.

The control circuit 10 includes a register 11 and a C element 18.
Consists of AND gate 16 and buffer 17,
The control circuit 20 includes a register 21 and a C element 28.
Consists of an AND gate 26 and a buffer 27,
The control circuit 30 includes a register 31 and a C element 38.
Consists of an AND gate 36 and a buffer 37,
The control circuit 40 includes a register 41 and a C element 48.
It is composed of an AND gate 46 and a buffer 47. The outputs of buffers 17, 27, 37 and 47 are wired OR connected and applied to C element 60. Note that C elements 18, 28, 3
8, 48 and 60 are the two-stage connected C elements 12, 13, 22, 23, 3 shown in FIG. 5, respectively.
2, 33, 42, 43 and 6, 7 are shown in a simplified manner.

Next, the operation will be explained. Data is input to register 4 and pulse signal C ₀ is input to C element 60.
, the register 4 stores data based on the pulse signal transmitted to the C element 60.
The identifier included in the data stored in the register 4 is given to an identifier decoding unit 50, and is output as an identification output in order to transmit the data to the data transmission line 300, for example.
DC3 is output from the identifier decoding section 50. This identification output DC3 is applied to one input terminal of the AND gate 36, and the pulse signal from the C element 60 is applied to the other input terminal. AND gate 36 opens its gate and provides a pulse signal to C element 38. The C element 38 receives a transmission permission signal UK from the data transmission line 300.
32 is input, the pulse signal is sent to the register 31.
give to Therefore, the register 31 stores the data stored in the register 4 and transmits it to the data transmission path 3.
Transmit to 00.

On the other hand, the identification output DC3 is also given to the buffer 37. A C element 38 is connected to the input of the buffer 37.
_Q2 output “L” signal is given. At this time,
The outputs of buffers 17, 27 and 47 are in high impedance. Batsuhua 3
7 outputs the “L” signal from the C element 38 and applies it to the C element 60. As a result, the C element 60 does not transmit the pulse signal C ₀ to the register 4 even if the pulse signal C 0 is input thereto. That is, while transmitting data to the data transmission path 300 as described above, the C element 6
Since 0 does not give a pulse signal to the register 4, even if the next data is input to the register 4, the data will not be stored.

After transmitting the data stored in the register 31 to the data transmission path 300 as described above,
The transmission permission signal UK32 changes from "L" to "H", and the _Q2 output of the C element 38 becomes "H". Therefore, the output of the buffer 37 becomes "H", making it possible to transmit the next data. Then, as soon as the next data arrives at the register 4, or if it has already arrived, the above-described operation is repeated according to the identifier included in the data.

Effects of the Invention As described above, according to the present invention, a transmission permission signal is output to a subsequent stage to hold data and a part of the data or an identifier attached to the data, and a plurality of parallel outputs are provided. Of the side data transmission lines,
In response to determining that a transmission permission signal is output from the output data transmission path corresponding to the identifier, data can be output from the input data transmission path to the corresponding output data transmission path. Therefore,
Even if different types of data are input, each data can be transmitted to the desired output data transmission path, and wiring can be provided for each type of data.
There is no need to provide input/output ports, and the device can be configured easily. Therefore, if applied to packet communication, for example, the contents of the packets can be arranged in an arbitrary order by dividing the contents of the packets into parallel output data transmission paths and composing the data in a different order than when it was divided. It is also possible to change it.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment in which data is divided into two branches and transmitted. FIG. 2 is a specific circuit diagram of an embodiment in which data is divided into two branches. FIG. 3 is a schematic block diagram of an embodiment in which data is divided into four branches and transmitted. FIG. 4 is a specific circuit diagram of an embodiment in which data is divided into four branches and transmitted. FIG. 5 is a specific circuit diagram of another embodiment in which data is divided into four branches and transmitted. FIG. 6 is a detailed circuit diagram of another embodiment in which data is divided into four branches and transmitted. In the figure, 1,100,200,300,4
00 is a data transmission path, 2 is an identifier transmission path, 3, 5
0 is an identifier decoding unit, 10, 20, 30, 40 are control units, 4, 11, 21, 31, 41 are registers,
5, 15, 25, 35, 45 are D type flip-flops, 6, 7, 12, 13, 22, 23, 3
2, 33, 42, 43 are C elements, 14, 24, 3
4, 44 are OR gates, 4, 8, 16, 26, 3
6, 46, 80 are AND gates, 17, 27, 3
7 and 47 indicate buffers.

Claims (1)

[Claims] 1. Each of them is provided in parallel and holds data from the latter stage in response to outputting a transmission permission signal to the latter stage, and retains data in response to outputting a transmission permission signal from the former stage. Multiple output side data transmission lines that output
An input that receives data from the subsequent stage and a part of the data or an identifier for specifying a transmission path associated with the data, and outputs the data and identifier to the previous stage in response to a transmission permission signal given from the previous stage. a determining means for determining whether a transmission permission signal is output from each of the plurality of output data transmission paths, and a transmission permission signal is output from the output data transmission path corresponding to at least the identifier. data transmission, comprising a control means for controlling the data outputted from the input side data transmission path to be outputted to the corresponding output side data transmission path in response to the judgment means determining that the input side data transmission path is Device. 2. The control means, in response to the determination means determining that a transmission permission signal is output from all of the plurality of parallel output-side data transmission paths, transmits a part of the data or information attached to the data. 2. The data transmission device according to claim 1, wherein the data is transmitted to an output side data transmission path represented by an identifier. 3. The control means identifies an output-side data transmission path represented by a part of the data or an identifier attached to the data, among the plurality of parallel output-side data transmission paths, and controls the output-side data transmission. The data according to claim 1, wherein the data is transmitted to the output data transmission path in response to the determination means determining that data transmission is possible through the output data transmission path. Transmission device. 4. The control means includes: a first storage means for temporarily storing the data;
transmission path selection signal output means for outputting a transmission path selection signal indicating to which of the plurality of parallel output data transmission paths data should be transmitted based on the identifier; and the plurality of parallel output data transmission paths. a second storage means provided corresponding to each of the plurality of parallel output-side data transmission paths for storing the data; In response to being given a determination signal for determining that a transmission permission signal has been given to a data transmission path, and also being given a transmission path selection signal for selecting the output side data transmission path from the transmission path selection means. , transmission control means for storing data stored in the first storage means in a second storage means corresponding to the output data transmission path and transmitting the data to the output data transmission path. A data transmission device according to claim 2 or 3. 5. According to claim 2, the control means is configured to intermittent the identifier based on a clock signal when the identifier for selecting the same output-side data transmission path is consecutively given. data transmission equipment.