JPH01108661A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To realize fast transmission and to improve reliability by transmitting data autonomously to either transmission path according to a result decided by collating and comparing a branch destination designation bit or a branch destination designation logic and also, corresponding to the vacant/filled state of the transmission path of a preceding stage. CONSTITUTION:When the transmission path is set at a transmittable state, an identifier to designate the transmission path following information in a part of the data or the data is collated and compared and decided with the branch destination designation bit or the branch destination designation logic to designate either plural parallel transmission paths. And the data can be transmitted to either the plural parallel transmission paths according to the above result. In such a way, since a desired transmission path can be selected and the data can be transmitted even when different kind of data is transmitted to the transmission path, it is not required to provided an input/output port at every different kind of data or to provide a specific wiring.

Description

[Detailed Description of the Invention] [Industrial Application Field J] This invention relates to a data transmission device, and in particular, it autonomously and selectively transmits data transmitted at arbitrary time intervals to one of a plurality of parallel transmission paths. The present invention relates to a data transmission device for transmitting data to a computer.

[Background Art] In a data processing device using an electronic computer or the like, a plurality of processing units are coupled through communication using digital signals. When data processing is distributed and processed by a plurality of processing units, the content of the data processing in each processing unit is generally different, and the data required to perform each processing and the results obtained are also different. For example, there is a device disclosed in Japanese Patent Application No. 61-17544.

[Problems to be Solved by the Invention] When the above-mentioned plurality of processing device groups are combined, if the processing units that require data reception and transfer are wired for each data processing and an input/output port is provided, the hardware However, there are problems in that the system becomes very complicated, the device becomes large, and the cost becomes expensive.

Therefore, the main object of the present invention is to be able to transmit different types of data using the same data transmission path, and to identify data by using information that a part of the data has or an identifier attached to the data. It is an object of the present invention to provide a data transmission device that can specify a branch destination, reduce the amount of hardware wiring, and autonomously and selectively transmit data to a desired transmission path.

Means for Solving Problem E] The data transmission device according to the present invention autonomously and selectively transmits data that is transmitted at a time interval longer than that unique to a transmission path to one of a plurality of parallel transmission paths. A data transmission device configured to control data transmission by a transmission permission signal from each transmission path, and to specify information contained in a part of the data or a transmission path associated with the data. The identifier is compared and compared with a branch destination designation bit and branch destination designation logic that designate one of the plurality of parallel transmission paths, and data is transmitted to one of the plurality of parallel transmission paths according to the result. Alternatively, one of a plurality of parallel transmission paths is specified.

[Operation] In the data transmission device according to the present invention, when the transmission path to be transmitted is in a transmittable state, information contained in a part of the data or an identifier for specifying the transmission path accompanying the data and a plurality of Data can be transmitted to any one of a plurality of parallel transmission paths according to the result of comparing and determining the branch destination designation bit or branch destination designation logic that designates any one of the parallel transmission paths. Therefore, even if different types of data are transmitted through transmission lines, the desired transmission line can be selected and the data can be transmitted, so it is necessary to provide input/output ports or special wiring for each type of data. There will be no need.

[Embodiment of the Invention] FIG. 1 is a schematic block diagram of an apparatus for splitting data into two and transmitting the data according to an embodiment of the invention.

First, with reference to FIG. 1, an example of branching into two transmission paths for transmission will be described. The data transmission lines 10 and 20 used in the embodiment shown in FIG. 1 each include a transfer control section for transmitting data and a data holding means. The comparison/judgment logic unit 30 includes an identifier for specifying an output data transmission line which is a part of data, a branch destination specification bit for specifying one of a plurality of parallel output side data transmission lines, and a branch destination specification logic circuit. and a means for comparing and determining. The branch control unit 60 transmits data to one of the plurality of parallel output side data transmission paths according to the result of the comparison/judgment logic unit 30.

Next, the specific operation of the embodiment shown in FIG. 1 will be explained. In the initial state, transmission permission signals AKI and AK2 are sent back to the data transmission path 20 so that the output side data transmission path can receive them.

When data arrives on the data transmission path 10, the data and the transmission signal C10 are transmitted to the data transmission path 20, and an identifier for specifying the transmission path, which is part of the data, is also transmitted to the comparison/judgment logic unit 30. be done. The comparison/judgment logic unit 30 is given in advance a branch destination designation bit and a branch destination designation logic circuit that designate the output transmission line of the branch destination, and the bit and an identifier for designating the transmitted output transmission path. If they match, the MATCH signal output from the comparison/judgment logic unit 30 is set to "L+1", and if they do not match, it outputs "iiH". Branch control unit 60
Then, when the MATCH signal is 'L', EA is selected, and II
It is impossible for EB to be selected and 100 directions to be selected at the same time. In the case ', the data transmission line 20 is transmitted, and in the case of blockage, the data transmission line 20 is stopped until the data transmission line 20 becomes free.

Figure 2 shows an identifier for specifying an output data transmission line, which is part of the data, and a branch destination specification bit and branch destination specification logic circuit that specify one of multiple parallel output data transmission lines. FIG. 7 is a specific circuit diagram of an embodiment in which a comparison is made and data is sent to either of two output-side data transmission paths based on the judgment result. First, the configuration will be explained with reference to FIG. Data transmission lines lO and 20 in FIG. 1 are transfer control units 11 and 21, respectively.
and data holding means 12 and 22. Each transfer control unit 11 receives one transmission signal input.

1 transmission permission signal input, 1 transmission signal output and 1
Data transfer associated with handshake control is performed by outputting the actual transmission permission signal. The transfer control unit 21 has a built-in function to perform a logical sum on two different transmission permission signal inputs, and performs handshake transfer control similar to that of the transfer control unit 11, but the transmission signal output is 2. It has a CB high output with a faster timing than the Q1 output with a book. A detailed circuit diagram of the transfer control section 11 is shown in FIG. 3, and a detailed circuit diagram of the transfer control section 21 is shown in FIG. The comparison/judgment logic section 30 connects inverters 31, 32, 33, 34, 35, 36 and 37 and N
AND game) 38, 39, 40° 41.42, 43, 4
4, 45, 46, 47, 48, 49, and 50, and a comparator 51. The branch control section 60 is composed of a D-type flip-flop 61.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

In the initial state, a reset signal is applied to the transfer control units 11 and 21 and the D-type flip-flop 62. As a result, the transfer control units 11 and 21 are initially reset, and (7) the Ql output becomes "H" level, and the Q2 output also becomes "H" level. The D type flip-flop 62 sets the Q output to "H".

In this state, when data 1 is given to the data holding means 12 and transmission signal C10 is given to the transfer control section 11, the transfer control section 11 causes the Q2 output of the transfer control section 21 to become "H".
”, the Q1 output of the transfer control section 11 is transmitted to the transfer control section 21, and becomes a clock pulse of the data holding means 12, and the contents of data 1 are transferred to the data holding means 12. An identifier for specifying the output side data transmission line that is output to Qi and is part of the data is input to the comparison judgment logic unit 30.The comparison judgment logic unit 30 uses the branch destination designation bit (BRANCH bit) and the branch The matching of the identifiers for specifying the destination transmission path is performed, and the output of the comparison/judgment logic section 30 becomes "L'" or "i+H" in accordance with the logic specified by the BRANCH bit. On the other hand, when the transmission permission signals AKI and AK2 are "H", which means that transmission is possible, the transmission signal transmitted to the transfer control section 21 is sent to the branch control section 60 as a pulse signal CB that changes from "H" to "L". It also sends out the Q1 output, which becomes a clock pulse for the data holding means 22, and outputs the contents of data 1 to Qi of the data holding means 22.

In the comparison/judgment logic section 30, the MATCH signal which is the output of the comparison/judgment logic section 30 is latched by the D-type flip-flop 60 in response to the CB pulse signal from the transfer control section 22, and outputted to the output Q. The signals become EA and EB for setting the branch destination, and the transmission signal C10 and data 1 are autonomously branched and transmitted to either one of the output transmission paths.

[Effects of the Invention] As described above, according to the present invention, information contained in a part of data among a plurality of output side transmission paths or an identifier for specifying a transmission path associated with the data and a plurality of parallel According to the result of comparing and comparing with the branch destination designation bit or branch destination designation logic that specifies any of the output side transmission paths, and if the recent transmission path is empty! Since data is autonomously sent to one of the transmission paths depending on the clog condition, even if different types of data are input at completely arbitrary time intervals, each piece of data can be sent to the desired transmission path. It can be transmitted autonomously, and wiring can be set up for each type of data.
There is no need to provide a highly functional input/output port, data can be accepted up to the limit of the physical capacity of the transmission line, and data can be transmitted sequentially without any transmission delay time to the output side transmission line. Therefore, a high-speed transmission and a highly reliable transmission device can be realized economically.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. Figure 2 shows the results of a comparison between an identifier for specifying an output data transmission path, which is part of the data, and a branch destination designation bit that specifies one of multiple parallel output data transmission paths. , is a detailed circuit diagram of an example in which data is sent to either of two output-side data transmission paths. FIGS. 3 and 4 show an embodiment of the transfer control section. In the figure, 10.20 is a data transmission path, 30 is a comparison/judgment logic section, 60 is a branch control section, 11, 21 is a transfer control section, 12.22 is a data holding means, 31.32, 33, 3
4, 35, 36.37 are inverters, 38, 39, 40
,41,42,43゜44.45,46,47,48,
49.50 is a NAND gate, 51 is a comparator, 6
1 indicates a D type flip-flop. Agent Patent Attorney Takeshi Sugiyama (and 1 other person) -! U Written amendment to the same procedure (formality) February 2, 1986

Claims (1)

[Claims] 1. A data transmission device for autonomously and selectively transmitting data transmitted at arbitrary time intervals to any of a plurality of parallel transmission paths, the plurality of transmission paths comprising: Among them, an identifier or information for specifying a part of the data or a transmission path associated with the data is compared with a branch destination specification bit and branch destination specification logic that specify one of the plurality of parallel transmission paths. A data transmission device, comprising means for comparing and determining, and output means for transmitting the data to any of the plurality of parallel transmission paths.