JPH01238338A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To transmit/receive a data of two kinds of transmission bit rates with simple constitution by providing two kinds of data period detection circuits with respect to input data different from transmission bit rates and setting respective data transmission periods. CONSTITUTION:A 1st data period detection circuit 1 receiving an input data A detects a 1Mb PG data and sends a period signal B. The 1st gate circuit 2 receiving the signal B selects the input data in the period signal to send the 1st data C. A 2nd period detection circuit 3 receiving the signal B confirms data to be a data less than 1MbPS and sends a period signal E. Thus, the data of plural transmission bit rates in mixture on one transmission line are extracted with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing circuit used in the field of communication that requires a communication method for transmitting data at a plurality of transmission bit rates on one signal line. It is something.

Conventional technology In the past, for example, when transmitting and receiving data at two different transmission bit rates, two transmission lines were prepared, or one
When transmitting and receiving data over a real transmission path, it is necessary to confirm the transmission rate between the transmitter and the receiver before transmitting the data.

Problems to be Solved by the Invention However, no matter which of the above configurations is adopted, the configuration becomes complicated and poses a major problem in system construction. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to selectively extract data corresponding to each transmission bit rate from data having different transmission bit rates sent through a single transmission path using a simple method.

Means to solve problems Therefore, the present invention has the following configuration.

That is, a first data interval detection circuit receives input data having different transmission bit rates through one signal line and detects one type of data input interval from the input data;
The detection signal in the first data interval detection circuit is also 91
a second data interval detection circuit that detects a data input interval of input data of a type; and a second data interval detection circuit that receives the output of the first data interval detection circuit, the output of the second data interval detection circuit, and the input data; a first gate circuit for selectively outputting data; receiving the output of the second data interval detection circuit, the input data and an external clock;
a count circuit that samples input data in the output section of the second data section detection circuit with a clock and sends out a count signal; and a count circuit that samples the input data of the output section of the second data section detection circuit and sends out a count signal; The gate circuit receives the output of the detection circuit and the input data and selectively outputs another type of data. An interval detection circuit is provided, each data transfer interval is set, and one type of data is extracted by gating the input data and the interval. For the other type of data, the transmission bit rate within the above interval is monitored by a counting circuit, and if it is determined that the transmission bit rate is a predetermined transmission bit rate, the data is extracted by gated with the input data.

This makes it possible to transmit and receive data at two different transmission bit rates with a simple configuration.

Example Specific examples of the present invention will be described.

FIG. 1 shows a specific configuration example of the present invention.

In the figure, reference numeral 1 denotes a first data section detection circuit, which detects a reception section corresponding to a predetermined transmission bit rate from an input datum and sends out a section signal B.

2 is a first gate circuit that selects the input data in section signal B and sends out the first data C; 3 is a second data section detection circuit that selects the input data in section signal B and sends out the first data C; The corresponding reception section is detected and the section signal E is sent out.

Reference numeral 4 denotes a counting circuit which samples the input data in the section signal E using a clock D supplied from the outside, detects that a predetermined transmission bit rate has been received, and sends out the section signal F.

Reference numeral 6 denotes a second gate circuit which selects the input data in the interval signal F and sends out the second data G.Next, the specific operation will be explained.

First, the first data section detection circuit 1, which is supplied with input data, detects that the transmission bit rate of the input data is 1, for example.
MbPs and 1. Considering the case where sMbPS is received in a mixed manner, 1MbPS data (or 1MbPS
S or more data) is detected, and section signal B is sent out. (
This detection method may be, for example, count detection using retriggerable monomulti or sampling. ) The first gate circuit 2, which has been supplied with the section signal B, selects input data within the section signal and sends out the first data O. This data is 1 MbPS input data.

Next is another 1. Data extraction of sMbPs will be explained. The second data section detection circuit 3, which has received the section signal B, confirms that the data is 1 MbPS or less and sends out the section signal R. (This detection method is possible in the same manner as for the section signal B.) The count circuit 4, which has been supplied with the section signal E, samples the input data using the clock D that is supplied from the outside. If this count matches 1.5 MbPS, section signal F is sent out. In other words, the input data is transmitted at a transmission bit rate of 1.5 MbPS. By changing the sampling counting method (count number), it is possible to easily determine which transmission bit rate data is received.

The second gate circuit 6, which has received the section signal F, receives the input data (i.e., 1.
5MbPS) and sends out the second data G.

As is clear from the above description, it is possible to extract data of a plurality of transmission bit rates mixed on one transmission path with a simple configuration.

Effects of the Invention As described above, the present invention provides a receiving configuration that can selectively extract data of multiple transmission bit rates that are mixedly transmitted on one transmission path with a simple configuration, and also allows time-division transmission on the transmitting side. As a result, the efficiency of using the transmission line can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 0 1... First data interval detection circuit, 2...
...First gate circuit, 3...Second data interval detection circuit, 4...Count circuit, 5...
...Second gate circuit.

Claims (1)

[Claims] a first data interval detection circuit that receives input data having different transmission bit rates through one signal line and detects one type of data input interval from the input data;
a second data interval detection circuit that detects a data input interval of another type of input data from the detection signal of the data interval detection circuit;
a first gate circuit that receives the output of the data interval detection circuit and the input data and selects and outputs one type of data; a count circuit that receives the supply, samples input data in the output section of the second data section detection circuit with a clock, and sends out a count signal; A signal processing circuit comprising a gate circuit that receives the output of one data interval detection circuit and input data and selectively outputs another type of data.