JPH04102374A - Insulating gate type effect transistor - Google Patents

Abstract

PURPOSE:To acquire an insulating gate type field effect transistor whose transfer conductance changes in accordance with positive and negative of a gate voltage by forming a gate electrode of a polycrystalline silicon layer wherein a P-N junction is formed. CONSTITUTION:A gate electrode 4 is composed of a polycrystalline silicon layer wherein a P-N junction is formed. A P<+> polycrystalline silicon layer 4b is formed in an N<+> polycrystalline silicon layer 4a and others are formed like a conventional example. Since a space region width in the P-N junction changes in accordance with positive and negative of a gate voltage and a voltage distribution in MOS structure changes, transfer conductance changes in accordance with positive and negative of the gate voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor such as a MOSFET.

[Prior art] Figure 5 shows a conventional polycrystalline silicon gate MOSFET.
In Figure 0, which shows an N-channel normally-on MO3FET, l is an N-type substrate, 2 is a
3 is a source, 3 is a drain, 4 is an N polycrystalline silicon gate, 5 is a gate oxide film, 6 is a channel, 7 is a source electrode, and 8 is a drain electrode.

[Problems to be Solved by the Invention] By the way, aluminum was used for the gate electrode of MOSFET before polycrystalline silicon was used.
The reality is that polycrystalline Noricon was only pursued as a substitute for metal (aluminum), and its properties as a semiconductor were not considered.

The present invention has been made in view of the above-mentioned reasons, and an object thereof is to provide an insulated gate field effect transistor whose transfer conductance changes depending on whether the gate voltage is positive or negative.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an insulated gate field effect transistor in which a gate electrode is made of polycrystalline silicon with impurities diffused therein, in which a PN junction is formed in the gate electrode. It is characterized by being composed of a polycrystalline silicon layer.

[Function] According to the present invention, since a PN junction is formed in the polycrystalline Noricon gate, the spatial region width at the PN junction changes depending on the positive or negative gate voltage, and the voltage distribution in the MO3 structure changes. , the transfer conductance changes depending on whether the gate voltage is positive or negative.

[Embodiment] FIG. 1 is a cross-sectional view showing an embodiment of the present invention. The difference from the conventional example is that the gate electrode 4 is composed of a polycrystalline silicon layer in which a PN junction is formed, so that the N. Since the other structures are the same as those of the prior art example except that the P polycrystalline silicon layer 4b is formed on the crystalline silicon layer 4a, the explanation will be omitted by assigning the same reference numerals to the same structures.

Figures 2 (a) and (b) are schematic representations of the energy diagrams of the MO3 structures according to the conventional example and the above example, respectively, focusing only on the work function. A depletion layer is formed in the silicon gate as shown in FIG. 2 0)).

Since a PN junction is formed in the polycrystalline silicon gate, the width of the depletion layer of the PN junction changes depending on whether the gate voltage is positive or negative, so the voltage distribution in each MO3 structure is different. Therefore, as shown in Fig. 3, the conventional transfer conductance g
, with respect to the gate oxide film vG, exhibits the characteristics as given by the graph in FIG. This characteristic is shown in FIG. 3(b). However, FIG. 3 shows a schematic example.

The above characteristics are explained using a schematic energy diagram shown in FIG. In other words, in the same figure (al is the gate voltage ■6
When is positive, the gate voltage (in the same figure) is ■.

This is the case when is negative. The voltage distribution differs depending on whether the gate voltage (■) is positive or negative. Furthermore, the depletion layer width W0 is also different.

[Effects of the Invention] As described above, the present invention provides an insulated gate field effect transistor in which the transfer conductance changes depending on the positive or negative gate voltage by forming a PN junction in the polycrystalline silicon gate. .

[Brief explanation of drawings]

Figure 1 is a sectional view showing one embodiment of the present invention, Figure 2 (a)
, (t)l are the MOs according to the conventional example and the above embodiment, respectively.
5 structure, Figures 3 (a) and (b) are diagrams showing the relationship between transfer conductance and gate voltage for the conventional example and the above embodiment, respectively, and Figures 4 (a) and (bl are for the conventional example, respectively). FIG. 5 is a cross-sectional view showing a conventional example. 1...Substrate, 2...・Source, 3...Drain, 4
... Polycrystalline Noricon gate, 5... Gate oxide film,
6... Channel, 7... Source electrode, 8... Drain electrode. Figure 3 (a) (b)

Claims (1)

[Claims] (1) In an insulated gate field effect transistor whose gate electrode is made of polycrystalline silicon with impurity diffused,
An insulated gate field effect transistor characterized in that the gate electrode is made of a polycrystalline silicon layer in which a PN junction is formed.