JPS63273361A - Mos field-effect transistor - Google Patents
Mos field-effect transistorInfo
- Publication number
- JPS63273361A JPS63273361A JP62108318A JP10831887A JPS63273361A JP S63273361 A JPS63273361 A JP S63273361A JP 62108318 A JP62108318 A JP 62108318A JP 10831887 A JP10831887 A JP 10831887A JP S63273361 A JPS63273361 A JP S63273361A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- effect transistor
- source region
- type
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000000903 blocking effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳ電界効果トランジスタに関し、特に縦形
のＭＯＳ電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS field effect transistor, and more particularly to a vertical MOS field effect transistor.
一般に、縦形のＭＯＳ電界効果トランジスタは中電力以
上のパワー機器に応用されるので、その電圧破壊耐量の
改善が常に話題となっている。In general, vertical MOS field effect transistors are applied to power equipment with medium or higher power, so improvement of their voltage breakdown capability is always a hot topic.
第２図（ａ）および（ｂ）は、従来のＭＯＳ電界効果ト
ランジスタの一例の半導体チップの断面図及び等価回路
図である。FIGS. 2(a) and 2(b) are a sectional view and an equivalent circuit diagram of a semiconductor chip of an example of a conventional MOS field effect transistor.
第２図（ａ）に示すように、ＭＯＳ電界効果トランジス
タ１０は、ｎ形シリコン基板１の一主面にｐ形ベース領
域２を選択的に形成し、さらにその一部にｎ形ソース領
域３を形成する。As shown in FIG. 2(a), the MOS field effect transistor 10 has a p-type base region 2 selectively formed on one principal surface of an n-type silicon substrate 1, and an n-type source region 3 formed in a part of the p-type base region 2. form.
ｐ形ベース領域２に囲まれるｎ形シリコン基板１の表面
にゲート酸化膜４を介してｎ形多結晶シリコン層のゲー
ト電極５を形成し、ｐ形ベース領域２とｎ形ソース領域
３にまたがってソース電極７を設け、さらにｎ形シリコ
ン基板１の他の主面にドレイン電極６を設けた縦形ＭＯ
３の構造となっている。A gate electrode 5 of an n-type polycrystalline silicon layer is formed on the surface of the n-type silicon substrate 1 surrounded by the p-type base region 2 via a gate oxide film 4, and extends over the p-type base region 2 and the n-type source region 3. A vertical MO in which a source electrode 7 is provided on the other main surface of the n-type silicon substrate 1 and a drain electrode 6 is provided on the other main surface of the n-type silicon substrate 1.
It has a structure of 3.
上述した従来のＭＯ３電界効果トランジスタは、ソース
電極７とのｎ形結晶シリコン層のゲート電極５がゲート
酸化膜４によって絶縁されているので、ソース及びゲー
ト電極間に高電圧が印加された場合に、ゲート酸化膜４
が絶縁破壊を起してソース及びゲート電極間が短絡し易
いという問題があった。In the conventional MO3 field effect transistor described above, since the gate electrode 5 of the n-type crystal silicon layer is insulated from the source electrode 7 by the gate oxide film 4, when a high voltage is applied between the source and gate electrodes, , gate oxide film 4
However, there is a problem in that dielectric breakdown occurs, which tends to cause a short circuit between the source and gate electrodes.
一般に行われる静電破壊耐量試験では、例えば２００ｐ
Ｆのコンデンサに電圧ＶＣの電荷を充実し、その放電エ
ネルギーの強さとして放電電圧■ｃを用いているが、従
来はゲート端子Ｇとソース端子Ｓとの絶縁耐圧が２００
Ｖに耐えるのは難しかった。In a commonly conducted electrostatic breakdown test, for example, 200p
The capacitor F is charged with the voltage VC, and the discharge voltage ■c is used as the strength of the discharge energy, but conventionally, the insulation voltage between the gate terminal G and the source terminal S is 200
It was difficult to endure V.
本発明の目的は、ソース及びゲート端子間の静電破壊耐
量の高いＭＯ３電界効果トランジスタを提供することに
ある。An object of the present invention is to provide an MO3 field effect transistor with high electrostatic breakdown resistance between the source and gate terminals.
本発明のＭＯ３電界効果トランジスタは、−導電形の半
導体基板の一主面に選択的に形成された逆導電形のベー
ス領域と、該ベース領域内に設けられた一導電形のソー
ス領域と、前記ベース領域に囲まれた前記半導体基板の
表面に絶縁膜を介して設けられた一導電形の多結晶シリ
コン層のゲート電極と他の主面に設けられたドレイン電
極とを含むＭＯ３電界効果トランジスタにおいて、前記
ゲート電極と前記ソース領域のそれぞれの表面にまたが
って設けた金属層によりショットキー接合部を形成して
前記ゲート電極と前記ソース領域との間に逆直列接続の
ショットキーバリヤダイオード対を設けて構成されてい
る。The MO3 field effect transistor of the present invention includes: a base region of an opposite conductivity type selectively formed on one principal surface of a semiconductor substrate of a − conductivity type; a source region of one conductivity type provided within the base region; An MO3 field effect transistor including a gate electrode of a polycrystalline silicon layer of one conductivity type provided on the surface of the semiconductor substrate surrounded by the base region via an insulating film, and a drain electrode provided on the other main surface. A Schottky junction is formed by a metal layer provided over surfaces of each of the gate electrode and the source region, and a pair of Schottky barrier diodes are connected in anti-series between the gate electrode and the source region. It is set up and configured.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ＞及び（ｂ）は本発明の一実施例の半導体チ
ップの断面図及び等価回路図である。FIGS. 1A and 1B are a sectional view and an equivalent circuit diagram of a semiconductor chip according to an embodiment of the present invention.
第１図（ａ）に示すように、ＭＯＳ電界効果トランジス
タ９は、第２図（ａ）のＭＯＳ電界効果トランジスタ１
０のｎ形ソース領域３とｎ形多結晶シリコン層のゲート
電極５のそれぞれの表面の一部にまたがってモリブデン
層１１を設けた以外は同一である。As shown in FIG. 1(a), the MOS field effect transistor 9 is the same as the MOS field effect transistor 1 in FIG. 2(a).
The structure is the same except that a molybdenum layer 11 is provided over part of the surface of each of the n-type source region 3 and the gate electrode 5 of the n-type polycrystalline silicon layer.
第１図（ｂ）に示すように、モリブデン層１１はｎ形ソ
ース領域３との間及びｎ形多結晶シリコン層のゲート電
極５との間にそれぞれショットキー接合を形成するので
、ソース端子Ｓとゲート端子Ｇとの間に等価回路として
、逆直列のショットキーバリヤダイオード対が設けられ
たことになる。As shown in FIG. 1(b), the molybdenum layer 11 forms a Schottky junction with the n-type source region 3 and the gate electrode 5 of the n-type polycrystalline silicon layer, so that the source terminal S This means that a pair of anti-series Schottky barrier diodes is provided between the gate terminal G and the gate terminal G as an equivalent circuit.
例えば、ショットキーバリヤダイオードの逆阻止電圧Ｖ
、が２５Ｖで、逆梁等電力耐量が１５０Ｗ ／ ｍ ｍ
２とすると、ゲート端子Ｇとソース端子Ｓ間の静電破
壊耐量試験で、放電電圧ＶＣが２００Ｖでも破壊しなく
なった。For example, the reverse blocking voltage V of a Schottky barrier diode
, is 25V, and the power capacity of the reverse beam is 150W/mm
2, in an electrostatic breakdown test between the gate terminal G and source terminal S, no breakdown occurred even when the discharge voltage VC was 200V.
以上説明したように本発明は、ゲート電極とソース電極
間に逆直列のショットキーバリヤダイオード対を設ける
ことにより、静電破壊耐量の高いＭＯ３電界効果トラン
ジスタを得る効果がある。As described above, the present invention has the effect of providing an MO3 field effect transistor with high electrostatic breakdown resistance by providing an anti-series pair of Schottky barrier diodes between the gate electrode and the source electrode.
第１図（ａ）及び（ｂ）は本発明の一実施例の半導体チ
ップの断面図及び透過回路図、第２図（ａ）及び（ｂ）
は従来のＭＯ３電界効果トランジスタの一例の半導体チ
ップの断面図及び等価回路図である。
１・・・ｎ形シリコン基板、２・・・ｐ形ベース領域、
３・・・ｎ形ソース領域、４・・・ゲート酸化膜、５・
・・ｎ形多結晶シリコン層のゲート電極、６・・・ドレ
イン電極、７・・・ソース電極、１１・・・モリブデン
層、ＳＢＤ・・・ショットキーバリヤダイオード。
ぐ−
代理人 弁理士 内 原 晋ｔ、５（（、”−
茅 ｌ 図
り
弄 ２ 回FIGS. 1(a) and (b) are a cross-sectional view and a transparent circuit diagram of a semiconductor chip according to an embodiment of the present invention, and FIGS. 2(a) and (b) are
1 is a cross-sectional view and an equivalent circuit diagram of a semiconductor chip of an example of a conventional MO3 field effect transistor. 1... N-type silicon substrate, 2... P-type base region,
3... N-type source region, 4... Gate oxide film, 5...
...Gate electrode of n-type polycrystalline silicon layer, 6...Drain electrode, 7...Source electrode, 11...Molybdenum layer, SBD...Schottky barrier diode. Gu- Agent Patent Attorney Susumu Uchihara, 5
Claims (1)
逆導電形のベース領域と、該ベース領域内に設けられた
一導電形のソース領域と、前記ベース領域に囲まれた前
記半導体基板の表面に絶縁膜を介して設けられた一導電
形の多結晶シリコン層のゲート電極と他の主面に設けら
れたドレイン電極とを含むＭＯＳ電界効果トランジスタ
において、前記ゲート電極と前記ソース領域のそれぞれ
の表面にまたがって設けた金属層によりショットキー接
合部を形成して前記ゲート電極と前記ソース領域との間
に逆直列接続のショットキーバリヤダイオード対を設け
たことを特徴とするＭＯＳ電界効果トランジスタ。a base region of an opposite conductivity type selectively formed on one principal surface of a semiconductor substrate of one conductivity type; a source region of one conductivity type provided within the base region; and the semiconductor surrounded by the base region. In a MOS field effect transistor including a gate electrode of a polycrystalline silicon layer of one conductivity type provided on a surface of a substrate via an insulating film and a drain electrode provided on the other main surface, the gate electrode and the source region A MOS electric field characterized in that a Schottky junction is formed by a metal layer provided over each surface of the gate electrode, and a Schottky barrier diode pair connected in anti-series is provided between the gate electrode and the source region. effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62108318A JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62108318A JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63273361A true JPS63273361A (en) | 1988-11-10 |
| JPH0671084B2 JPH0671084B2 (en) | 1994-09-07 |
Family
ID=14481670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62108318A Expired - Fee Related JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671084B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286490B1 (en) * | 1994-09-13 | 2001-04-16 | 니시무로 타이죠 | Semiconductor device |
-
1987
- 1987-04-30 JP JP62108318A patent/JPH0671084B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286490B1 (en) * | 1994-09-13 | 2001-04-16 | 니시무로 타이죠 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0671084B2 (en) | 1994-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |