JPH0671084B2 - MOS field effect transistor - Google Patents
MOS field effect transistorInfo
- Publication number
- JPH0671084B2 JPH0671084B2 JP62108318A JP10831887A JPH0671084B2 JP H0671084 B2 JPH0671084 B2 JP H0671084B2 JP 62108318 A JP62108318 A JP 62108318A JP 10831887 A JP10831887 A JP 10831887A JP H0671084 B2 JPH0671084 B2 JP H0671084B2
- Authority
- JP
- Japan
- Prior art keywords
- effect transistor
- field effect
- mos field
- base region
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOS電界効果トランジスタに関し、特に縦形のM
OS電界効果トランジスタに関する。The present invention relates to a MOS field effect transistor, and more particularly to a vertical M field effect transistor.
OS Field effect transistor.
一般に、縦形のMOS電界効果トランジスタは中電力以上
のパワー機器に応用されるので、その電圧破壊耐量の改
善が常に話題となっている。In general, vertical MOS field-effect transistors are applied to power devices of medium power or higher, so that improvement in withstand voltage breakdown has always been a topic.
第２図（ａ）および（ｂ）は、従来のMOS電界効果トラ
ンジスタの一例の半導体チップの断面図及び等価回路図
である。2A and 2B are a sectional view and an equivalent circuit diagram of a semiconductor chip as an example of a conventional MOS field effect transistor.
第２図（ａ）に示すように、MOS電界効果トランジスタ1
0は、ｎ形シリコン基板１の一主面にｐ形ベース領域２
を選択的に形成し、さらにその一部にｎ形ソース領域３
を形成する。As shown in FIG. 2 (a), the MOS field effect transistor 1
0 indicates a p-type base region 2 on one main surface of the n-type silicon substrate 1.
Of the n-type source region 3
To form.
ｐ形ベース領域２に囲まれるｎ形シリコン基板１の表面
にゲート酸化膜４を介してｎ形多結晶シリコン層のゲー
ト電極５を形成し、ｐ形ベース領域２とｎ形ソース領域
３にまたがってソース電極７を設け、さらにｎ形シリコ
ン基板１の他の主面にドレイン電極６を設けた縦形MOS
の構造となっている。A gate electrode 5 of an n-type polycrystalline silicon layer is formed on the surface of the n-type silicon substrate 1 surrounded by the p-type base region 2 with a gate oxide film 4 interposed between the p-type base region 2 and the n-type source region 3. Vertical MOS having a source electrode 7 and a drain electrode 6 on the other main surface of the n-type silicon substrate 1.
It has a structure of.
上述した従来のMOS電界効果トランジスタは、ソース電
極７とのｎ形結晶シリコン層のゲート電極５がゲート酸
化膜４によって絶縁されているので、ソース及びゲート
電極間に高電圧が印加された場合に、ゲート酸化膜４が
絶縁破壊を起してソース及びゲート電極間が短絡し易い
という問題があった。In the conventional MOS field effect transistor described above, since the source electrode 7 and the gate electrode 5 of the n-type crystalline silicon layer are insulated by the gate oxide film 4, when a high voltage is applied between the source and the gate electrode. However, there is a problem that the gate oxide film 4 causes a dielectric breakdown and a short circuit easily occurs between the source and the gate electrode.
一般に行われる静電破壊耐量試験では、例えば200pFの
コンデンサに電圧Vcの電荷を充実し、その放電エネルギ
ーの強さとして放電電圧Vcを用いているが、従来はゲー
ト端子Ｇとソース端子Ｓとの絶縁耐圧が200Vに耐えるの
は難しかった。In a generally performed electrostatic breakdown withstand test, for example, a capacitor of 200 pF is filled with an electric charge of voltage Vc, and the discharge voltage Vc is used as the strength of the discharge energy. It was difficult to withstand withstand voltage of 200V.
本発明の目的は、ソース及びゲート端子間の静電破壊耐
量の高いMOS電界効果トランジスタを提供することにあ
る。An object of the present invention is to provide a MOS field effect transistor having a high electrostatic breakdown resistance between the source and gate terminals.
本発明のMOS電界効果トランジスタは、一導電形の半導
体基板の一主面に選択的に形成された逆導電形のベース
領域と、該ベース領域内に設けられた一導電形のソース
領域と、前記ベース領域に囲まれた前記半導体基板の表
面に絶縁膜を介して設けられた一導電形の多結晶シリコ
ン層のゲート電極と他の主面に設けられたドレイン電極
とを含むMOS電界効果トランジスタにおいて、前記ゲー
ト電極と前記ソース領域のそれぞれの表面にまたがって
設けた金属層によりショットキー接合部を形成して前記
ゲート電極と前記ソース領域との間に逆直列接続のショ
ットキーバリヤダイオード対を設けて構成されている。The MOS field effect transistor of the present invention comprises a base region of opposite conductivity type selectively formed on one main surface of a semiconductor substrate of one conductivity type, and a source region of one conductivity type provided in the base region. MOS field effect transistor including a gate electrode of a polycrystalline silicon layer of one conductivity type provided on the surface of the semiconductor substrate surrounded by the base region via an insulating film and a drain electrode provided on the other main surface In, a Schottky junction is formed by a metal layer provided over each surface of the gate electrode and the source region, and a Schottky barrier diode pair of anti-series connection is formed between the gate electrode and the source region. It is provided and configured.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の一実施例の半導体チ
ップの断面図及び等価回路図である。1A and 1B are a sectional view and an equivalent circuit diagram of a semiconductor chip according to an embodiment of the present invention.
第１図（ａ）に示すように、MOS電界効果トランジスタ
９は、第２図（ａ）のMOS電界効果トランジスタ10のｎ
形ソース領域３とｎ形多結晶シリコン層のゲート電極５
のそれぞれの表面の一部にまたがってモリブデン層11を
設けた以外は同一である。As shown in FIG. 1A, the MOS field effect transistor 9 is the same as the n-type MOS field effect transistor 10 shown in FIG.
-Type source region 3 and gate electrode 5 of n-type polycrystalline silicon layer
The molybdenum layer 11 is the same except that the molybdenum layer 11 is provided so as to extend over part of the respective surfaces.
第１図（ｂ）に示すように、モリブデン層11はｎ形ソー
ス領域３との間及びｎ形多結晶シリコン層のゲート電極
５との間にそれぞれショットキー接合を形成するので、
ソース端子Ｓとゲート端子Ｇとの間に等価回路として、
逆直列のショットキーバリヤダイオード対が設けられた
ことになる。As shown in FIG. 1B, the molybdenum layer 11 forms a Schottky junction with the n-type source region 3 and with the gate electrode 5 of the n-type polycrystalline silicon layer.
As an equivalent circuit between the source terminal S and the gate terminal G,
An anti-series Schottky barrier diode pair is provided.
例えば、ショットキーバリヤダイオードの逆阻止電圧Ｖ
Ｒが25Vで、逆尖等電力耐量が150W/mm2とすると、ゲー
ト端子Ｇとソース端子Ｓ間の静電破壊耐量試験で、放電
電圧ＶＣが200Vでも破壊しなくなった。For example, the reverse blocking voltage V of the Schottky barrier diode
R is 25V, the reverse leaflet like power absorption capability and 150 W / mm 2, an electrostatic breakdown tolerance test between the gate terminal G and source terminal S, a discharge voltage V C is no longer destroyed even 200V.
以上説明したように本発明は、ゲート電極とソース電極
間に逆直列のショットキーバリヤダイオード対を設ける
ことにより、静電破壊耐量の高いMOS電界効果トランジ
スタを得る効果がある。As described above, the present invention has an effect of obtaining a MOS field effect transistor having a high electrostatic breakdown resistance by providing an anti-series Schottky barrier diode pair between the gate electrode and the source electrode.
第１図（ａ）及び（ｂ）は本発明の一実施例の半導体チ
ップの断面図及び透過回路図、第２図（ａ）及び（ｂ）
は従来のMOS電界効果トランジスタの一例の半導体チッ
プの断面図及び等価回路図である。 １……ｎ形シリコン基板、２……ｐ型ベース領域、３…
…ｎ形ソース領域、４……ゲート酸化膜、５……ｎ形多
結晶シリコン層のゲート電極、６……ドレイン電極、７
……ソース電極、11……モリブデン層、SBD……ショッ
トキーバリヤダイオード。1 (a) and 1 (b) are a sectional view and a transparent circuit diagram of a semiconductor chip according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b).
FIG. 4A is a sectional view and an equivalent circuit diagram of a semiconductor chip as an example of a conventional MOS field effect transistor. 1 ... n-type silicon substrate, 2 ... p-type base region, 3 ...
... n-type source region, 4 ... gate oxide film, 5 ... gate electrode of n-type polycrystalline silicon layer, 6 ... drain electrode, 7
...... Source electrode, 11 …… Molybdenum layer, SBD …… Schottky barrier diode.
Claims (1)
形成された逆導電形のベース領域と、該ベース領域内に
設けられた一導電形のソース領域と、前記ベース領域に
囲まれた前記半導体基板の表面に絶縁膜を介して設けら
れた一導電形の多結晶シリコン層のゲート電極と他の主
面に設けられたドレイン電極とを含むMOS電界効果トラ
ンジスタにおいて、前記ゲート電極と前記ソース領域の
それぞれの表面にまたがって設けた金属層によりショッ
トキー接合部を形成して前記ゲート電極と前記ソース領
域との間に逆直列接続のショットキーバリヤダイオード
対を設けたことを特徴とするMOS電界効果トランジス
タ。1. A base region of opposite conductivity type selectively formed on one main surface of a semiconductor substrate of one conductivity type, a source region of one conductivity type provided in the base region, and a base region on the base region. In a MOS field effect transistor including a gate electrode of a polycrystalline silicon layer of one conductivity type provided on the surface of the semiconductor substrate surrounded by an insulating film and a drain electrode provided on the other main surface, A Schottky junction is formed by a metal layer provided over the surface of each of the electrode and the source region, and an anti-series Schottky barrier diode pair is provided between the gate electrode and the source region. Characteristic MOS field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62108318A JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62108318A JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63273361A JPS63273361A (en) | 1988-11-10 |
| JPH0671084B2 true JPH0671084B2 (en) | 1994-09-07 |
Family
ID=14481670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62108318A Expired - Fee Related JPH0671084B2 (en) | 1987-04-30 | 1987-04-30 | MOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671084B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960012413A (en) * | 1994-09-13 | 1996-04-20 | Inclined incident multispectral interferometer device and method for measuring total surface height error in substrate surface and total thickness of substrate using same |
-
1987
- 1987-04-30 JP JP62108318A patent/JPH0671084B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63273361A (en) | 1988-11-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |