KR100286490B1 - Semiconductor device - Google Patents

Abstract

The present invention is to improve the driving force of the MIS-type FET, the gate electrode 2 is formed on the p-type substrate 1 via the insulating film 3, the gate electrode 2 of the substrate 1 immediately N-type source / drain regions 5 and 6 are formed on both sides of the channel formation region 4 below, the insulating film 3 has a Tox of less than 2.5 nm, and the length Lg of the gate electrode 2 is 0.3. It becomes micrometer or less. In addition, the FET is preferably used in a circuit having a power supply voltage of 1.5 V or less.

According to the present invention, it is possible to improve the driving power 1 and conductance gm and to reduce the tunnel current Id2.

Description

Semiconductor device

1 is a device cross-sectional view showing the structure of a MOS transistor according to a first embodiment of the present invention;

2 is an impurity concentration profile diagram of the transistor shown in FIG.

3 is a curve diagram showing the gate oxide film thickness dependence of the deterioration amount of the mutual conductance under the hot carrier stress (Vd = 2.5V, lsubmax, 1000 sec stress applied) of the transistor;

4 is a curve diagram showing the dependence of the gate length Lg of the tunnel current Ig of the transistor (W = 10 μm),

5 is a curve diagram (W = 10 mu m) showing the dependence of the gate length Lg of the drain current IdO of the transistor;

6 is a curve diagram (W = 10 μm) showing the dependence of the gate length Lg of the tunnel current Ig of the transistor;

7 is a curve diagram (W = 10 μm) showing the dependence of the gate length Lg of the conductance gm of the transistor,

8A is a curve diagram showing the dependence of the gate length Lg of the substrate maximum current Isubmax of the transistor (W = 10 μm),

8b is a curve diagram showing the gate voltage dependence of the substrate current Isub of the transistor (W = 10 mu m);

9 is a curve diagram showing the dependence of the gate length (Lg) on the impact ionization rate of the transistor (W = 10 mu m),

10 is a curve diagram showing the dependence of the power supply voltage (Vd = Vg) of the current (Ig, Id) of the transistor (Lg = 0.14 µm, W = 10 µm),

11 is a curve diagram showing the dependence of the power supply voltage (Vd = Vg) of the drain current (Id) of the transistor;

12 is a curve diagram showing the dependence of the power supply voltage (Vd = Vg) of Ig / Id of the transistor;

13 is a curve diagram showing the gate length dependency of the Ig-Id characteristics of the transistor;

14 is a curve diagram showing the gate length dependency of the conductance gm of the transistor;

FIG. 15 is a curve diagram comparing the characteristics of the conventional transistor with respect to the main characteristics of the transistor of the present invention (power supply voltage 0.5V),

16 is a curve diagram showing the effective field dependence of carrier mobility;

FIG. 17 is a curve diagram showing the deterioration of the conductance (gm) of the MOS transistor according to the first embodiment of the present invention (degradation of mutual conductance with respect to stress time),

18A is a schematic explanatory diagram showing the configuration of a semiconductor device in which semiconductor devices in all areas are made of the MOSFET of the present invention as an example of the semiconductor device according to the present invention;

18B is a schematic explanatory diagram showing the structure of a semiconductor device in which the MOSFET of the present invention is manufactured in a part of the region;

18C is a schematic explanatory diagram showing the structure of a semiconductor device including a MOSFET of the present invention in a peripheral region;

19 is a schematic explanatory diagram showing a configuration of a conventional example of a high speed semiconductor device formed of a bipolar transistor and a CMOS transistor;

20 is a curve diagram showing the voltage dependence of the interconductance of Lg = 0.09µm and Tox = 1.5nm transistor,

21 is a curve diagram showing power supply voltage dependence of mutual conductance;

22 is a curve diagram showing the power supply voltage dependence of the current driving force per unit,

23 is a curve diagram showing the gate current ratio Ig / Id to the channel current with respect to the gate length Lg;

24 is a curve diagram showing the characteristics (Id-Vd characteristic (a), gm-Vg characteristic (b)) of Tox = 1.5 nm, Lg = 0.2 µm pMOS transistor,

25a shows an Lg = 0.4 mu m, Tox = 9 nm transistor (traditional example), Lg = 0.1 mu m, Tox = 3 nm transistor (traditional example), Lg = 0.14 mu m and Lg = 0.99 mu m, Tox = 1.5 nm transistor (invention) Is a curve diagram showing the relationship between the clock frequency and the power consumption determined by the accumulation elimination and sub-threshold leakage,

25b is a curve diagram illustrating a relationship between a power consumption component determined by a clock frequency and a gate leakage current;

Figure 26 shows Lg = 0.4 mu m, Tox = 9 nm transistor (traditional example), Lg = 0.1 mu m, Tox = 3 nm transistor (traditional example), Lg = 0.14 mu m and Lg = 0.99 mu m, Tox = 1.5 nm transistor (invention) Is a curve diagram showing the relationship between power consumption and clock frequency at the same power consumption or the same clock frequency condition as all transistors,

FIG. 27A shows Ig-Vg characteristics of gate insulating films having various thicknesses (Tox) used in conventional tunnel gate oxide MOSFETs. FIG. 27A is a curve diagram showing more types of gate insulating films.

27B is a curve diagram showing the rectification of the thickness of the gate insulating film and detailing the gate insulating film of the limited type;

28 is a curve diagram showing the relationship between gate leakage current and gate length when a tunnel gate oxide film is applied to a MOSFET;

FIG. 29A is a circuit diagram for preparing a semiconductor device using a MOSFET with a gate insulating film protection according to the present invention compared with the conventional one;

29B is a circuit diagram of the present invention for preparing a semiconductor device using a MOSFET with a gate insulating film protection according to the present invention compared with the conventional one;

30a is a conventional circuit diagram for contrasting the structure of a MOSFET designed to reduce the gate leakage current according to the present invention;

30B is a circuit diagram of the present invention for contrasting the structure of a MOSFET with a reduction in gate leakage current according to the present invention.

<Explanation of symbols for main parts of drawing>

1: semiconductor substrate 2: gate electrode

3: gate oxide film 4: channel forming region

5: source region 6: drain region

7 gate power 8 drain power

9: MOSFET with normal gate length

10: low voltage power source 11: Schottky diode

12: MOSFET with fine gate length

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and in particular, to a fine, high performance MOS transistor suitable for use under low power supply voltage.

[Conventional Technology and Its Problems]

In particular, in the MOS transistors, the area of the gate length of 0.5 µm or less has been studied in each part due to the improvement of the MOSFET integration technology. In 1974, R. L. Dennard et al. Proposed the so-called scaling law for the miniaturization of MOSFETs. This is a law that protects the operating characteristics as a transistor by reducing the size of certain components (e.g., channel length) of the device by reducing other components in the same ratio. Basically, the integration of MOSLSI, which continued from the 1970s to the early 90s, was realized on the basis of this law.

However, further miniaturization progresses, and the limit value like the "physical limit value" also approaches in various components, and reduction of the value beyond that value is difficult. For example, it is generally mentioned that the thickness of the gate insulating film is about 3 to 4 nm, which is the limit of thinning. Below this thickness, it is known that the tunneling current between the gate electrode and the source / drain electrodes increases, so that normal operation as a transistor cannot be realized. have.

Therefore, a method of fixing the gate insulating film to about 3 nm and considering reduction of other components has been proposed by Piena et al. In 1993 (authors C. Fiegna, H. Iwai, T. Wada, T. Saito, E). Sangiorgio, and B. Ricco; A New scaling methodology for the 0.1-0.025 μm MOSFET, 'Dig. Of Tech. Papers, VLSI Symp .; Source Technol., Kyoto, pp, 33-34, 1993). By the same method, a transistor having a gate length of 0.04 μm was realized by Ono et al. (Authors M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai; 50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junction; see IEDM Tech, Dig., Pp119-122, 1993).

A transistor having a gate switching film thickness of 3 nm and a gate length of 0.04 mu m is manufactured as follows. First, an element region and an isolation region are formed on a p-type silicon substrate by a local oxide of silicon (LOCOS) method, and then p-type impurities (for example, B (boron)) are formed in the channel formation region so that a desired threshold voltage is obtained. Introduce.

Thereafter, an oxide film of 3 nm is formed on the surface of the silicon substrate as a gate oxide film, for example, by oxidation at 800 ° C. for 10 minutes in a dry 0 ₂ atmosphere. Thereafter, for example, 100 nm of polysilicon is deposited under P (phosphorus) -containing conditions, and then a resist is applied and patterned to process the gate electrode to a desired length. The introduction of the n-type impurity into the source / drain formation region is formed by solid phase diffusion of P from the PSG film (P (phosphorus-containing silicon oxide film)) left in the gate electrode sidewall portion. For the purpose of making a good connection with the metal wiring part and making the diffusion layer of the part which does not affect the short channel effect of the transistor low resistance, n-type impurities are then implanted, for example, by 5 × 10 ^15. Introduce cm- ² . Anneal for impurity diffusion and activation at this time is, for example, 1000 ° C for 10 seconds. Thereafter, the contact portion is opened and metal wiring is performed.

The transistor thus manufactured has a sheet resistance (Ps) of 6.2 kPa / The diffusion length (ie depth of source / drain regions) was 10 nm as a result of SIMS analysis.

However, the parasitic resistance of the conventional transistor is relatively large because the source / drain region is shallow. As a result, an improvement in driving force corresponding to the reduction of the gate length could not be obtained.

[Purpose of invention]

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a MOS semiconductor device having improved driving force.

[Configuration of Invention]

In order to achieve the above object, the semiconductor device of the present invention includes a first conductive semiconductor substrate, a gate electrode formed on the semiconductor substrate via an insulating film, and a channel forming region located directly under the gate electrode of the semiconductor substrate. And a second conductive source / drain region formed on both sides of the film, wherein the thickness of the insulating film is less than 2.5 nm, preferably 2.0 nm or less, and the gate length of the gate electrode is 0.3 m or less.

In addition, the semiconductor device obtains more desirable characteristics when the power supply voltage is used in a circuit of 1.5 V or less.

Furthermore, it is preferable to connect a Schottky diode made of a metal / silicon layer to the gate electrode.

[Action]

According to the present invention configured as described above, by making the thickness of the gate insulating film less than 2.5 nm, the reliability under hot-carrier stress is greatly improved as shown in FIG. Moreover, when it is set to 2 nm or less, it will improve further.

In addition, as shown in FIG. 4, when the channel length is 0.3 占 퐉 or less, the gate current is drastically reduced to have good transistor characteristics.

Therefore, when the gate length of the present invention is 0.3 탆 or less and the gate insulating film thickness is less than 2.5 nm, it is possible to achieve a good transistor operation and a transistor with high hot carrier reliability.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1A shows the structure of a MOS transistor according to the first embodiment of the present invention. In this figure, reference numeral 1 denotes a semiconductor substrate of a first conductivity type (e.g., p-type), and a gate electrode 2 is formed on the substrate 1 via an oxide film 3. On the side of the channel formation region 4 directly below the gate electrode 2 in the substrate 1, the reverse conductivity type (for example, n ⁺ type) is different from the first conductivity type, which is the source region 5 and the drain region 6. A high concentration diffusion layer is formed. The power source 7 is connected to the gate electrode 2 and the power source 8 is connected to the drain region 6, respectively. The gate length Lg, which is a dimension in the longitudinal direction of the channel formation region 4 of the gate electrode 2, is 0.3 µm or less, and the thickness Tox of the gate insulating film 3 is less than 2.5 nm. The transistor having the gate length Lg of the present invention improves the conductance gm and reduces the tunnel current Id2 flowing into the gate among the currents Id1 and Id2 to be introduced into the drain region 6. It becomes.

FIG. 1 (b) shows a typical structural diagram and dimensions of each part of the embodiment of the present invention. The gate length Lg of the gate electrode is 0.09 μm, the gate insulating film thickness Tox is 1.5 nm, the effective channel length Leff between the source and the drain is 0.05 μm, and the diffusion depth (xj) near the channel is the region other than the source and drain. It is shallow compared to 30 nm. In this embodiment, the diffusion layer near the channel is formed by solid phase diffusion from the PSG film formed on the gate side wall, and is a MOS transistor of a so-called Solid Phase Diffused Drain (SPDD) structure.

Here, the manufacturing method of the principal part of the transistor of this invention is demonstrated first.

After forming the element region and the element isolation region on the semiconductor substrate 1 by the conventional method, the gate oxide film is oxidized at 800 ° C. for 10 seconds by the rapid ramp heating method. Thus, the gate insulating film 3 having a film thickness suitable for the above condition of 1.5 nm can be formed. Further, a gate insulating film thickness of 1.8 nm could be formed under conditions of 850 ° C. for 10 seconds. A gate insulating film thickness of 2.0 nm could be formed under conditions of 900 ° C. for 5 seconds. By selecting the temperature and time, a gate insulating film having a desired film thickness of less than 2.5 nm could be formed. Thereafter, about 100 nm of the phosphorus-containing polysilicon film is deposited, and then patterned by anisotropic etching to form a gate electrode having a desired gate length Lg.

After the HF treatment, the source / drain regions 5 and 6 having a 30 nm diffusion length could be formed by solid phase diffusion from the PSG film (phosphorus-containing silicon oxide film). 2 shows the impurity concentration profile at that time. The sheet resistance Ps of the diffusion layer could be set to 1.4 mA / square. On the other hand, it was 6.2 kV / square when the HF treatment was not performed.

The subsequent steps are produced in the same manner as in the conventional example. By the above-described method, the gate length is the smallest, and 0.06 m is realized, and a transistor having a gate length of a desired size can be fabricated up to 10 m or less and 0.06 m. The gate oxide film has a desired film thickness of less than 2.5 nm including 1.5 nm in thickness. In addition, the value of the gate length and the gate insulating film thickness can be confirmed by observation with a transmission microscope: TEM (Trans mission Eloctron Microscope).

The result of having performed the various characteristics evaluation in the MIS type FET formed as mentioned above is demonstrated below.

3 shows the gate oxide film thickness dependence of interconductance degradation under hot carrier stress (Vd = 2.5V, Isubmax condition). As shown in this figure, when the gate oxide film is less than 2.5 nm, the deterioration of the mutual conductance (gm) is 1/2 of the threshold value at which the tunnel current is generated and the deterioration amount at the conventionally known 3 nm, and the lifetime of the transistor is increased. Since it improves 2 times or more, it is preferable to use it below 2.5 nm.

Furthermore, as can be clearly seen from FIG. 4, when used at the film thickness Tox = 2.0 nm or less of the gate oxide film, the lifetime of the transistor is improved by three times or more.

When the thickness of the gate oxide film was Tox = 2.0 nm or less, the amount of deterioration of mutual conductance Δgm / gm = 10% or less at the gate length Lg = 0.10 탆, and Δgm / gm = 6% at the gate length Lg = 0.14 탆. The transistors with less degradation amount can be configured as follows.

On the other hand, when the film thickness Tox of the gate oxide film was 2.5 nm or more, the amount of deterioration of mutual conductance Δgm / gm (%) increased, and a sudden deterioration of the transistor life was found.

4 is a curve diagram illustrating the dependence of the gate length Lg on the tunnel current Ig. In FIG. 4, tunnel current Ig is less than Ig = 0.5 mA at oxide thickness Tox = 1.5 nm and oxide thickness Tox = 1.8 when gate length Lg = 0.3 µm or less (gate width W = 10 µm). At nm, it is found to be stable at less than Ig = 0.1 μs. On the other hand, when gate length Lg exceeds 0.3 micrometer, rapid increase of gate current appears.

5 shows the dependency of the gate length Lg of the drain current IdO. In this figure, in the case of Tox = 1.5 nm and xj = 30 nm (invention), in the case of Tox = 1.8 nm and xj = 30 nm (invention), in the case of Tox = 3.0 nm and xj = 12 nm (conventional example) Are shown respectively. As shown in this figure, it can be seen that the driving force is approximately doubled as compared with the conventional one.

FIG. 6 shows the gate length Lg dependency of the tunnel current Ig, and FIG. 7 shows the gate length Lg dependency of the conductance gm. In the figure, when the gate oxide film thickness Tox = 1.5 nm and the diffusion length xj = 30 nm (invention), Tox = 1.8 nm and the diffusion length xj = 30 nm (invention), Tox = 3.0 nm and the diffusion length xj The case of = 12 nm (prior art) is shown respectively. As is clear from these figures, it can be seen that the transistor of the present invention obtains 1.5 to 2 times better driving force and mutual conductance than conventional transistors having the same gate length. Further, at this time, the gate current is 10 ^-4 or less than the driving force when Lg is 0.3 µm or less (this means that the gate current Ig is four orders of magnitude smaller than the drain current Id), and there are operational problems. None was confirmed.

FIG. 8 shows the gate length Lg dependence of the substrate current Isub, and FIG. 9 shows the gate length Lg dependence of the substrate current impact ionization rate, each of which is an indicator of the reliability of the transistor. Particularly, the substrate current Isub is represented as the Vg-Isub characteristic by using the gate length Lg as a parameter in FIG. 8 (b). Here, in the case of the gate oxide film thickness Tox = 1.5 nm and the diffusion layer length xj = 30 nm (invention), in the case of Tox = 1.8 nm and the diffusion layer length xj = 30 nm (invention: Fig. 8 (b) is not shown). ) And (x) are shown for Tox = 3.0nm and diffusion layer length xj = 12nm, respectively. The transistor of the present invention has a larger substrate current and impact ionization rate than conventional transistors.

FIG. 17 shows the deterioration of the interconductance gm (the deterioration of the interconductance with respect to the stress time). Here, conventional transistors having an oxide film thickness of Tox = 3.0 μm, a diffusion length of xj = 12 nm, a gate length of Lg = 0.10 μm, an oxide film thickness of Tox and a diffusion layer length of xj having the same size, and a gate length of Lg = 0.17 μm. In the transistor of the present invention, the oxide film thickness Tox = 1.5 nm, the diffusion layer length xj = 30 nm, the gate length Lg = 0.99 m, and the oxide film thickness Tox and the diffusion layer length xj are the same size and the gate length Lg. The result of having tested on the thing of 0.14 micrometer is shown. Although the conventional transistor and the transistor of the present invention have almost the same time dependence, the transistor of the present invention has a low value of Δgm / gm and has been found to improve the degradation characteristics of gm.

Figure 16 shows the dependence of the effective field of the carrier mobility, which is also an indicator of the reliability of transistors (Y. Toyoshima, H. lwai, F. Matsuoka, H. Hayashida, K. Maeguchi, and K. Kanzaki, 'Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFETs,' IEEE Trans.Eelectron Device, vol. 37, no. 6, pp. 1496-1503, 1990.) Factors determining 1 / μeff) include surface roughness scattering (1 / sr), phonon scattering (1 / ph), and coulomb scattering (1 / c), and the overall mobility (1 / eff)

ln (1 / μeff) = ln (1 / μc) + (1 / μsr) + (1 / μph))

It is expressed as The broken line in the graph shows the carrier mobility by each factor, and the solid line shows the carrier mobility in which they are combined.

As shown in FIG. 17, it is understood that the transistor (shown in solid line) of the present invention has better reliability under hot carrier stress than the transistor of the prior art (shown in dashed line). It is small. That is, the small amount of deterioration in the deterioration characteristic of gm is a cause for causing a decrease in driving force due to deterioration of mobility due to an increase in interface level Nit caused by hot carrier stress as shown in FIG. The thinner the oxide film thickness (Tox) is lost, and in addition, when the gate oxide film thickness (Tox) is thin, it is mainly dominated by the surface roughness scattering (1 / μsr) because the electric field (Eeff) in the longitudinal direction of the channel is very strong. The influence of the coulomb scattering (1 / μc) by the interface level is that it is difficult to appear in the carrier mobility (1 / μeff).

Therefore, in the case of the thin film gate oxide MOSFET, it can be seen that a transistor having good reliability with less deterioration after stress despite a large substrate current and impact ionization rate.

Figure 10 shows the dependence of the power supply voltage (Vd = Vg) of the current (Ig, Id). Here, the case where oxide film thickness Tox = 1.5 nm, gate length Lg = 0.14 micrometers, and diffusion layer length xj = 30 nm is shown. Further, it can be seen that the transistor of the present invention has an Ig / Id ratio of 1 × 10 ⁻⁴ or less at 2.0 V or less and no problem in operation. In addition, at 1.5 V or less, the above ratio was about 6 x 10 ^-5 or less, whereby a more reliable transistor could be realized.

11 shows the dependency of the gate voltage Vg on the drain current Id. This is measured for a transistor like a transistor having the characteristics shown in FIG. It has been confirmed that the transistor of the present invention obtains a driving force that is 3 to 5 times better than the conventional example even under low voltage.

12 shows the dependency of the drain voltage Vd of Ig / Id. As shown in this figure, a good value of 6 × 10 ⁻⁵ or less was obtained at a drain voltage Vd of 1.5 V or less. On the other hand, when the drain voltage Vd exceeds 1.5 V, it can be seen that the tunnel current Ig suddenly increases and the characteristics deteriorate.

Therefore, when used in a circuit of 1.5V or less, it can be seen that the transistor of the present invention has good characteristics.

Further, when the transistor of the present invention is used in a circuit of 1.2V or less, the gate current (Ig / Id) for the channel current is reduced by about 25 ‰ compared with the case of 1.5V power supply, and the performance is remarkably improved. In FIG. 10, the value of Ig / Id is reduced to 4.5 × 10 ⁻⁵ when the value of Ig / Id drops from 1.2V to 1.2V with respect to about 6 × 10 ⁻⁵ . The value of the gate current Ig is also reduced by about 50%.

However, the value of the mutual conductance, which is the performance of the transistor, is gm = 1,010mS / mm at the power supply voltage VDD as shown in FIG. 21, while gm = 995mS / mm even when the power supply voltage is dropped to 1.2V. When it had, it stayed in the 1.5% fall. Therefore, when used in a circuit of 1.2V or less, the performance is further remarkably improved by the improvement of 25% of Ig / Id compared with the case of 1.5V power supply.

In addition, when the transistor of the present invention is used in a circuit of 0.5V or less, it can be seen that as shown in FIG. 10, the gate leakage current is reduced to 1/20 or less as compared with 1.5V operation. About 80% of gate currents are also reduced. Therefore, when the transistor of the present invention is used in a circuit of 0.5V or less, a high performance transistor is realized with even lower power consumption.

FIG. 13 shows the gate length dependency of the Id-Vd characteristic, and FIG. 14 shows the gate length dependency of the conductance gm. Here, the Id-Vd characteristics and the gm subthreshold characteristics when the gate length Lg is 10 µm (a), 0.14 µm (b) and 0.09 µm (c) are shown, respectively. It can be seen that the remarkable gate leakage current seen in a conventional transistor having a gate length of 10 mu m is suppressed in the fine device of the present invention, and further, a high performance of gm = 1,010 mS / mm is obtained at Lg = 0.09 mu m.

15 shows transistor characteristics at a power supply voltage of 0.5V or less. The power supply voltage at this time is 0.5V. The main characteristics are shown in comparison with those of the present invention and the conventional transistor. [0027] Figures (a) are the transistor characteristics of the present invention, (b) are the conventional transistor characteristics, and the driving force (Id-Vd characteristic) The threshold characteristics (log Id-Vg) and the mutual conductance (gm-Vg) characteristics are shown. As is clear from this figure, in the transistor of the present invention, a large drain current Id flows with a smaller power supply voltage than the conventional one, and a large value of conductance gm is obtained, and the characteristics are improved overall. In the transistor of the present invention, even at a low power supply voltage of 0.5 V, an excellent mutual conductance of 746 mS / mm is obtained.

Fig. 20 shows the power supply voltage dependence of the interconductance of the transistor of the present invention when the gate length is 0.09 mu m and the gate oxide film thickness is 1.5 nm. Even at 0.5 V operation, a very good mutual conductance of 860 mS / mm is obtained.

21 and 22 compare the power supply voltage dependence of the interconductance and current driving force of the transistor of the present invention with that of a conventional transistor having a 0.4 mu m gate length. The gate film thickness of the 0.4 mu m transistor is 9 nm.

Currently, a general-purpose microprocessor operating at 150MHz uses a gate-length MOSFET of about 0.4µm, and the FET has a crossconductance of 200mS / mm under a 3.3V supply. Therefore, if the wiring capacity and the resistance are not reduced, the high speed will not be realized. However, when inferred from the mutual conductance of the device, the MOSFET of high driving force realized at this time is about 1.5V under the low voltage of the 3.3V operation transistor in the current state. There is a possibility of speeding up 5.7 times. Even in the low voltage operation of 0.5V, since it has the mutual conductance of 860mS / mm, compared with the current 3.3V operation, power consumption is about 1/9, and there exists a possibility of speeding up 5 times from the ratio of mutual conductance.

Currently, commercialized LSIs (such as MPU microprocessors) operate at a clock frequency of 200 MHz at a power supply voltage of 3.3V.

The transistor of the present invention has a high current driving force even at a low power supply voltage (for example, 1.5V or 0.5V). Therefore, the low power supply voltage (Note: the power consumption P is proportional to the square of the voltage V) due to the low power supply. Therefore, it is effective to lower the power supply voltage for low power consumption operation. The lowering of the voltage results in a decrease in the current driving force of the transistor, and the lowering of the operating speed of the LSI) further increases the speed of the LSI operation.

The power consumption of the LSI can be expressed by the following equation.

P = KfcV ² _dd + (I _ls + I _lg ) V _dd

Here, P: power consumption, f: clock frequency, c: capacitance, Vdd: power supply voltage, Ils: leakage current determined by sub-threshold characteristics, Ilg: gate leakage current.

In this equation, the first kfcV ² _dd is the power consumed by the accumulation and charge-discharge of the charge, and the second term (I _1s + I _1g ) V _dd is the power consumed by the leakage current component of the transistor. to be.

In addition, the clock frequency f is a value determined by the current driving force I of the transistor.

The charge accumulation time t is

t = Q / I = CV / I, f = I / CV

It can be represented as.

Here, the power consumption per chip is 10 W, the number of chip transistors is 3x10 ⁶ , and the relationship between the power consumption and the clock frequency of the transistor of the present invention and the transistor of the conventional structure is shown.

Here, in the design of the threshold voltage of each transistor, if the definition of the threshold voltage is a voltage at which the drain current Id flows by 1 mA / µm, 0.6V at 3.3V power supply, 0.4V at 1.5V power supply and 1.5V power supply at 2.0V power supply. 0.2V at 0.3V, 1.0V power supply, 0.15V at 0.5V power supply, and 0.1V at 0.3V power supply.

The relationship between the power consumption P and the clock frequency f can be divided into a region determined by the accumulation and erasure of charge and a region determined by the leakage current.

As shown in Fig. 25 (a), the component determined as the sub-threshold characteristic among the leakage currents is the threshold voltage 0.3V at the supply voltage of 1.5V from the respective threshold voltages, and the power consumption by the leakage current is 4.5. mW. Likewise,

30 mW at 1.0 V supply voltage,

45 mW at 0.5 V supply voltage,

100mW at 0.3V Supply Voltage

to be.

On the other hand, in the case of using the tunnel gate oxide film of the present invention (Lg = 0.14µm, Tox = 1.5nm), the leakage current is 6 × 10 ^-8 A / µm at 1.5V power supply, and the gate width of each transistor is 10µm. When the number of transistors is 3 × 10 ⁶ , the power consumption component due to the leakage current is 2.7 W.

In each case, the gate oxide thickness is 1.5nm.

When Lg = 0.14㎛

2.7 W at 1.5 V supply

600 mW at 1.0 V supply voltage,

45 mW at 0.5 V supply voltage,

45 mW at 0.3 V supply voltage,

6.3mW at 0.3V Supply Voltage

When Lg = 0.09㎛

540 mW at 1.5 V supply voltage,

120 mW at 1.0 V supply voltage,

9 mW at 0.5 V supply voltage,

1.3mW at 0.3V Supply Voltage

to be.

On the other hand, as shown in Fig. 25 (a), the power consumption determined by the accumulation and erasing of electric charges is driven based on the 3.3V operation of a transistor of Lg = 0.4 mu m and Tox = 9 nm. Is 0.40 mA / µm.

In the transistor of the present invention, in the transistor of Lg = 0.14 µm and Tox = 1.5 nm, the power consumption is 1.2 times and the clock frequency is 5.7 times at 1.5V power supply. In 0.5V operation, the power consumption is 0.047 times and the clock frequency is 2.1 times.

In the transistor of Lg = 0.09 mu m and Tox = 1.5 nm, the power consumption is 1.8 times and the clock frequency is 8.6 times in 1.5V operation. At 0.5V operation, power consumption is 0.11 times and clock frequency is 4.9 times.

In addition, the above-described gate leakage current component is about one digit smaller than the intrinsic power consumption component consumed by charge accumulation elimination and does not cause a problem.

Therefore, as shown in FIG. 26, in the transistor of the present invention, as compared with the LSI of 200 MHz and 3.3 V operation, the high power operation (about 1000 MHz) of 5 times at the same power consumption in the 1.5 V operation and 1 in the 0.5 V operation is performed. Low power consumption of / 9 enables 5x higher clock operation.

In addition, when operating at 200 MHz, the power supply voltage can be lowered to 0.3 V, thereby reducing the power consumption to 100 mW of 1/100 or less.

In addition, the transistor has a high mutual conductance even at a low voltage, and has a high current driving capability (1,010 mS / mm at 1.5 V, 860 mS / mm at 0.5 V, and conventionally 200 mS / mm at 3.3 V). About twice as high frequency analog operation is possible under low voltage.

For example, although the high frequency analog IC for communication of 1-10 microsecond operation | movement mainly uses transistors, such as a bipolar and GaAs, it becomes possible to replace this by the CMOS of this invention.

In order to achieve high integration and high speed of LSI, miniaturization of MOS transistors has been conventionally performed. Of course, in order to increase the speed, it is important to reduce the wiring capacity, reduce the resistance, and reduce the parasitic capacitance and parasitic resistance of the device, but the miniaturization of the device itself is also a key to high driving power. In order to reduce the power consumption in the future, use of a device under a lower voltage is required, but how to form a transistor of high driving power under a low voltage becomes an important problem.

Ordinarily, for example, the authors (authors GG Shahidi, J. Warnock, A. Acovic, P. Agnello, C. Blair, C. Bucelot, A. Burghartz, E. Crabbe, J. Cressler, P. Coane, J. Comfort) , B. Davarl, S. Fischer, E. Ganin, S. Gittleman, J. Keller, K. Jenkins, D. Klans, K. Kiewtniak, T. Lu, PA McFarland, T. Ning, M. Polcari, S. Subbana, JY Sun, D. Sunderland, AC Warren, C. Wong; Paper Title A HIGH PERFORMANCE 0.15㎛ CMOS; Source Dig. Of Tech.Paper, VLSI Symp.on Tech., Kyoto, pp. 93-94, 1993 As shown in [a], nMOS of 0.05 µm channel length (estimated at 0.10 µm of gate length) is usually less than 480 mS / mm and 0.06 µm channel length (estimated at 0.14 µm of gate length) at 1.8V power supply. The pMOS is only a cross conductance (gm) of 250 mS / mm or less. Therefore, in the transistor of this document [a], the above-described values of 480 mS / mm and 250 mS / mm are obtained as much as possible even with a 1.5 V power supply. Meanwhile, the authors (authors Y. Taur, S. Wind, YJ Mii, Y. Lii, D. Moy, KA Jenkins, CL Chen, PJ Coane, D. Klaus, J. Buchchignano, M. Rosenfield, MGR Thomson, and M Polcari; High Performance 0.1 μm CMOS DEVICE with 1.5V Power Supply; Source IEDM Tech.Dig., Pp. 127-130, 1993 = hereinafter referred to as [c]), 0.09 μm at 1.5V power supply. The nMOS of channel length (estimated at 0.14 μm of gate length) is 620 mS / mm, and the pMOS of 0.11 μm channel length (estimated at 0.19 μm of gate length) is only 290 mS / mm. See also, Authors Y. Mii. S. Rishton, Y. Teur, D. Kern T. Lii, K. Lee, K. Jenkins, D. Quinlan, T. Brown Jr., D. Danner, F. Sewell, and M. Polcari; Paper title High Performance 0.1㎛ nMOSFET's with 10ps / stage Delay (85K) at 1.5V Power Supply; Source Dig. of Tech.Pater, VLSI Symp.on Tech., Kyoto, pp 91-92, 1993 = or less The document [d] shows that a value of 740 mS / mm can be obtained in an nMOS having a channel length of 0.05 m (presumed to be a gate length of 0.100 m) at a power supply voltage of 1.5V. See also, for example, the authors: Y. Mii, S. Wind, Y. Lii, D. Klaus, and J. Bucchignano; Paper Name An Ultra-Low Power 0.1 μm CMOS; Dig. Of Tech. Papers, VLSI Symp. On Tech , Hawaii, pp. 9-10, 1994 hereinafter referred to as [b]), 340 mS / mm, 0.12 μm at nMOS with 0.12 μm channel length (estimated gate length of 0.17 μm) at 0.5 V power supply. The interconductance gm of 140 mS / mm or less is obtained only in the pMOS of the channel length (estimated at 0.2 μm of the gate length). Moreover, as an example of a high performance p-channel MOSFET, the author (authors Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. Chang, D. Buchanan, P. Agnello, Y) Mii, C. Reeves, A. Acovic, and V. Kesan; Paper name High Transconductance 0.1 μm pMOSFET: Source IEDM Tech.Dig., Pp. 901-904, 1992 = hereinafter referred to as [e]) At 1.5 V, 400 mS / mm at a gate oxide thickness of 3.5 nm, effective channel length of 0.08 μm (estimated gate length of 0.15 μm), and 330 mS / mm at an effective channel length of 0.11 μm (gate length of 0.18 μm) have been reported. Therefore, nMOS exceeds 740mS / mm at 1.5V or higher, pMOS exceeds 400mS / mm, nMOS exceeds 540mS / mm at 1.2V or higher, pMOS exceeds 245mS / mm, nMOS exceeds 340mS / mm at 0.5V or higher In order for the pMOS to have a performance exceeding 140 mS / mm, it is necessary to have the configuration of the present invention as the structure of the transistor.

Similarly, for the power supply driving force, as shown in, for example, [b], the nMOS stays at 0.052 mA / µm and the pMOS at 0.032 mA / µm, for example. In the 1.5 V power supply, as shown in the document [c], the nMOS stays at 0.65 mA / µm and the pMOS is 0.51 mA / µm. Therefore, nMOS exceeds 0.65 mA / µm at 1.5 V or higher power supply, pMOS exceeds 0.51 mA / µm, nMOS exceeds 0.47 mA / µm at 1.2 V or higher power supply, pMOS exceeds 0.22 mA / µm and nMOS is higher than 0.5V power supply. In order to obtain a driving force of greater than 0.052 kPa / µm and a pMOS of more than 0.032 kPa / µm, it is necessary to have the structure of the present invention as the structure of the transistor.

The values of the mutual conductance and the current driving force described above are both characteristic values at room temperature.

Therefore, in the nMOS under a certain power supply voltage VDD,

gm ＞ 400 × VDD + 140

In pMOS,

gm> 260 * VDD + 10

The structure which becomes is a characteristic of this invention. The unit is VDD (V), gm (mS / mm).

In addition, as a current driving force

nMOS is Id> 0.598 × VDD-0.247

pMOS is Id> 0.268 × VDD-0.102

The structure which becomes is a characteristic of this invention. The unit is VDD (V) and Id (µs / µm). In addition, these values do not describe the value of a gate length in particular, but they are all about 0.1 micrometer in size.

It is well known that the driving force of the MOSFET shortens the gate length and strengthens the electric field of the channel, so that the method of increasing the speed of electrons or holes is effective in improving the driving force.However, in the method of shortening the gate length and strengthening the channel electric field, When the length is 0.1 µm or less, in principle, a speed saturation (a phenomenon in which the velocity of electrons or holes does not improve due to the saturation of electrons or holes even when the electric field of the channel becomes to some extent strong) is increased. It was saturated.

As a fine gate MOSFET, the world's smallest nMOSFET with a gate length of 0.04 mu m was reported last year, and its room temperature operation was reported. However, the current driving force remained at an improvement of 20 to 30% compared to a transistor having a 0.1 mu m gate length.

Therefore, the above-described values of the mutual conductance and the driving force are difficult to realize by the conventional method, and can be realized by the transistor having the structure of the present invention.

In a conventional MOSFET which does not use the tunneling gate oxide film of the present invention, in a device having an effective channel length (Leff) of 0.5 µm and a gate oxide thickness (Tox) of 3.5 nm in an N-channel MOS, the mutual conductance of 40 mS / The value of mm is obtained (document [d]). The gate length Lg of this transistor can be estimated to be 0.10 mu m. The value of this cross-conductance is the highest performance of the 0.1 mu m gate length MOSFET of the conventional structure. In addition, the transistor having an effective channel length of 0.1 mu m (presumed to have a gate length of 0.15 mu m) has a value of 620 mS / mm of mutual conductance, which is also the highest performance obtained with a 0.15 mu m gate length MOSFET of a conventional structure.

The inversion layer capacity of the MOSFET of the present invention is equivalent to a gate oxide film of about 0.5 nm from the estimation of the surface carrier concentration.

Therefore, in the transistor having the structure of applying the gate oxide film of less than 2.5 nm of the present invention, in the device having a gate length of 0.1 탆, the mutual conductance (gm) is

gm> 740 × (3.5 + 0.5) / (2.5 + 0.5)

990 mS / mm

0.15 μm gate length device

gm> 620 × (3.5 + 0.5) / (2.5 + 0.5)

830 mS / mm

Can be realized. In other words, in order to obtain a mutual conductance of 990 mS / mm at a gate length of 0.1 μm and 830 mS / mm or more at a gate length of 0.15 μm, application of a tunnel gate oxide of less than 2.5 nm, which is a basic element of the present invention, is required.

At the same time, the current driving force is 0.65 kW / µm under the power supply voltage of 1.5 V, which is the conventional highest performance (document [c]). This value is for a device having an effective channel length of Leff = 0.09 mu m (gate length is estimated to be 0.14 mu m). If the device having a gate length of 0.10 mu m is realized in this conventional transistor structure, the current driving force can be estimated to be 0.77 mA / mu m.

Therefore, in a transistor having a structure of less than 2.5 nm of the gate oxide film of the present invention, the current driving force Id is 0.1 μm in a gate length device.

Id> 0.77 × (3.5 + 0.5) / (2.5 + 0.5)

~ 1.0 mA / μm

In devices with 0.15 μm gate length,

Id〉 0.65 × (3.5 + 0.5) / (2.5 + 0.5)

~ 0.87 mA / μm

Can be realized.

On the contrary, in order to obtain a current driving force of 1.0 mA / µm at a gate length of 0.1 µm and 0.87 mA / µm at a gate length of 0.15 µm under a power supply voltage of 1.5 V, application of a tunnel oxide film of less than 2.5 nm, which is a basic element of the present invention, is essential. to be.

As an example of a high-performance p-channel MOSFET, the literature ([e]) shows 400 mS / mm and 0.51 mA / µm at a gate oxide film of 3.5 nm and an effective channel length of 0.08 µm (estimated gate length of 0.15 µm) at a power supply voltage of 1.5 V. 330 mS / mm and 0.44 μs / μm are reported at an effective channel length of 0.11 μm (gate length of 0.18 μm).

As in the case of the n-channel MOSFET, the transistor having the gate oxide film less than 2.5 nm of the present invention has a structure of 533 mS / mm, 0.68 mA / µm at a gate length of 0.15 µm, 440 mS / mm at a gate length of 0.18 µm, and 0.59 μs / µm. High performance can be realized.

In each gate length device, application of a channel oxide film of less than 2.5 nm, which is a basic element of the present invention, is essential in order to obtain performance above the values shown above.

Therefore, the relationship between the power supply voltage Vdd and the mutual conductance gm or the current driving force Id is

nMOS

gm ＞ 530 × Vdd +190

in pMOS

gm ＞ 330 × Vdd + 13

nMOS

Id> 0.80 × Vdd-0.33

in pMOS

Id> 0.36 × Vdd-0.14

(Unit is Vdd (V), gm (mS / mm))

In order to realize a transistor satisfying this requirement, application of a gate oxide film less than 2.5 nm, which is a basic element of the present invention, is indispensable.

As described above, according to the present invention, it is possible to realize a transistor having both better driving force and higher reliability than before.

As mentioned above, although the silicon oxide film was demonstrated using the gate insulating film, this invention has the same effect also when using the insulating film which has the equivalent gate capacitance. Examples of the insulating film include a silicon nitride film (Si ₃ N ₄ ), a silicon nitride oxide film (SiOxNy), a silicon nitride film and a silicon oxide film (SiO ₂ / Si ₃ N _4, Si ₃ N ₄ / SiO ₂ , SiO ₂ / Si _3). N ₄ / SiO ₂ , Si ₃ N ₄ / SiO ₂ / N ₄ ) or tantalum oxide (TaOx), a strontium titanate film (TiSrxOy), a silicon oxide film and a silicon nitride film, and the like. When the gate capacitance of these insulating films is equivalent to less than 2.5 nm of silicon oxide film in terms of silicon oxide film, the effect of the present invention is obtained. For example, the relative dielectric constant (7.9) of the silicon nitride film is about twice that of the silicon oxide film (3.9). When the silicon nitride film is used, the effect of the present invention is obtained when the film thickness is less than 5 nm. In the case of using any of the above-described insulating films, even if the tunnel leakage current flows through the gate insulating film, the same principle as that of forming a transistor with the insulating film thickness through which the tunnel current flows in the silicon oxide film has the same effect. In addition, as long as the insulating film has a gate capacitance equivalent to less than 2.5 nm of the silicon oxide film described above, an insulating film through which a tunnel current does not flow can be used. In this case, power consumption is reduced, and high-performance transistors can be realized with low power consumption.

For example, when 1 million MOSFETs having a gate tunnel leak of 10 ⁻⁸ A per transistor are integrated, power of 10 ㎃ is consumed. On the other hand, when a transistor in which no tunnel current flows is used, the power consumption of 10 mA is suppressed and the performance as an LSI can be improved.

In addition, when the transistor of the present invention is used for a part of a semiconductor device, a high performance and low cost semiconductor device is realized.

18 is a schematic diagram of a semiconductor device using the transistor of the present invention as a part of the semiconductor device. In particular, as shown in Fig. 18B, the transistor of the present invention may be used for a portion of a peripheral circuit requiring driving with a large current. Such a semiconductor device can be manufactured by the following manufacturing method.

After forming a device region and a device isolation region on a semiconductor substrate by a conventional method, a silicon oxide surface of 4 nm is formed by oxidizing a silicon surface in an oxygen atmosphere at 800 ° C., for example, by a oxidizing method. Thereafter, only the transistor formation region of the present invention removes the first silicon oxide film. Thereafter, a second silicon oxide film having a desired film thickness is formed by rapid lamp heating. The following process is produced through the process similar to the formation method of the transistor of this invention mentioned above.

In the semiconductor device thus produced, the high-performance transistor produced in the present invention is formed in a required region of a transistor driven with a large current, and the semiconductor device is excellent as a whole. Conventionally, for example, in a high speed logic device, as shown in FIG. 19, the peripheral circuit portion (I / O portion) is formed of a bipolar transistor, and the internal logic circuit is formed of a CMOS transistor to achieve high speed.

By using the present invention, fabrication can be performed only by a CMOS process, and high-performance devices can be realized at low cost.

In the transistor of the present invention, since the gate insulating film is extremely thin (less than 2.5 nm), in a situation in which an excessive voltage, that is, a voltage exceeding the power supply voltage is applied due to an unexpected gate voltage, noise, or the like during LSI operation, A problem arises in that an insulating film called gate breakage is caused and a good function cannot be performed as a MOSFET.

FIG. 29 shows a structure in which the Schottky diode 11 made of a metal / silicon layer is connected to the gate of the transistor 9 of the present invention as a protection circuit against breakdown. This Schottky diode is lower in breakdown voltage than the transistor 9 of the present invention.

As the Schottky diode 9, either n-type silicon or p-type silicon can be used. As a metal, what has Al, W, Ti, Mo, Ni, V, Co etc. as a main component can be used.

Compared with the structure without the Schottky diode, when the excessive voltage such as noise is applied, the Schottky diode is destroyed to generate an overcurrent, thereby preventing the gate insulating film of the transistor 9 of the present invention from being destroyed. .

That is, a semiconductor device resistant to electrostatic breakdown using the transistor of the present invention can be realized.

In the present invention, in particular, the description has been made using an example of an nMOSFET, but the present structure is similarly applicable to a pMOSFET. In this case, the gate side wall portion may be formed of BSG (B (boron) -containing silicon oxide film), and a shallow p-type source / drain region may be formed. This is described by the authors M. Saito, T. Yoshitomi, H. Hara, M. Ono, Y. Akaska, H. Nii, S. Matsuda, HS Momose, Y. Katsumata, and H. Iwai; Papers P-MOSFETs with Ultra -Shallow Solid-Phase-Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall; reported in IEEE Trans.Eelectron Devices, vol, ED-40, no.12, pp. 2264-2272, December, 1993). .

As described above, the source / drain oxide layer may be produced by the ion implantation method of the normal B (boron) atom, rather than the solid phase oxidation technique from the BSG side wall.

24 is an electrical characteristic of a p-type MOSFET in which a source / drain diffusion layer is formed by ion implantation. At this time, the gate oxide film thickness was 1.5 nm and the gate length was 0.2 탆. The pMOSFET fabricated with the present invention has a current driving force of 0.41 mA / m and a cross conductance of 408 mS / mm at a 1.5 V power supply, and is described in the authors (Y. Taur, S. Wind J. Mii, D. Moy, KA Jenkins, CL). Chen, PJ Coane, D. Klaus, J. Bucchignano, MGR ThomSon, and M. Polcari; paper titled "High Performance 0.1 μm CMOS Device with 1.5V Power Supply; Source IDEM Tech. Dig, pp, 127-130, 1993). The Tr has a high performance significantly exceeding the performance value of about 200 mS / mm of the reported 0.2 µm gate length pMOSFET, and this Tr has a driving force of 0.06 mW / µm and a cross conductance of about 350 mS / mm at a 0.5 V power supply. have.

In the present embodiment, the diffusion layer depth is described using an example of 30 nm, but the temperature and time can be freely selected by appropriately selecting the temperature and time between 700 ° C and 1,100 ° C for annealing conditions for diffusion and activation. .

FIG. 23 shows how the ratio Ig / Id of the gate current Ig to the channel current Id changes in the oxide film thickness Tox and the gate length Lg. The same ratio (Ig / Id) is the same amount of leakage when the gate length is shortened to 1/2 when the film thickness is 1.5 nm in the case of 1.8 nm, which is 20% thick as compared to the oxide film thickness of 1.5 nm. It can be seen that it generates a current.

As shown in Fig. 12, assuming that the gate length Lg and the insulating film thickness Tox having the following characteristics are preferred, with a limit of 6 × 10 ⁻⁵ , which is a point where Ig / Id increases rapidly, The formula is established. When there is a 6 × 10 ^-5 Ig / Id ratio of the limit,

Tox (nm) = logLg (μm) +2.02

It becomes

This equation is derived from the curve shown in FIG. 12 and is shown for the case where the threshold value is Ig / Id = 6.0 × 10 ⁻⁵ .

In fact, the preferable gate length Lg and the insulating film thickness Tox can also be seen from the value below the limit of Ig / Id = 6.0 × 10 ⁻⁵ , which is indicated by the dotted line in FIG. 23.

Therefore, when the insulating film thickness Tox (nm) is allowed, the gate length Lg (µm) is allowed.

Lg≤10 (Tox-2.02)

In order to improve the integration degree of the LSI, the gate current which becomes the power consumption is further reduced, and when applied to 100,000 (1M (mega) bit) memory, the influence on the power consumption as the LSI is about 10 mA. If the gate current of one transistor is allowed, Ig / W = 1 × 10 ⁻⁸ mA / µm, as shown in FIG. 6 (in this FIG. 6, the gate current per gate width W = 10 μm is shown). As shown, the gate current (Ig / W) per gate width of 10 ⁻⁸ mA / µm is represented by the intersection with each dependent curve as indicated by the dotted line in the figure, and each value is Tox = 1.5 nm. Lg = 0.15µm when Lx = 0.30µm when Tox = 1.8nm. That is, based on the results of this experiment, the following formula holds if these are expressed by the formula.

Tox (nm) = logLg (μm) +2.32

Therefore, the value of the gate length Lg (µm) allowed at any insulating film thickness is

Lg≤10 ^(Tox-2.32)

In this case, the performance can be further improved, and the present invention can be applied to an LSI having high integration.

FIG. 27 shows Ig-Vg characteristics of gate insulating films having various thicknesses (Tox) used in conventional tunnel gate oxide MOSFETs. FIG. 27 (a) and (b) show that the horizontal axis (Vg axis) is higher than the former. It is assumed that elongated. Accordingly, the same figure (a) shows characteristics for more types of gate insulating films than the same figure (b). Moreover, the same figure (b) limits the kind of gate insulating film rather than the same figure (a), and shows the characteristic with respect to the limited kind of gate insulating film in detail. This characteristic was measured in a MOS capacitor with a relatively large area (110 µm x 100 µm). When the insulating film of this characteristic is used in a MOSFET, the leakage current is reduced by miniaturization of the gate area as shown in FIG. Known.

FIG. 28 shows the relationship between the gate leakage current and the gate length when the tunnel gate oxide film is applied to the MOSFET. As shown in this figure, it is known that the leakage current decreases with the gate length Lg when used for a MOSFET, but the dependency on Lg is greater than the −1 power of Lg. Therefore, when a circuit is constructed with only a short gate length, an increase in power consumption due to a leak current can be suppressed as compared with a long Lg transistor.

FIG. 30 shows the MOSFET of the present invention as compared to the conventional one, in which a is a MOSFET according to the present invention, and B is a conventional MOSFET. When constructing a circuit having the same performance as that of the gate length MOSFET 13 shown in the diagram (b) and low power consumption, the microgate length MOSFET 12 is properly connected in series as shown in the diagram (a). The circuit having the desired driving force can be realized. This configuration makes it possible to sufficiently suppress the leak current that has been a problem in the conventional structure and to realize a semiconductor device suitable for low power consumption.

[Effects of the Invention]

As described above, according to the present invention, the thickness of the gate insulating film is less than 2.5 nm to improve the reliability under hot carrier stress, and to make the gate length 0.3 m or less, thereby making tunnel current (Ig) from the source / drain electrode to the gate electrode. ), And the transistor characteristics can be improved. In addition, when the power supply voltage is used at 1.5 V or less, a more reliable transistor can be realized.

In the case where a Schottky diode according to an embodiment of the present invention is connected, even if an excessive voltage such as noise is applied to the MOSFET, it is possible to prevent the Schottky diode from being destroyed by breaking the Schottky diode. .

Therefore, according to the present invention, a transistor resistant to electrostatic breakdown can be realized.

Claims (9)

A first conductive semiconductor substrate, a gate electrode formed on the semiconductor substrate via an insulating film, and a second conductive source / drain region formed on both sides of the channel formation region located directly below the gate electrode of the semiconductor substrate. And the mutual conductance (gm) gm> 400 × VDD + 140 in n-type MOS Gm> 260 × VDD + 10 in P-type MOS The unit is VDD (V), gm (mS / mm), Current driving force (Id) In n-type MOS, Id> 0.598 × VDD-0.247 In P-type MOS, Id> 0.268 × VDD-0.102 MOSFET characterized in that. The MOSFET according to claim 1, wherein the voltage applied to the gate electrode and the drain region is set at 1.5V or less. The MOSFET according to claim 2, wherein the voltage applied to the gate electrode and the drain region is set at 0.5V or less. The method of claim 1 wherein the mutual conductance (gm) is In n-type MOS, gm> 530 × VDD + 190 Gm> 350 × VDD + 13 in P-type MOS MOSFET characterized in that. The MOSFET according to claim 1, wherein said MOSFET defined therein is included as part of a semiconductor device. A first conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate via the insulating film, and directly below the gate electrode formed on the semiconductor substrate via the insulating film; The second conductive source / drain regions formed on both sides of the channel forming region, and the current driving force Id is In n-type MOS, Id> 0.598 × VDD-0.247 In p-type MOS, Id> 0.268 × VDD-0.102 At this time, the unit is VDD (V), Id (㎃ / ㎛) MOSFET characterized in that. The method of claim 6, wherein the current driving force (Id) In n-type MOS, Id> 0.80 × VDD-0.33 Id> 0.36 x VDD-0.14 for p-type MOS MOSFET characterized in that. 7. The MOSFET of claim 6, wherein the MOSFET defined therein is included as part of a semiconductor device. The MOSFET according to claim 1, wherein a tunnel current flows through said insulating film during operation of said semiconductor device.