JP2005123647A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve driving force of a MIS type FET.
A first conductivity type semiconductor substrate (1), a gate insulating film (3) formed on the semiconductor substrate, and a gate electrode (on the semiconductor substrate via the gate insulating film). 2) and a second conductivity type source / drain region (5, 6) formed on both sides of the channel formation region (4) located immediately below the gate electrode of the semiconductor substrate, The thickness of the gate insulating film (3) is less than 2.5 nm in terms of oxide film, the gate length of the gate electrode (2) is 0.3 μm or less, and the length (Lg) of the gate electrode in the channel direction The relationship of the gate insulating film equivalent thickness (Tox) is as follows: Lg ≦ 10 ^{(Tox-2.02) In} this case, the unit of Lg is (μm)
The unit of Tox is (nm)
A semiconductor device characterized by satisfying
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and particularly to a fine, high-performance MOS transistor suitable for use under a low power supply voltage.

  With regard to MOS transistors, in particular, with the improvement of MOSFET integration technology, studies on regions with a gate length of 0.5 μm or less are being promoted in various places. In 1974, R.L.Dennard et al. Proposed a so-called scaling law for MOSFET miniaturization. This is a rule that, when the size of a certain component of an element (for example, channel length) is reduced, the other components are also reduced at the same ratio to ensure the operation characteristics as a transistor. Basically, high integration of MOS LSI, which continued from the 1970s to the early 90s, has been realized based on this rule.

  However, further miniaturization has progressed, and limit values called “physical limit values” are approaching even in various components, and reduction beyond those values is becoming difficult. For example, it is generally said that the thickness of the gate insulating film is about 3 to 4 nm, and below this film thickness, the tunneling current between the gate electrode and the source / drain electrode increases, and the transistor operates normally. Is known to be impossible.

  Therefore, a method of fixing the gate insulating film to about 3 nm and considering reduction of other components was proposed by Fiena et al. In 1993 (authors C. Fiegna, H. Iwai, T. Wada, T Saito, E. Sangiorgio, and B. Ricco; Title of paper A new scaling methodology for the 0.1-0.025 um MOSFET, ´Dig.of Tech. Papers, VLSISymp .; Source Technol., Kyoto, pp. 33-34, 1993 .). That method has led to the realization of a 0.04μm gate length transistor by Ono et al. (Authors M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai) ; Paper title Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junction; Source IEDMTech.Dig., Pp.119-122, 1993).

  A transistor having a gate insulating film thickness of 3 nm and a gate length of 0.04 μm is manufactured as follows. First, after forming an element region and an element isolation region on a p-type silicon substrate by a LOCOS (Local Oxidation of Silicon) method, a p-type impurity (for example, B) is formed in the channel formation region so as to obtain a desired threshold voltage. (Boron)).

Thereafter, a 3 nm oxide film is formed as a gate oxide film on the silicon substrate surface by oxidation at 800 ° C. for 10 minutes, for example, in a DryO ₂ atmosphere. Thereafter, for example, polysilicon is deposited to a thickness of 100 nm under conditions containing P (phosphorus), a resist is applied, and the gate electrode is processed to a desired length by patterning. The n-type impurity is introduced into the source / drain formation region by solid phase diffusion of P from the PSG film (P (phosphorus) -containing silicon oxide film) left on the side wall of the gate electrode. After that, for the purpose of making a good connection with the metal wiring portion and reducing the resistance of the diffusion layer in the portion that does not affect the short channel effect of the transistor, an n-type impurity is ion-implanted by, for example, 5 × 10 ¹⁵ cm. ^-2 introduced. At this time, annealing for impurity diffusion and activation is performed under conditions of, for example, 1000 ° C. and 10 seconds. Thereafter, the contact portion is opened and metal wiring is applied.

  The transistor manufactured in this manner has a sheet resistance (ρs) of the source / drain diffusion layer under the gate side wall of 6.2 kΩ / □, and the diffusion length (that is, the depth of the source / drain region) is 10 nm as a result of SIMS analysis. there were.

  However, the conventional transistor has a relatively large parasitic resistance due to the shallow source / drain regions. For this reason, an improvement in driving force corresponding to the reduction in gate length cannot be obtained.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a MOS semiconductor device having improved driving force.

According to the present invention, a semiconductor device includes a first conductivity type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate via the gate insulating film, and the semiconductor 1. In a MOS type semiconductor device having a second conductivity type source / drain region formed on both sides of a channel formation region located immediately below a gate electrode of a substrate, the thickness of the gate insulating film is equivalent to an oxide film. Less than 5 nm, the gate length of the gate electrode is 0.3 μm or less, and the relationship between the length of the gate electrode in the channel direction (Lg) and the equivalent thickness of the gate insulating film (Tox) is as follows: Lg ≦ 10 ^(Tox-2.02) At this time, the unit of Lg is (μm)
The unit of Tox is (nm)
It is a semiconductor device characterized by satisfying the above.

  According to the present invention, the thickness of the gate insulating film is set to be less than 2.5 nm, the gate length is set to 0.3 μm or less, and the length in the channel direction of the gate electrode and the equivalent thickness of the gate insulating film are defined as follows. As a result, the reliability under hot carrier stress is improved, the tunnel current Ig from the source / drain electrode to the gate electrode can be reduced, and the transistor characteristics can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows the structure of a MOS transistor according to an embodiment of the present invention. In this figure, 1 is a semiconductor substrate of a first conductivity type (for example, p-type), and a gate electrode 2 is formed on the substrate 1 with an oxide film 3 interposed. On each side of the channel forming region 4 immediately below the gate electrode 2 in the substrate 1, a high concentration diffusion layer having a conductivity type opposite to the first conductivity type (for example, n + type) to be the source region 5 and the drain region 6 is formed. . A power source 7 is connected to the gate electrode 2 and a power source 8 is connected to the drain region 6 for use. The gate length Lg, which is the dimension in the length direction of the channel formation region 4 of the gate electrode 2, is 0.3 μm or less, and the thickness Tox of the gate insulating film 3 is less than 2.5 nm. The transistor having the gate length Lg of the present invention is intended to improve the conductance gm and reduce the tunnel current Id2 flowing into the gate out of the currents Id1 and Id2 that should flow into the drain region 6.

  FIG. 1B shows a typical structural diagram of the embodiment of the present invention and dimensions of each part. The gate length (Lg) of the gate electrode is 0.09 μm, the gate insulating film thickness (Tox) is 1.5 nm, the effective channel length (Leff) between the source and drain is 0.05 μm, and the diffusion depth (Xj) near the channel Is shallower than other regions of the source and drain and is 30 nm. In this embodiment, the diffusion layer in the vicinity of the channel is formed by solid phase diffusion from a PSG film formed on the gate sidewall, and is a MOS transistor having a so-called SPDD (Solid Phase Diffused Drain) structure.

Here, the manufacturing method of the main part of the transistor of the present invention will be described first.
The gate oxide film is formed by forming a device region and a device isolation region on the semiconductor substrate 1 by a conventional method, and then oxidizing it at 800 ° C. for 10 seconds by a rapid lamp heating method. As a result, the gate insulating film 3 having a thickness suitable for the above condition of 1.5 nm could be formed. In addition, a gate insulating film of 1.8 nm could be formed under conditions of 850 ° C. and 10 seconds. A gate insulating film having a thickness of 2.0 nm was formed at 900 ° C. for 5 seconds. By selecting the temperature and time, a gate insulating film having a desired film thickness of less than 2.5 nm could be formed. Thereafter, a phosphorus-containing polysilicon film is deposited to about 100 nm and then patterned by anisotropic etching to form a gate electrode having a desired gate length Lg.

  After the HF treatment, source / drain regions 5 and 6 having a diffusion length of 30 nm could be formed by solid phase diffusion from the PSG film (phosphorus-containing silicon oxide film). FIG. 2 shows the impurity concentration profile at that time. The sheet resistance ρs of such a diffusion layer could be 1.4 kΩ / □. In addition, it was 6.2 kΩ / □ when HF treatment was not performed.

  Subsequent steps are produced by the same method as in the conventional example. With the above-described method, the minimum gate length is 0.06 μm, and a transistor having a desired gate length of 10 μm or less to 0.06 μm can be manufactured. In addition, a gate oxide film having a desired film thickness of less than 2.5 nm was realized, including a thickness of 1.5 nm. The values of the gate length and the gate insulating film thickness can be confirmed by observation with a transmission electron microscope (TEM).

  The results of various characteristic evaluations of the MIS type FET formed as described above will be described below.

  FIG. 3 shows the gate oxide film thickness dependence of transconductance degradation under hot carrier stress (Vd = 2.5 V, Isubmax condition). As shown in this figure, when the gate oxide film thickness is less than 2.5 mm, the deterioration of the mutual conductance gm is ½ of the limit value in the case of 3 nm, which is conventionally called the limit value at which the tunnel current is generated. Therefore, it is desirable to use less than 2.5 nm because the lifetime of the transistor is improved by more than twice.

  Furthermore, if it is used at 2.0 nm or less, the lifetime of the transistor is improved by 3 times or more. Therefore, it is more desirable if used at 2.0 nm. When the thickness Tox of the gate oxide film 3 is 2 nm or less, the gate length Lg is 10% or less when the gate length Lg is 0.10 μm, and the gate length Lg is 0.14 μmm or less when the thickness is 6% or less. Deterioration was observed.

  FIG. 4 shows the dependency of the tunnel current Ig on the gate length Lg. In this figure, when the gate length Lg is 0.3 μm or less, the gate width W = 10 μm, the oxide film thickness Tox = 1.5 nm is less than 0.5 μA, and the oxide film thickness Tox = 1.8 nm is stable to less than 0.1. . On the other hand, when the gate length Lg exceeds 0.3 μm, a rapid increase in gate current was observed.

  FIG. 5 shows the dependency of the drain current Id0 on the gate length Lg. In this figure, when Tox = 1.5 nm and xj = 30 nm (invention), Tox = 1.8 nm and xj = 30 nm (invention), Tox = 3.0 nm and xj = 12 nm (conventional) Each example). As shown in this figure, it can be seen that the driving force is improved about twice as compared with the conventional one.

FIG. 6 shows the dependence of the tunnel current Ig on the gate length Lg, and FIG. 7 shows the dependence of the conductance gm on the gate length Lg. In these figures, the gate oxide film thickness Tox = 1.5 nm and the diffusion length xj = 30 nm (invention), Tox = 1.8 nm and the diffusion length xj = 30 nm (invention), Tox = 3. The case of 0 nm and the diffusion length xj = 12 nm (prior art) is shown respectively. As can be seen from these figures, the transistor of the present invention has 1.5 to 2 times better driving force and transconductance than the conventional transistor having the same gate length. Furthermore, the gate current at this time was 10 ⁴ or less (4 digits smaller) than the driving force when Lg was 0.3 μm or less, and it was confirmed that there was no problem in operation.

  FIG. 8 shows the dependency of the substrate current Isub on the gate length Lg, and FIG. 9 shows the dependency of the substrate current impact ionization rate on the gate length Lg. Each of these is an index for the reliability of the transistor. In particular, the substrate current Isub is expressed as a Vg-Isub characteristic with the gate length Lg as a parameter in FIG. 8B. Here, when the gate oxide film thickness Tox = 1.5 nm and the diffusion length xj = 30 nm (invention), Tox = 1.8 nm and the diffusion length xj = 30 nm (invention), Tox = 3.0 nm, diffusion The case of the length xj = 12 nm (conventional) is shown. The transistor of the present invention has a larger substrate current and impact ionization rate than conventional transistors.

  FIG. 17 shows the deterioration of transconductance gm (transconductance deterioration with respect to stress time). Here, as a conventional transistor, the oxide film thickness Tox = 3.0 nm, the diffusion length xj = 12 nm, the gate length Lg = 0.10 μm, the oxide film thickness Tox and the diffusion length xj are the same size, and the gate length Lg = A transistor of 0.17 μm is used, and the transistor of the present invention includes an oxide film thickness Tox = 1.5 nm, a diffusion length xj = 30 nm, a gate length Lg = 0.09 μm, an oxide film thickness Tox and a diffusion length. xj represents the result of a test conducted with the same size and gate length Lg = 0.14 .mu.m. The conventional transistor and the transistor of the present invention have approximately the same time dependency, but the transistor of the present invention has a low value of Δgm / gm itself, and it has been confirmed that the deterioration characteristics of gm are improved.

FIG. 16 shows the effective electric field dependence of carrier mobility, which is also an indicator of transistor reliability. Y.Toyoshima, H.Iwai, F.Matusoka, H.Hayashida, K, Maeguchi, and K.Kanzaki, ´Analysis on gate-oxidethickness dependence of hot-carrior-induceddegradation in thin-gate oxide nMOSFETs, ´IEEETrans.Electron Devices , vol.37, No.6, pp.1496-1503, 1990. The factors determining carrier mobility (1 / μeff) include surface roughness scattering (1 / μsr), phonon scattering (1 / μph), There is Coulomb scattering (1 / μc), and the overall mobility (1 / μeff) is
ln (1 / μeff) = ln ((1 / μc) + (1 / μsr) + (1 / μph))
It is represented by The broken line in the graph indicates the carrier mobility due to each factor, and the solid line indicates the total carrier mobility.

  As shown in FIG. 12, the transistor of the present invention is superior in hot carrier reliability to the transistor of the present invention in FIG. 17, that is, the deterioration amount (Δgm / gm) is small. This is because the increase in the interface state caused by the hot carrier stress causes the lowering of the driving force due to the deterioration of mobility, which becomes less visible as the gate oxide film thickness becomes thinner. When the oxide film is thin, the electric field in the longitudinal direction of the channel is very strong, so mobility is mainly governed by surface roughness scattering, and the effect of Coulomb scattering due to interface states is less likely to appear in mobility.

  Therefore, it can be seen that the thin-film gate oxide film MOSFET is a transistor having good reliability with little deterioration after stress despite the large substrate current and impact ionization rate.

FIG. 10 shows the dependency of the currents Ig and Id on the power supply voltage Vd = Vg. Here, the case where the oxide film thickness Tox = 1.5 nm, the gate length Lg = 0.14 μm, and the diffusion length xj = 30 nm is shown. It can be seen that the transistor of the present invention has an Ig / Id ratio of 1 × 10 ⁻⁴ or less at 2.0 V or less, which is not problematic in operation. At 1.5 V or less, the above ratio was about 6 × 10 ⁻⁵ or less, and a highly reliable transistor could be realized.

  FIG. 11 shows the dependency of the drain current Id on the gate voltage Vg. This is measured for the same transistor as the transistor having the characteristics shown in FIG. It was confirmed that the transistor of the present invention was 3 to 5 times better in driving force than conventional reports even under low voltage.

FIG. 12 shows the dependence of Ig / Id on the drain voltage Vd. As shown in this figure, a good value of 6.0 × 10 ⁻⁵ or less was obtained when the drain voltage Vd was 1.5 V or less. On the other hand, when the drain voltage Vd exceeds 1.5 V, the tunnel current Ig increases abruptly and the characteristics are deteriorated.

  Therefore, it can be seen that the transistor of the present invention has good characteristics when used in a circuit of 1.5 V or less.

Further, when the transistor of the present invention is used in a circuit of 1.2 V or less, the gate current Ig / Id with respect to the channel current is reduced by about 25% compared with the 1.5 V power supply, and the performance is remarkably improved. In FIG. 10, the value of Ig / Id is 1.5 V and is reduced to 4.5 × 10 ⁻⁵ if it is lowered to 1.2 V with respect to about 6 × 10 ⁻⁵ . The value of the gate current Ig was also reduced by about 50%.

  However, the value of transconductance, which is the performance of the transistor, has a value of 995 ms / mm even when the voltage is lowered to 1.2 V, as compared to 1.5 V 1.010 ms / mm as shown in FIG. % Decline. Therefore, when used in a circuit of 1.2V or less, the performance is further improved by improving Ig / Id by 25% compared with the case of 1.5V power supply.

  Further, it can be seen that when the transistor of the present invention is used in a circuit of 0.5 V or less, the gate leakage current is reduced to 1/20 or less as compared with the 1.5 V operation as shown in FIG. Further, the gate current with respect to the channel current is also reduced by about 80%. Therefore, if the transistor of the present invention is used in a circuit of 0.5 V or less, a further high performance transistor with lower power consumption can be realized.

  FIG. 13 shows the gate length dependence of the Id-Vd characteristics, and FIG. 14 shows the gate length dependence of the conductance gm. Here, Id-Vd characteristics and gm subthreshold characteristics when the gate length Lg is 10 μm (a), 0.14 μm (b), and 0.09 μm (c) are shown, respectively. It can be seen that the significant gate leakage current observed in the conventional transistor having a gate length of 10 μm is suppressed in the fine device of the present invention, and that Lg = 0.09 μm and high performance of gm = 1010 mS / mm are obtained. .

  FIG. 15 shows transistor characteristics at a power supply voltage of 0.5 V or less. The power supply voltage at this time is 0.5V. The main characteristics are shown in comparison with the characteristics of the present invention and the conventional transistor. (A) is the transistor characteristic of the present invention, and (b) is the conventional transistor characteristic. For each, the driving force (Id -Vd characteristic, subthreshold characteristic, (log Id -Vg), transconductance (gm) As can be seen from the figure, the transistor of the present invention has a large drain current Id flowing at a lower power supply voltage than that of the conventional transistor, and a large conductance gm is obtained. The transistor of the present invention has an excellent transconductance of 746 mS / mm even at a power supply voltage as low as 0.5 V.

  FIG. 20 shows the power supply voltage dependence of the mutual conductance of the transistor of the present invention when the gate length is 0.09 μm and the gate oxide film thickness is 1.5 nm. A very excellent transconductance of 860 ms / mm is obtained even at 0.5 V operation.

  21 and 22 compare the power supply voltage dependence of the mutual conductance and current driving power of the transistor of the present invention with a conventional transistor having a gate length of 0.4 μm. The gate film thickness of the 0.4 μm transistor is 9 nm.

  Currently, a general-purpose microprocessor operating at 150 MHz uses a MOSFET having a gate length of about 0.4 μm. This FET has a transconductance of about 200 mS / mm under a 3.3 V power supply. Therefore, if the wiring capacitance and resistance are not reduced, the speed cannot be increased naturally. However, by analogy with the transconductance of the element, the MOSFET with the high driving power realized this time is compared with the current 3.3 V operation transistor. Therefore, it has a possibility of speeding up about 5.7 times under a low voltage of 1.5. Even at low voltage operation of 0.5V, it has a transconductance of 860mS / mm, so the power consumption is about 1/9 compared to the current 3.3V operation, and the transconductance ratio is 5 times faster. There is a possibility.

  Currently commercialized LSIs (for example, MPU microprocessors) operate at a clock frequency of 200 MHz with a power supply voltage of 3.3V.

  The transistor of the present invention has a high current driving capability even at a low power supply voltage (for example, 1.5 V or 0.5 V). Therefore, lowering the power supply voltage by lowering the power supply voltage (Note: power consumption (P) is proportional to the square of the voltage (V), so it is effective to lower the power supply voltage for low power consumption operation. However, in general, a decrease in voltage causes a decrease in the current driving capability of the transistor, leading to a decrease in the operation speed of the LSI. Further speeding up of the LSI operation is possible.

The power consumption of LSI can be expressed by the following equation.
P = kfcV _dd ² + (I _ls + I _lg ) V _dd
Where P: Power consumption
f: Clock frequency
c: Capacity
V _dd : Power supply voltage
I _ls : Leakage current with sub-threshold characteristics
I _lg : gate leakage current In this equation, the first term kfcV _dd ² is the power consumed by charge-discharge and the second term (I _ls + I _lg ) is the transistor leakage This is the power consumed by the current component.
The clock frequency f is a value determined by the current driving force I of the transistor.

The charge accumulation time t is
t = Q / I = CV / I and f = I / CV
Can be shown.

Here, the power consumption per chip is 10 W, the number of chip transistors is 3 × 10 ⁶ , and the relationship between the power consumption and clock frequency of the transistor of the present invention and the conventional transistor is shown (FIG. 25).

  Here, the threshold voltage of each transistor is designed to be 0.6V with a 3.3V power supply, 0.4V with a 2.0V power supply, 0.3V with a 1.5V power supply, and 1.0V with a threshold voltage of 1 μA / μm. The power supply was 0.2V, the 0.5V power supply was 0.15V, and the 0.3V power supply was 0.1V.

  The relationship between power consumption (P) and clock frequency (f) can be divided into a region determined by charge accumulation and erasure and a region determined by leakage current.

As shown in FIG. 25 (b), the component determined by the subthreshold characteristics in the leakage current is the threshold voltage of 0.3V at the power supply voltage of 1.5V from the respective threshold voltages. The power consumption due to leakage current is 4.5 mW. Similarly,
30mW at 1.0V supply voltage,
45mW at 0.5V supply voltage,
100mW at 0.3V power supply voltage
It is.

On the other hand, when the tunnel gate oxide film of the present invention is used (Lg = 0.14 μm, Tox = 1.5 nm), the leakage current is 6 × 10 ⁻⁸ A / μm with a 1.5 V power supply, When the per-transistor gate width is 10 μm and the number of transistors is 3 × 10 ⁶ , the power consumption component due to the leakage current is 2.7 W.

To summarize each case, when the gate oxide film thickness is 1.5 nm and Lg = 0.14 μm,
2.7W at 1.5V power supply voltage
600mW at 1.0V supply voltage,
45mW at 0.5V supply voltage,
6.3mW at 0.3V power supply voltage
When Lg = 0.09 μm,
540mW at 1.5V supply voltage,
120mW at 1.0V supply voltage,
9mW at 0.5V power supply voltage,
1.3 mW at 0.3 V power supply voltage
It is.

  On the other hand, as shown in FIG. 25 (a), the power consumption determined by charge accumulation and erasure is based on the 3.3V operation of a normal transistor with Lg = 0.4 μm and Tox = 9 nm. 0.40 mA / μm.

  In the transistor of the present invention, when Lg = 0.14 μm and Tox = 1.5 nm, the power consumption is 1.2 times and the clock frequency is 5.7 times with a 1.5 V power supply. In 0.5V operation, the power consumption is 0.047 times and the clock frequency is 2.1 times.

  In addition, in a transistor with Lg = 0.09 μm and Tox = 1.5 nm, the power consumption is 1.8 times and the clock frequency is 8.6 times in 1.5V operation. With 0.5V operation, the power consumption is 0.11 times and the clock frequency is 4.9 times.

  Further, the above-described gate leakage current component is about one order of magnitude smaller than the essential power consumption component consumed by charge accumulation and erasure, and does not cause a problem.

  Therefore, as shown in FIG. 26, in comparison with an LSI operating at 200 MHz and 3.3 V, the transistor of the present invention has 1.3 times operation, the same power consumption, 5 times higher frequency operation (about 1000 MHz), and 0.5 V operation. 5 times higher clock operation is possible with 1/9 lower power consumption.

  Moreover, if it operates at 200 MHz, the power supply voltage can be lowered to 0.3 V, and the power consumption can be reduced to 1/100, 100 mW or less.

  In addition, this transistor has a high transconductance even under a low voltage and has a high current driving capability (1,010 mS / mm at 1.5 V, 860 mS / mm at 0.5 V, and conventionally, 200 mS / mm at 3.3 V). mm), high-frequency analog operation that is about 5 times the current is possible under low voltage.

  For example, high-frequency analog ICs for communication operating at 1 to several tens of GHz mainly use transistors such as bipolar and GaAs, but this can be replaced with the CMOS of the present invention.

  In order to achieve high integration and high speed of LSI, miniaturization of MOS transistors has been conventionally performed. Of course, in order to increase the speed, it is important to reduce the capacitance and resistance of the wiring, and to reduce the parasitic capacitance and resistance of the element, but miniaturization of the element itself is a key to increase the driving force. . In the future, in order to reduce power consumption, it is required to use devices under a lower voltage, but how to form a transistor with a high driving force under a low voltage is an important issue.

  Further, usually, for example, literature (authors GG Shahidi, J. Warnock, A. Acovic, P. Agnello, C. Blair, C. Bucelot, A. Burghartz, E. Crasbe, J. Cressler, P. Coane , J. Comfort, B. Davarl, S. Fischer, E. Ganin, S. Gittleman, J. Keller, K. Jenkins, D. Klans, K. Kiewtniak, T. Lu, PAMcFarland, T. Ning, M. Polcari, S. Subbana, JYSun, D. Sunderland, AC Warren, C. Wong; Title A HIGH PERFORMANCE 0.15 μm CMOS; Source: Dig. Of Tech. Papers, VLSI Symp. On Tech., Kyoto, PP.93- 94,1993 = hereinafter referred to as the document [a]), with a 1.8V power supply, an nMOS with a 0.05 μm channel length (estimated to have a gate length of 0.10 μm) is 480 mS / mm or less, 0.06 μm A pMOS with a channel length (estimated to have a gate length of 0.14 μm) only has a transconductance gm of 250 mS / mm or less. Therefore, in the transistor of this document [a], the above-mentioned values of 480 mS / mm and 250 mS / mm can be obtained even at 1.5V power source. Meanwhile, the literature (authors Y. Taur, S. Wind, YJMii, Y. Lii, D. Moy, KAJenkins, CLChen, PJCoane, D. Klaus, J. Bucchignano, M. Rosenfield, MGRThomson, and M .Polcari ； Paper title High Performance 0.1μm CMOS Device with 1.5V Power Supply; Source IEDM Tech.Dig., Pp.127-130,1993 = Hereinafter referred to as document [C]) The nMOS having a channel length of 09 μm (estimated to be 0.14 μm) has a value of only 620 mS / mm, and the pMOS having a channel length of 0.11 μm (estimated to be 0.19 μm) is only 290 mS / mm. The literature (authors Y. Mii. S. Rishton, Y. Teur, D. Kern, T. Lii, K. Lee, K. Jenkins, D. Quinlan, T. Brown Jr., D. Danner, F. Sewell , and M.Polcari ； Title of High Performance 0.1μm nMOSFET´s with 10ps / stage Delay (85K) at 1.5V Power Supply ； Source Dig. of Tech.Pater, VLSI Symp. on Tech., Kyoto, pp91-92, [1993] Document [D]) shows that a value of 740 mS / mm is obtained with an nMOS of 0.05 μm channel length (estimated to have a gate length of 0.10 μm) at a power supply voltage of 1.5 V. Also, for example, literature (authors Y. Mii, S. Wind, Y. Lii, D. Klaus, and J. Bucchignano; paper title An Ultra-Low Power 0.1 μm CMOS; source Dig. Of Tech. Papers, VLSI Symp. on Tech., Hawaii, pp. 9-10, 1994 = Hereinafter referred to as the document [B]), an nMOS having a channel length of 0.12 μm (estimated to have a gate length of 0.17 μm) with a 0.5 V power supply Thus, a pMOS having a channel length of 340 mS / mm and a channel length of 0.12 μm (estimated to have a gate length of 0.2 μm) only has a transconductance gm of 140 mS / mm or less. Examples of high-performance p-channel MOSFETs include literature (authors Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. Chang, D. Buchanan, P. Agnello, Y. Mii, C. Reeves, A. Acovic, and V. Kesan; Title High Transconductance 0.1 μm pMOSFET: Source IEDM Tech. Dig., Pp. 901-904, 1992 = Document [E]) When the power supply voltage is 1.5 V, the gate oxide film thickness is 3.5 nm, the effective channel length is 0.08 μm (the gate length is estimated to be 0.15 μm), 400 mS / mm, and the effective channel length is 0.11 μm (the gate length is 0.18 μm). 330 mS / mm has been reported. Therefore, with a power supply of 1.5 V or higher, nMOS is 740 mS / mm or higher, pMOS is 400 mS / mm or higher, 1.2 V or higher, nMOS is 540 mS / mm or higher, pMOS is 245 mS / mm or higher, and 0.5 V or higher. In order for the nMOS to have a performance of 340 mS / mm or more and the pMOS to have a performance of 140 mS / mm or more, it is necessary to have the structure of the present invention as a transistor structure.

  Similarly, as shown in the document [B], for example, the current drivability is normally 0.052 mA / μm for the nMOS and 0.032 mA / μm for the pMOS with a 0.5 V power supply. On the other hand, with the 1.5V power supply, as shown in the document [C], the nMOS remains 0.65 mA / μm and the pMOS remains 0.51 mA / μm. Therefore, nMOS is 0.65 mA / μm or more with a power supply of 1.5 V or more, pMOS is 0.51 mA / μm or more, nMOS is 0.47 mA / μm or more with a power supply of 1.2 V or more, and pMOS is 0.22 mA / μm. As described above, in order to obtain a driving force of nMOS of 0.052 mA / μm or more and pMOS of 0.032 mA / μm or more with a power supply of 0.5 V or more, it is necessary to have the structure of the present invention as a transistor structure.

  The values of mutual conductance and current driving force described above are characteristic values at room temperature.

Therefore, in an nMOS under a certain power supply voltage (VDD),
gm> 400 VDD + 140
In pMOS, gm> 260V DD +10
This structure is a feature of the present invention. The unit is VDD (V), gm (mS / mm).

In addition, as the current driving force, nMOS is Id> 0.598V DD -0.247
pMOS Id> 0.268V DD -0.102
This structure is a feature of the present invention. The unit is VDD (V), Id (mA).

  Further, although these values do not particularly describe the gate length value, they are all in the vicinity of 0.1 μm.

  It is well known that MOSFET driving force shortens the gate length and increases the electric field of the channel to increase the speed of electrons and holes, which is effective for improving the driving force. In the method of shortening and increasing the channel electric field, the gate length is 0.1 μm or less, and in principle, speed saturation (when the electric field of the channel is increased to some extent, the electric field is further increased). The phenomenon in which the speed of electrons and holes is saturated and does not improve.

  Last year, the world's smallest nMOSFET with a gate length of 0.04 μm was fabricated as a fine gate MOSFET, and its room temperature operation was reported, but its current driving capability was 2 to 3 compared to a 0.1 μm gate length transistor. However, it was only an improvement.

  Therefore, the above-described values of mutual conductance and driving force are difficult to realize by the conventional method, and can be realized by the transistor having the configuration of the present invention.

  In a normal MOSFET not using a tunneling gate oxide film of the present invention, an N channel MOS is a device having an effective channel length (Leff) of 0.05 μm and a gate oxide film thickness (Tox) of 3.5 nm, and a 1.5 V power supply voltage. Below, a value of mutual conductance of 740 mS / mm is obtained (reference [D]). The gate length (Lg) of this transistor can be estimated to be 0.10 μm. This transconductance value is the highest performance of a conventional 0.1 μm gate length MOSFET. The transistor having the effective channel length of 0.1 μm (estimated to have a gate length of 0.15 μm) having the above-described conventional structure has a mutual conductance of 620 mS / mm, which is also obtained by the 0.15 μm gate length MOSFET having the conventional structure. It was the highest performance possible.

  The inversion layer capacitance of the MOSFET of the present invention is equivalent to a gate oxide film of about 0.5 nm from the estimation of the surface carrier concentration.

Therefore, in the transistor having the gate oxide film of less than 2.5 nm according to the present invention, the transconductance gm of the device having a gate length of 0.1 μm is
In devices with gm> 740 × (3.5 + 0.5) / (2.5 + 0.5) to 990 mS / mm 0.15 μm gate length,
gm> 620 × (3.5 + 0.5) / (2.5 + 0.5) to 830 mS / mm can be realized. In other words, in order to obtain a transconductance of 830 mS / mm or more with a 0.15 μm gate length with a 0.1 μm gate length, application of a tunnel gate oxide film of less than 2.5 nm, which is a basic element of the present invention, is required. is necessary.

  At the same time, the current driving force is 0.65 mA / μm under the 1.5 V power supply voltage, which is the highest performance of the prior art (reference [c]). This value is a value for a device having an effective channel length Leff = 0.09 μm (the gate length is estimated to be 0.15 μm). Further, when a device having a gate length of 0.10 μm is realized with this conventional transistor structure, the current driving force can be estimated to be 0.77 mA / μm.

Therefore, in the transistor of the present invention to which the gate oxide film of less than 2.5 nm is applied, the current driving force Id is 0.1 μm gate length device and Id> 0.77 × (3.5 + 0.5) / ( 2.5 + 0.5)
~ 1.0mA / mm
A device with a gate length of 0.15 μm,
Id> 0.65 × (3.5 + 0.5) / (2.5 + 0.5)
~ 0.87mA / mm
Can be realized.

  Conversely, in order to obtain a current driving force of 1.0 mA / mm at a gate length of 0.1 μm and 0.87 mA / mm at a gate length of 0.15 μm under a 1.5 V power supply voltage, it is a basic element of the present invention. Application of a tunnel oxide film of less than 5 nm is essential.

  As an example of a high-performance p-channel MOSFET, in the literature ([E]), when the power supply voltage is 1.5 V, the gate oxide film is 3.5 nm, the effective channel length is 0.08 μm (the gate length is estimated to be 0.15 μm). ) 400 mS / mm, 0.51 mA / μm, effective channel length 0.11 μm (gate length 0.18 μm), 330 mS / mm, 0.44 mA / μm are reported.

  Similarly to the case of the n-channel MOSFET, in the transistor having the gate oxide film of less than 2.5 nm according to the present invention, the gate length is 0.15 μm, the gate length is 533 mS / mm, 0.68 mA / μm, and 0.18 μm. Long, high performance of 440 mS / mm and 0.59 mA / μm can be realized.

  In each gate length device, in order to obtain the performance exceeding the above-mentioned value, it is essential to apply a tunnel oxide film of less than 2.5 nm, which is a basic element of the present invention.

Therefore, the relationship between the power supply voltage Vdd and the mutual conductance gm or the current driving force Id is
NMOS with gm> 530 × Vdd + 190
PMOS with gm> 350 × Vdd + 13
NMOS with Id> 0.80 × Vdd−0.33
With PMOS Id> 0.36 × Vdd−0.14
(Unit is Vdd (V), gm (mS / mm))
In order to realize a transistor that satisfies the above conditions, it is essential to apply a gate oxide film of less than 2.5 nm, which is a basic element of the present invention.

  As described above, according to the present invention, a transistor having better driving power and higher reliability than the conventional one can be realized.

  In the above description, the silicon oxide film is used as the gate insulating film. However, the present invention has the same effect even when an insulating film having the same gate capacitance is used. As the insulating film, for example, a silicon nitride film (Si3 N4), a silicon nitride oxide film (SiOx Ny), a laminated film of a silicon nitride film and a silicon oxide film (SiO2 / Si3 N4, Si3 N4 / SiO2, SiO2 / Si3 N4 / SiO2) , Si3 N4 / SiO2 / N4) or tantalum oxide (TaOx), strontium titanate film (TiSrxOy), a silicon oxide film, a silicon nitride film, or the like. If the gate capacitance of these insulating films is equivalent to a silicon oxide film thickness of less than 2.5 nm in terms of silicon oxide film, the effect of the present invention can be obtained. For example, in FIG. 27, the relative dielectric constant 7.9 of the silicon nitride film is about twice that of the silicon oxide film 3.9, and when the silicon nitride film is used, the effect of the present invention is obtained when the film thickness is less than 5 nm. It is done. In the case of using any of the insulating films described above, even if a tunnel leakage current flows in the gate insulating film, it is consistent with the gist that the transistor is configured with an insulating film thickness in which the tunnel current flows in the silicon oxide film. Has the same effect. In addition, an insulating film that does not flow a tunnel current can be used as long as the insulating film has a gate capacitance equivalent to that of the silicon oxide film less than 2.5 nm. In this case, power consumption is reduced, and a low-power consumption and high-performance transistor can be realized.

For example, when 1 million MOSFETs having a gate tunnel leakage of 10 ⁻⁸ A are integrated per transistor, 10 mA of power is consumed. On the other hand, when a transistor that does not flow a tunnel current is used, the power consumption of 10 mA can be suppressed, and the performance as an LSI can be improved.

  Further, when the transistor of the present invention is used for a part of a semiconductor device, a high-performance and inexpensive semiconductor device is realized.

  FIG. 18 is a schematic view of a semiconductor device using the transistor of the present invention as part of the semiconductor device. In particular, the transistor of the present invention is preferably used in a peripheral circuit portion that is required to be driven with a large current as shown in FIG. Such a semiconductor device can be manufactured by the following manufacturing method.

  After forming an element region and an element isolation region on a semiconductor substrate by a conventional method, the silicon surface is oxidized in an oxygen atmosphere at 800 ° C. by, for example, furnace oxidation to form a 4 nm first silicon oxide film. Thereafter, the first silicon oxide film is removed only in the transistor formation region of the present invention. Thereafter, a second silicon oxide film having a desired film thickness is formed by a rapid lamp heating method. Subsequent steps are manufactured through the same steps as those of the transistor formation method of the present invention described above.

  The semiconductor device manufactured as described above is a semiconductor device which is excellent as a whole because the high-performance transistor manufactured in the present invention is formed in a region where a transistor driven by a large current is required. Conventionally, for example, in a high-speed logic device, as shown in FIG. 19, the peripheral circuit portion (I / O portion) is formed of a bipolar transistor, and the internal logic circuit is formed of a CMOS transistor to increase the speed.

  By using the present invention, it is possible to manufacture only by a CMOS process, and a high-performance element can be realized at low cost.

  In addition, since the transistor of the present invention has a very thin gate insulating film of less than 2.5 nm, an excessive voltage, that is, a voltage exceeding the power supply voltage is applied due to sudden application of gate voltage, noise, etc. during LSI operation. If this situation occurs, a dielectric breakdown called gate breakdown occurs, and there is a problem that the MOSFET cannot function well.

  FIG. 29 shows a structure in which a Schottky diode 11 made of a metal / silicon layer is connected to the gate of the transistor 9 of the present invention as a dielectric breakdown protection circuit. This Schottky diode has a lower withstand voltage than the transistor 9 of the present invention.

  As the Schottky diode 9, either n-type silicon or p-type silicon can be used. As the metal, a metal mainly composed of Al, W, Ti, Mo, Ni, V, Co, or the like can be used.

Compared to a structure without a Schottky diode, when an excessive voltage such as noise is applied, the Schottky diode is destroyed and an overcurrent is generated, thereby destroying the gate insulating film of the transistor 9 of the present invention. Can be prevented.
That is, a semiconductor device that is resistant to electrostatic breakdown using the transistor of the present invention can be realized.

  In this embodiment, the description has been made using the example of the nMOSFET, but this structure can be applied to the pMOSFET as well. In this case, the gate side wall portion may be formed of BSG (B (boron) -containing silicon oxide film) and a shallow p-type source / drain region may be formed. This is the literature (authors M. Saito, T. Yoshitomi, H. Hara, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, HSMomose, Y. Katsumata, and H. Iwai; with Ultra-Shallow Solid-Phase-Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall; Source IEEE Trans.Electron Devices, vol.ED-40, no.12, pp.2264-2272, December, 1993) ing.

  Further, as described above, the source / drain diffusion layer may be formed not by a solid phase diffusion technique from the BSG side wall but by a normal ion implantation method of B (boron) atoms.

  FIG. 24 shows electrical characteristics of a p-type MOSFET in which a source / drain diffusion layer is formed by ion implantation. At this time, the gate oxide film thickness is 1.5 nm and the gate length is 0.2 μm. The pMOSFET produced by the present invention has a current driving force of 0.41 mA / μm and a transconductance of 408 mS / mm with a 1.5 V power source, and the literature (authors Y. Taur, S. Wind, YJMii, Y. Lii, D.Moy, KAJenkins, CLChen, PJCoane, D.Klaus, J.Bucchignano, MGRThomson, and M.Polcari; title “High Performance 0.1μm CMOS Devices with 1.5V Power Supply; Source IEDM Tech. Dig , pp. 127-130, 1993), the performance value of the 0.2 μm gate length pMOSFET is significantly higher than about 200 mS / mm, and this Tr is 0.06 mA with a 0.5 V power supply. A driving force of / μm and a mutual conductance of about 350 mS / mm are obtained.

  In this embodiment, the diffusion layer has a depth of 30 nm. However, the annealing conditions for diffusion and activation are appropriately selected between 700 ° C. and 1,100 ° C. for the temperature and time. Thus, a desired diffusion layer depth can be freely selected.

  FIG. 23 shows how the ratio Ig / Id of the gate current Ig to the channel current Id varies depending on the oxide film thickness Tox and the gate length Lg. The ratio Ig / Id is the same when the gate length is shortened to ½ when the film thickness is 1.5 nm, compared with the oxide film thickness of 1.5 nm when the thickness is 1.8 nm. It can be seen that the same amount of leakage current is produced.

As shown in FIG. 12, if 6 × 10 ⁻⁵ , which is a point at which Ig / Id suddenly increases, is set as a limit value, and the gate length Lg and the insulating film thickness Tox having the following characteristics are preferable, the following equation is obtained. Is established. When there is a limit of 6 × 10 ^-5 Ig / Id ratio,
Tox (nm) = logLg (μm) +2.02
Therefore, the gate length Lg (μm) allowed for a certain insulating film thickness Tox (nm) is
Lg ≦ 10 ^(Tox-2.02)
In order to further reduce the gate current, which is the power consumption, in order to improve the degree of integration of the LSI, and when applied to a 1 million (1M (mega) bit) memory, the influence on the power consumption of the LSI is about 10 mA. . ^Assuming that the allowable gate current of a transistor per transistor is 10 ⁻⁸ A / μm, from FIG. 6, this figure is described as a gate current per 10 μm gate width, so 10 ⁻⁸ A / μm. This is 0.15 μm when Tox = 1.5 nm, and 0.30 μm when Tox = 1.8 nm.
Tox (nm) = logLg (μm) +2.32
Therefore, the allowable gate length Lg (μm) at a certain film thickness is Lg ≦ 10 ^(Tox-2.32)
If so, the performance is further improved, and it can be applied to a highly integrated LSI.

  FIG. 27 shows Ig-Vg characteristics of a gate insulating film having various thicknesses Tox used for a normal tunnel gate oxide film MOSFET. FIG. 27 (a) and FIG. ) Is an extension of the latter over the former. As a result, FIG. 6A shows the characteristics of more types of gate insulating films than FIG. FIG. 6B shows the characteristics of the limited type of gate insulating film in more detail than that of FIG. This characteristic is measured by a MOS capacitor having a relatively large area (110 μm × 100 μm). When an insulating film having this characteristic is used for a MOSFET, the leakage current is reduced by reducing the gate area as shown in FIG. Is known to decrease.

  FIG. 29 shows the relationship between the gate leakage current and the gate length when the tunnel gate oxide film is applied to a MOSFET. As shown in this figure, when it is used for a MOSFET, it is known that the leakage current decreases according to the gate length Lg. However, the dependence on Lg is larger than the −1th power of Lg. Therefore, when a circuit is configured with only a short gate length, an increase in power consumption due to a leakage current can be suppressed as compared with a long Lg transistor.

  FIG. 30 shows a MOSFET of the present invention in comparison with a conventional one. FIG. 30A shows a MOSFET according to the present invention, and FIG. 30B shows a conventional MOSFET. When configuring a circuit having performance equivalent to that of the MOSFET 13 having the gate length shown in FIG. 5B and low power consumption, the fine gate length MOSFETs 12 are appropriately connected in series as shown in FIG. A circuit having a desired driving force can be realized. With this configuration, it is possible to realize a semiconductor device suitable for low power consumption by sufficiently suppressing the leakage current which has been a problem in the conventional structure.

1 is a device cross-sectional view illustrating a structure of a MOS transistor according to an embodiment of the present invention. FIG. 2 is an impurity concentration profile diagram of the transistor shown in FIG. 1. The curve figure which shows the gate oxide film thickness dependence of the deterioration amount of the transconductance under the hot carrier stress (Vd = 2.5V, Isubmax, 1000 second stress application) of the transistor. The curve figure (W = 10 micrometer) which shows the gate length Lg dependence of the tunnel current Ig of the transistor. The curve figure which shows the gate length Lg dependence of the drain current Id0 of the transistor (W = 10 micrometer). The curve figure (W = 10 micrometer) which shows the gate length Lg dependence of the tunnel current Ig of the transistor. The curve figure (W = 10 micrometer) which shows the gate length Lg dependence of the conductance gm of the transistor. The curve diagram (W) which shows the gate length Lg dependence of the substrate maximum current Isubmax of the transistor (a) and the curve diagram (W = 10 μm) (b) which shows the gate voltage dependency of the substrate current Isub of the transistor. The curve figure (W = 10 micrometer) which shows the gate length Lg dependence of the impact ionization rate of the transistor. The curve figure which shows the power supply voltage Vd = Vg dependence of the current Ig of the same transistor, Id (Lg = 0.14 micrometer, W = 10 micrometer). The curve figure which shows the power supply voltage Vd = Vg dependence of the drain current Id of the transistor. The curve figure which shows the power supply voltage (Vd = Vg) dependence of Ig / Id of the transistor. The curve figure which shows the gate length dependence of the Id-Vd characteristic of the transistor. The curve figure which shows the gate length dependence of the conductance gm of the transistor. The curve figure (power supply voltage 0.5V) which contrasts the characteristic of the conventional transistor about the main characteristics of the transistor of this invention. The curve figure which shows the effective electric field dependence of carrier mobility. The curve figure which shows the deterioration (deterioration of transconductance with respect to stress time) characteristic of the conductance gm of the MOS type transistor which concerns on one Example of this invention. An example of a semiconductor device according to the present invention, a semiconductor device (a) in which the semiconductor device of the entire region is fabricated with the MOSFET of the present invention, a semiconductor device (b) in which the MOSFET of the present invention is fabricated in a part of the region, and a peripheral region BRIEF DESCRIPTION OF THE DRAWINGS Schematic explanatory drawing which shows the structure of the semiconductor device (c) which produced MOSFET of this invention. Schematic explanatory drawing which shows the structure of the prior art example of the high-speed semiconductor device formed with the bipolar transistor and the CMOS transistor. FIG. 6 is a curve diagram showing the voltage dependence of the mutual conductance of a transistor with Lg = 0.09 μm and Tox = 1.5 nm. The curve figure which shows the power supply voltage dependence of a mutual conductance. The curve figure which shows the power supply voltage dependence of the current driving force per unit. The curve diagram which shows gate current ratio Ig / Id with respect to the channel current with respect to gate length Lg. Tox = 1.5 nm, Lg = 0.2 μm Curves showing pMOS transistor characteristics (Id-Vd characteristic (a), gm-Vg characteristic (b)). Lg = 0.4 μm, Tox = 9 nm transistor (conventional example), Lg = 0.1 μm, Tox = 3 nm transistor (conventional example), Lg = 0.14 μm and Lg = 0.09 μm, Tox = 1.5 nm transistor (present) FIG. 4 is a curve diagram showing the relationship between the clock frequency and the power consumption determined by charge erasing and subthreshold leakage (a), and the relationship (b) between the clock frequency and the power consumption component determined by the gate leakage current. Lg = 0.4 μm, Tox = 9 nm transistor (conventional example), Lg = 0.1 μm, Tox = 3 nm transistor (conventional example), Lg = 0.14 μm and Lg = 0.09 μm, Tox = 1.5 nm transistor (present) FIG. 5 is a curve diagram illustrating a relationship between power consumption and clock frequency when the same power consumption is used for all transistors or the same clock frequency condition. The gate insulating film having various thicknesses Tox used for a normal tunnel gate oxide film MOSFET shows Ig-Vg characteristics. The curve diagram (a) showing more types of gate insulating films and the gate insulating film thickness Curve diagram (b) showing the details of the limited types of gate insulating films. FIG. 3 is a circuit diagram showing a structure of a semiconductor device using a MOSFET in which a gate insulating film is protected according to the present invention. The curve figure which shows Lg-Ig characteristic about MOSFET whose gate insulating film Tox is 1.5 nm. 1 is a circuit diagram showing a structure of a semiconductor device using a MOSFET in which a gate leakage current according to the present invention is reduced.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate electrode 3 Gate oxide film 4 Channel formation area 5 Source area 6 Drain area 7 Gate power supply 8 Drain power supply 9 MOSFET which has normal gate length
10 Low Voltage Power Supply 11 Schottky Diode 12 MOSFET with Fine Gate Length

Claims (3)

A first conductivity type semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the semiconductor substrate via the gate insulating film;
In a MOS type semiconductor device comprising a second conductivity type source / drain region formed on both sides of a channel formation region located directly under the gate electrode of the semiconductor substrate,
The thickness of the gate insulating film is less than 2.5 nm in terms of oxide film, the gate length of the gate electrode is 0.3 μm or less, the length (Lg) of the gate electrode in the channel direction and the silicon film of the gate insulating film The relationship of the converted thickness (Tox) is as follows: Lg ≦ 10 ^(Tox-2.02) At this time, the unit of Lg is (μm)
The unit of Tox is (nm)
A semiconductor device characterized by satisfying The relationship between the length (Lg) of the gate electrode in the channel direction (Lg) and the equivalent thickness of the gate insulating film (Tox) is as follows: Lg ≦ 10 ^{(Tox−2.32) where} the unit of Lg is (μm )
The unit of Tox is (nm)
The semiconductor device according to claim 1, wherein:   A semiconductor integrated circuit device comprising a part of the semiconductor device according to claim 1 in part.

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