JPS61289667A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a phenomenon of discharge around a semiconductor element and thereby to enable the attainment of high performance and high reliability, by providing a low-resistance semiconductor film with impurities of high concentration added thereto, and a high-resistance semiconductor film formed on an insulating film integrally with said semiconductor film and containing no impurities substantially. CONSTITUTION:An epitaxial layer 22 and first and second semiconductor layers 23a and 23b are formed on a substrate 21, and a field oxide film 25b, a gate oxide film 25c, a polycrystalline silicon film 26a, a photoresist film 27, a polycrystalline silicon film 26c and a semiconductor layer 28 are formed on the main surface of the epitaxial layer 22. Thereafter a silicon oxide film 25d containing no impurities is deposited and a PSG film 25e containing phosphorus of high concentration is formed. Next, contact holes are opened in the CVD-SiO2 film 25d and the PSG film 25e, a source Al electrode 29 and a gate Al electrode are formed therein, and thus DSA MOS FET having a field plate and a high- resistance polycrystalline silicon film 26a of non-dope together with a gate electrode film is completed. By this method, the attainment of high reliability and high performance is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, particularly a high voltage semiconductor device and a method for manufacturing the same, and particularly relates to a technique for improving the reliability thereof.

(Prior Art) In recent years, as the demand for high-voltage, high-power transistors has increased, transistors with particularly high performance and high reliability have become desired.

Generally, for high voltage transistors of 800 V or 1000 V or more, a field limiting ring is used to expand the depletion layer on a silicon substrate with a low impurity concentration, or to make it easier to expand the depletion layer and stabilize the potential. field plate and is doped with Linnaeus to further improve reliability.
A passivation film such as (Phospho 5 Ilicate Glass) film is provided.

Figure 5 shows an example of a conventional high voltage semiconductor device.
Diffusion Self-Alignment)
The structure of the power MO3FET is shown. O
3A MOS PET forms a channel by double diffusion, and impurities are added to form the channel region through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon film formed through a gate oxide film. The feature is that diffusion and impurity diffusion for forming a source region are performed.

As shown in FIG. 5, an n-type epitaxial layer 2 is formed on an n-type semiconductor substrate 1 constituting a drain region.
It has an on-n+ structure, and the drain electrode 1a is formed on the back surface of the n-conductor substrate 1. A gate oxide film 5a is formed on the main surface of the n-type epitaxial layer 2, and a gate polycrystalline silicon film 6 is formed thereon. This gate polycrystalline silicon film 6 is formed in a predetermined pattern and constitutes a cell. Each cell includes a p type groove conductor layer 3, a p type semiconductor layer 4 constituting a channel region,
An n-type trench conductor layer 8 constituting a source region is formed. On the polycrystalline silicon film 6, an oxide film 5b and a PS
A G film 5c is formed, and the p'' type groove conductor layer 3 and the n'' type groove conductor layer 8 are formed through the openings made in these insulating films.
A source electrode 9 made of aluminum and in ohmic contact with both is formed on the PSG film 5. field, surrounding the cell assembly region to widen the depletion layer.
Limiting ring (hereinafter abbreviated as FLR)
10a and 10b are formed, and a field plate (hereinafter abbreviated as FP) is formed in contact with these FLRs.

11b is formed on the PSG film 5 deposited on the field oxide film 5d. Furthermore, on the outermost periphery of the chip, n
゛゛A channel stopper 12 made of a semiconductor layer is formed, and an equal potential ring (hereinafter referred to as
It is abbreviated as I'OR, an acronym for equi-ptential ring. )13 are connected.

(Problems to be Solved by the Invention) In the conventional O3A M port SF [ET shown in FIG.
Since the silicon substrate 1.2 with the following low impurity concentration is used, the surface of the semiconductor element is susceptible to changes depending on various surrounding conditions, and in particular, the source/drain surface may deteriorate due to contamination due to moisture, Na ions, heavy metal ions, resin mold sealing, etc. There is a drawback that the voltage VDSS deteriorates and the characteristics deteriorate. Similar drawbacks also occur in bipolar transistors, in which case the base-collector voltage V C
ll0 will deteriorate. Doping pure Linnaeus into the conventional PSG film is very effective in trapping Na ions and heavy metal ions, but it has extremely high moisture absorption, and requires a high breakdown voltage of 800μ or more. In such transistors, there is a drawback that breakdown voltage deteriorates particularly in high temperature reverse bias tests.

Furthermore, in conventional high-voltage transistors, in order to stabilize the device characteristics, especially the breakdown voltage, PLRloa, l is used to make it easier for the depletion layer to spread around the lubricating region.
In addition, a channel stopper 12 for stabilizing the potential around the transistor and an 1EQR 13 connected thereto are formed. however,
A high voltage ranging from several hundred volts to several thousand volts is applied between the outermost FpHb and εQR13 located further outside, and these are formed from a relatively thick aluminum metal film of 3 to 5 μm. Since the pattern edges are sharp, a discharge phenomenon tends to occur between the two, resulting in damage to the device. In order to prevent such discharge, it is possible to cover the Aj7 electrode film with a PSG passivation film, but since the edges of the electrode film pattern are sharp, there is no PSG in this part.
Since the SG film is not formed at all, or even if it is formed, it is only formed very thinly, so that the discharge phenomenon cannot be effectively prevented. Such a discharge phenomenon occurs particularly during wafer probing in a reverse bias test, and semiconductor devices manufactured with high yields become defective products, so it is necessary to prevent them as much as possible.

The present invention has been made in view of the above-mentioned problems, and in a semiconductor device that requires a high breakdown voltage, a high-resistance semiconductor film containing no impurities and a low-resistance semiconductor film containing impurities are placed in the vicinity of the active region via an insulating film. By continuously providing a semiconductor film, it is possible to prevent a discharge phenomenon around a semiconductor element, provide a high performance and highly reliable semiconductor device, and manufacture such a semiconductor device with excellent productivity. The aim is to provide a manufacturing method that can.

(Means for Solving the Problems) A semiconductor device of the present invention includes a semiconductor substrate of one conductivity type, a semiconductor layer of an opposite conductivity type formed on the main surface of the semiconductor substrate,
An insulating film formed on the main surface of the semiconductor substrate, and an insulating film provided in such a way that it contacts the semiconductor layer through an opening in the insulating film and extends partially over the insulating film beyond the semiconductor layer. A low resistance semiconductor film doped with impurities,
It is characterized by comprising a high-resistance semiconductor film that is formed integrally with this low-resistance semiconductor film on an insulating film and that does not substantially contain impurities.

Furthermore, the method for manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor layer of an opposite conductivity type on the main surface of a semiconductor substrate of one conductivity type, a step of forming an insulating film on the main surface of the semiconductor substrate, and a step of forming an insulating film on the main surface of the semiconductor substrate. forming a high-resistance semiconductor film substantially free of impurities on the insulating film so as to contact the semiconductor layer through an opening formed in the insulating film; A low-resistance semiconductor film is formed by selectively doping impurities of the opposite conductivity type into parts including those in contact with the semiconductor layer, and at the same time, impurities of the opposite conductivity type are also doped into the semiconductor substrate to form a semiconductor layer of the opposite conductivity type. The method is characterized by comprising a step of forming.

An embodiment of the semiconductor device of the present invention includes a semiconductor substrate of one conductivity type, a first semiconductor layer of the opposite conductivity type formed on the main surface of the semiconductor substrate, and a layer surrounding the first semiconductor layer. A second electrode of opposite conductivity type formed on the main surface of the semiconductor substrate
a semiconductor layer, an insulating film formed on the main surface of the semiconductor substrate, and a semiconductor layer that contacts the first semiconductor layer through an opening in the insulating film and extends over the insulating film, with a portion extending beyond the first semiconductor layer. a first low-resistance semiconductor film doped with impurities at a high concentration; a second low-resistance semiconductor film doped with impurities at a high concentration, the second low-resistance semiconductor film being in contact with the semiconductor layer and partially extending over the insulating film beyond the second semiconductor layer;
A high-resistance semiconductor film that is provided integrally with the second low-resistance semiconductor film on the insulating film and that does not substantially contain impurities is provided between the second low-resistance semiconductor film and the second low-resistance semiconductor film.

Another embodiment of the semiconductor device of the present invention includes a semiconductor substrate of one conductivity type, a first semiconductor layer of the opposite conductivity type formed on the main surface of the semiconductor substrate, and a semiconductor layer surrounding the first semiconductor layer. a second semiconductor layer of the opposite conductivity type formed on the main surface of the semiconductor substrate; a third semiconductor layer of one conductivity type formed on the main surface of the semiconductor substrate surrounding the semiconductor layer; an insulating film formed on the main surface of the semiconductor substrate; and an insulating film that contacts the first semiconductor layer through an opening in the insulating film and extends partially over the insulating film beyond the first semiconductor layer. a first low-resistance semiconductor film that is provided and doped with impurities at a high concentration; and a first low-resistance semiconductor film that is formed integrally with the first low-resistance semiconductor film and contacts the second semiconductor layer through an opening formed in the insulating film. The second semiconductor layer is provided such that a portion thereof extends over the insulating film beyond the second semiconductor layer, and is doped with impurities at a high concentration.
is formed integrally with the first and second low-resistance semiconductor films, and contacts the third semiconductor layer through an opening in the insulating film, and a portion of the third semiconductor layer contacts the third semiconductor layer. a third low-resistance semiconductor film extending over the insulating film and doped with impurities at a high concentration; formed integrally with the second and third low-resistance semiconductor films on the insulating film, and located between the first and second low-resistance semiconductor films and between the second and third low-resistance semiconductor films, respectively; and first and second high-resistance semiconductor films substantially free of impurities.

Furthermore, an embodiment of the method for manufacturing a semiconductor device of the present invention includes a step of forming a first semiconductor layer of an opposite conductivity type on the main surface of a semiconductor substrate of one conductivity type, and a step of forming an insulating layer on the main surface of the semiconductor substrate. forming a high-resistance first semiconductor film substantially free of impurities on the insulating film so as to contact the first semiconductor layer through an opening formed in the insulating film; forming a second semiconductor layer entirely located on the insulating film; doping the main surface of the semiconductor substrate with impurities of opposite conductivity type to form a second semiconductor layer of opposite conductivity type; doping a portion of the first semiconductor film, including a portion that contacts the first semiconductor layer through the opening, and the second semiconductor film with impurities of opposite conductivity type to lower the resistance; Selectively doping an impurity of one conductivity type into the layer to form a third semiconductor layer of one conductivity type, and at the same time selectively doping the second semiconductor film with an impurity of one conductivity type to form a pn junction. The method includes the step of:

(Function) In the high-voltage semiconductor device of the present invention, the field plate and the equal potential ring are constructed of a low-resistance polycrystalline silicon film or an amorphous silicon film doped with a large amount of impurities. Because there is a high-resistance polycrystalline silicon film or amorphous silicon film between them that contains no or almost no impurities, even if a high voltage is applied between the field plate and the equal potential ring, No discharge phenomenon occurs, and the semiconductor device can be effectively protected from destruction.

Furthermore, these polycrystalline silicon films and amorphous silicon films effectively block Na ions, heavy metal ions, moisture, etc., making it possible to obtain highly reliable semiconductor devices regardless of ambient conditions. can.

(Example) FIGS. 1(a) to 1(f) show states in successive manufacturing steps of an O3A MOS FBT, which is a first example of a semiconductor device of the present invention.

First, an n-type epitaxial layer 22 is formed on an n-type semiconductor substrate 21 to have a specific resistance of 40 to 60 Ω-Cffi and a thickness of 80 to 100 μm, and then the n-type epitaxial layer 22 is placed in the cell at the opening of the gate polycrystalline silicon film. A first p-type trench conductor layer 23a and a second p-type trench conductor layer 23b located around this cell integrated area and electrically connected to the source electrode are formed in the same diffusion process. . Furthermore, a silicon oxide film 25a is formed on the main surface of the n° type epitaxial layer 22. This situation is shown in FIG. 1(a).

Thereafter, a field oxide film 25b having a thickness of about 8,000 wafers is formed in the field region, followed by a gate oxide film 25C having a thickness of about 1,000 nits, as shown in FIG. 1(b).

Subsequently, after selectively opening the field oxide film 25b, a polycrystalline silicon film 26a substantially free of impurities is deposited to a thickness of about 4,000 layers, for example, and then selectively patterned. At this time, the polycrystalline silicon film 26a
is a second p” type semiconductor layer 2 located around the cell integrated part.
The patterning is performed to extend from field oxide film 3b onto field oxide film 25b. This situation is shown in FIG. 1(C).

Next, after selectively forming a photoresist film 27 using photoetching technology, boron ions, for example, are implanted to convert a portion of the polycrystalline silicon film 26a into a p-type concrystalline silicon film 26b. This p-type child crystalline silicon film 26b constitutes a field plate.

At the same time, boron ions are implanted into the n-type epitaxial layer 220 where the channel region is to be formed.
A type semiconductor layer 24 is formed. This situation is shown in Figure 1(d).
Shown below.

Next, a photoresist film is selectively formed again using photoetching technology, and ion implantation of, for example, phosphorus is performed at a high concentration to form an n-type polycrystalline silicon film 26C as a gate electrode and an n-type polycrystalline silicon film 26C to act as a source region. A mold groove conductor layer 28 is formed. This situation is shown in FIG. 1(e).

Thereafter, a silicon oxide film (CVD 5ITo) 25d containing no impurities was uniformly deposited to a thickness of approximately 3000 mm using the CVD method, and on top of this, PS containing a high concentration of phosphorus was deposited.
A G film 25e is formed to a thickness of about 5000 Å. next,
After performing various thermal processes, contact holes are opened in the CVD-3lO□ film 25d and the PSG film 25e, and a source A1 electrode 29 and a gate Al electrode (not shown) are formed. In this way, the n+ type polycrystalline silicon film 26C
O3A M has a gate electrode film made of a p+ type polycrystalline silicon film 26d, and a field plate made of a p+ type polycrystalline silicon film 26d, and a non-doped high resistance polycrystalline silicon film 26& formed integrally with this field plate.
OS FET is completed. This situation is shown in FIG. 1(f).

FIGS. 2(a) to 2(f) show states in successive manufacturing steps of a high voltage O3A MOS FBT, which is a second embodiment of the semiconductor device according to the present invention.

An n-type epitaxial layer 32 is placed on an n++ semiconductor substrate 31, for example, with a specific resistance of 40 to 60 Ω-CI and a thickness of 80 to 100 Ω.
After forming a silicon oxide film 35a on the surface, a p-type thick conductor layer is formed to a depth of, for example, about 15 μm. This p-type thick conductor layer, the first p-type groove conductor layer 33a in the cell located in the gate polycrystalline silicon opening, and the first p a second p゛ type half body layer 33b in contact with;
In order to increase the source-drain breakdown voltage (Voss), the depletion layer from the second p'' type semiconductor layer 33b tends to spread (and the field limiting layer located in a ring shape around the second p'' type semiconductor layer 33b) There is a third p-type groove conductor layer 33c called a ring, which is formed in the same diffusion process.This situation is shown in FIG. 2(a).

After that, the field silicon oxide film 35b with a thickness of about 3000 layers is formed into a field limiting ring (
A gate oxide film 35C is then formed to a thickness of about 1000A, and the field oxide film 33b is selectively opened.
).

Next, a polycrystalline silicon film 36 that does not substantially contain impurities
After depositing, for example, about 4000 layers to a zero thickness, it is selectively patterned. At this time, a third p-type semiconductor layer 33 forming a field limiting ring is formed from the second p-type semiconductor layer 33b located around the cell integrated portion.
C, and further this third p'' type semiconductor layer 33c.
It is formed from the tip to the circumferential edge of the chip.

Subsequently, a photoresist film 37 is selectively left on the polycrystalline silicon 36a on the field silicon oxide film 35b using a photoetching technique. This situation is shown in Figure 2 (
Shown in C). Next, selectively implant p-type impurity ions,
Using the pattern of the polycrystalline silicon film 36a for gate electrode as a mask, the p-type semiconductor 34 constituting the channel region is formed in a self-aligned manner.

At this time, all p impurities of the gate protection diode are ion-implanted into the polycrystalline silicon film 36a at the same time to form a p-type child crystalline silicon 36b.

Next, using photoetching technology again, the polycrystalline silicon film 36a near the filled limiting ring (on the field oxide film) and the polycrystalline silicon film 36b of the gate protection diode are selectively patterned with photoresist. do. This situation is shown in FIG. 2(d). After that, ion implantation is performed, and the n-type groove conductor layer 38a,
Gate protection diode n-type polycrystalline silicon film 36C
1. Then, an n+ type polycrystalline silicon film 36c for an equal potential ring for the purpose of stabilizing the potential around the silicon chip and an n+ type groove conductor layer 38b for a channel stopper are simultaneously formed. Subsequently, a CVD-St02 film 35d containing no impurities is formed to a thickness of approximately 3000 nm using the CVD method, and a PSG film 3 containing a high concentration of phosphorus is formed.
Figure 2 (e
).

After that, after performing various heat treatments, contact holes are opened in the CVD-3in2 film 35d and the PSG film 35e, and the source A1 electrode 39a and the gate Al electrode 39b are connected to each other.
A polycrystalline silicon film 36b is formed between the gate and source.
The O3FBT is completed to O88 having a protection diode consisting of and 36c. This situation is shown in FIG. 2(f).

FIG. 3 shows a third embodiment of the semiconductor device according to the present invention, and shows a cross-sectional structural diagram of a high voltage O3A MOS FET. The manufacturing process of the semiconductor device of this example is shown in FIGS.
It is almost the same as the second embodiment shown in f), and similar parts are designated by the same reference numerals. In this example, during p-type ion implantation and n
By forming a photoresist pattern during pear-shaped ion implantation, an n-type thick conductor is formed in the n-type polycrystalline silicon film 36c constituting the field plate and the third p-type semiconductor layer 33d constituting the field limiting ring. Layer 38c is formed at the same time. This n-type thick conductor layer 38
c action is as follows. That is, when a positive charge is applied to the source region and a negative charge is applied to the drain region, the second
The depletion layer spreading from the p'' type semiconductor layer 33b reaches the third p'' type semiconductor layer 33C (field limiting ring) at a certain potential, and this third p+ type semiconductor layer is connected to the second p'' type semiconductor layer 33b. becomes the same potential as Therefore, the third p'' type semiconductor layers 33c and 33d in the field limiting ring, the n'' type groove conductor layer 38C, and the n'' type polycrystalline silicon film 36C are the third p'' type semiconductor layer 3.
3c and 33d, it fully fulfills the role of a field plate, and the p-type child crystal film 36 of the second embodiment
It will have the same function as the field plate made of b.

In this example, a polycrystalline silicon film that does not substantially contain impurities refers to not only one that does not contain any impurities at all, but also a polycrystalline silicon film that contains a trace amount of n-type impurity or an n-type impurity to deposit the polycrystalline silicon film. It does not matter if they are mixed in at some point. Generally, there is no problem as long as the impurity concentration is 101 to 1013 atoms/cd or less.

In the so-called embodiment of the present invention, the second p'' type semiconductor layer, the third p'' type semiconductor layer, and the polycrystalline silicon film located through the insulating film have increased conductivity, and perform MO8 operation or an operation close to this. , for example, a sheet of several kiloohms or several megaohms that does not cause the phenomenon of not being able to obtain the normal withstand voltage even though it satisfies the optimum silicon wafer concentration, thickness, and field limiting ring. Any polycrystalline silicon film with resistance may be used.

Further, in the above embodiment, a polycrystalline silicon film containing no impurities was deposited on the field silicon oxide film, but an amorphous silicon film may be used instead.

In particular, when amorphous silicon is not doped with impurities, extremely low concentration n-type amorphous silicon is formed during the deposition process, so by mixing extremely low concentration p-type impurities, An amorphous silicon film with an extremely low concentration of 101' to 1012 atoms/Cd or less can be obtained. Therefore, amorphous silicon is particularly suitable for
Since the deposition is performed in a plasma atmosphere of about 300°C, shallow junctions are formed in advance in MOS type semiconductor devices, for example.
) can be used as a passivation film in the field silicon oxide film, but also on the electrode, for example, polyimide resin, plasma oxide film, or plasma oxidation film can be used on the electrode. It can be used as a passivation film or an interlayer insulating film for multilayer wiring together with an insulating film that can be processed at an extremely low temperature such as a film.

In the above-described embodiments, a MOS type semiconductor device was used as an example, but the present invention can also be applied to a bipolar rain semiconductor device or a high voltage semiconductor device such as a diode. or,
It may also be used for low voltage semiconductor devices. In embodiments of the present invention, p and n may be reversed.

(Effects of the Invention) As described above, according to the present invention, among semiconductor films, for example, polycrystalline silicon films that do not contain semiconductor impurities are devised in various ways, and can be processed in the same process step without increasing the number of conventional process steps. It is called a gate protection diode, and is used to protect an extremely thin gate insulating film from dielectric breakdown due to static electricity. When forming an n1 type semiconductor layer), it is possible to form a pn diode using a polycrystalline silicon film, and at this time, the polycrystalline silicon film is selectively covered with a photoresist, so that it does not contain impurities. A high resistance and strong passivation film and a field plate made of a polycrystalline silicon film doped with p-type impurities or a field plate made of a polycrystalline silicon film doped with n+ type impurities can be integrally formed.

Particularly in high-voltage MOS semiconductor devices, the most important point is how well the peripheral structure of the cell integrated part can maintain its initial characteristics without being affected by surrounding conditions. Sodium, heavy metal ions, etc. are trapped in the PSG film, and the above ions that pass through the PSG film, as well as especially water, are trapped in a field plate made of an n-type polycrystalline silicon film containing a high concentration of phosphorus, or a p-silicon film. The field plate made of a patterned crystalline silicon film is completely isolated by a polycrystalline silicon film having high resistance and does not contain semiconductor impurities, and the interface between the thick silicon oxide film particularly on the field region and the n-type epitaxial layer is formed. Since contamination in the vicinity can be prevented, it is possible to create a high voltage transistor with less leakage current between the source and drain. Moreover, the most important point of the present invention is that n-type impurity ions are selectively implanted into a polycrystalline silicon film that does not contain impurities, one side is used as a gate electrode, and the other is an n-type packed crystal silicon film for a gate protection diode. On the other hand, the field plate from the source n-type semiconductor layer is formed, and the n-type semiconductor layer constituting the equal potential ring and the channel stopper are simultaneously formed, and finally, the selective The remaining impurity-free polycrystalline silicon film is formed on the field as a strong passivation film, making it possible to create a highly reliable, high-performance, high-voltage semiconductor device.

By the way, in the embodiment according to the present invention, the initial value is 120.
A source-drain breakdown voltage of 0 V was obtained.

Figure 4 shows the conventional element and the USA MOS according to the present invention.
This figure shows the reliability test for source-drain breakdown voltage during high-temperature reverse bias testing of FAT. The data in Figure 4 clearly shows how superior the semiconductor device of the present invention is, as it is not enough to use conventional PSG films or metal field plates for high-voltage semiconductor devices such as high-voltage MO3FBTs. Recognize.

Next, the present invention solves the discharge phenomenon that is often observed between a field plate on a field limiting ring and an equal potential ring in a high voltage element by using p or n゛ metal film instead of the conventional ^β metal film. This can be prevented by using a type polycrystalline silicon layer, which is formed together with the gate polycrystalline silicon electrode or gate protection diode in MOS FBTs, and in the same process as the polycrystalline silicon layer for the emitter resistor in bipolar transistors. Formable. Therefore, the field plate made of polycrystalline silicon is, for example, a Cv row 5 formed by the CVD method.
It is possible to cover the surface well with i02 or PSG, and the CV
D-3iOz acts as a strong insulating film, so it can be used as a conventional metallic field plate or
Unlike potential rings, no discharge occurs at all, and for example, damage to non-defective products due to discharge during the wafer blobbing process for selecting non-defective products can be completely eliminated.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are cross-sectional views showing the configuration of one embodiment of the semiconductor device according to the present invention in the sequential manufacturing process, and FIGS. 2(a) to (f) are the same (other embodiments). 3 is a cross-sectional view showing the structure of another embodiment. FIG. 4 is a cross-sectional view showing the structure of a semiconductor device of the present invention and a conventional semiconductor device in a high-temperature reverse bias test. 5 is a cross-sectional view showing the structure of a conventional semiconductor device. 21...n゛゛Semiconductor substrate 22...N-type epitaxial layer 23a, 23b...p "type semiconductor layer 24...P-type semiconductor layer 25b...Field oxide film 25C...Gate oxide film 26&...High resistance polycrystalline silicon film 26b, 26c...Low resistance polycrystalline silicon film 28...
... n'-type semiconductor layer 29... source Al electrode 31... n'-type semiconductor substrate 32... n-type epitaxial layer 33a, 33b, 33c... p'' type semiconductor layer 34... p-type Semiconductor layer 36a...High resistance polycrystalline silicon film 36b...P-type subcrystalline silicon film 36c...N-type subcrystalline silicon film 38a, 38b-n" type semiconductor 1 39a...Source Al electrode 39b. ...Ge) 1 electrode Figure 1

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type formed on the main surface of the semiconductor substrate, an insulating film formed on the main surface of the semiconductor substrate, and the insulating film formed on the main surface of the semiconductor substrate. A low-resistance semiconductor film doped with impurities at a high concentration, which is provided so as to contact the semiconductor layer through an opening in the film and partially extend over the insulating film beyond the semiconductor layer; 1. A semiconductor device comprising a high-resistance semiconductor film that is formed integrally with a semiconductor film on an insulating film and that is substantially free of impurities. 2. A step of forming a semiconductor layer of an opposite conductivity type on the main surface of a semiconductor substrate of one conductivity type, a step of forming an insulating film on the main surface of the semiconductor substrate, and an opening formed on the insulating film. forming a high-resistance semiconductor film substantially free of impurities so as to contact the semiconductor layer through the opening; It is characterized by comprising the step of selectively doping impurities of opposite conductivity type to form a low-resistance semiconductor film, and simultaneously doping the semiconductor substrate with impurities of opposite conductivity type to form a semiconductor layer of opposite conductivity type. A method for manufacturing a semiconductor device.