JPH0312970A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable high-speed and large-breakdown-proof-quantity turnoff operation by placing a contact point of a second main electrode and a second semiconductor region in said second semiconductor region in contact with a fourth semiconductor region closer to the force semiconductor region than to a third semiconductor region. CONSTITUTION:A plurality of p-layers 13 are arranged in parallel so that the outer one may come into contact with a surrounding p-layer 15 and an n<+> layer 14 is formed in the outer p-layer 13 or the next p-layer 13 to place a contact point of the same p-layer 13 and a second main electrode 3 closer to the surrounding p-layer 15 than to the n<+> layer 14. By this placing the contact point of the second main electrode 3, the surrounding p-layer 15, and the p-layer 13 closer to the surrounding p-layer 15, and the p-layer 13 closer to the surrounding p-layer 15 than the nearest n<+> layer 14, a hole current and a charging current stored around substrate are drawn quickly in turnoff and a parasitic thyristor and a parasitic transistor are not activated by said hole current and charging current. Thereby high-speed and large-breakdwon-proof-quantity turnoff operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor having an insulated gate, and particularly to a structure with excellent high speed and breakdown resistance.

[Conventional technology]

Recently, power MO3FET (MetalOxi
de-5emiconductor Field Ef
trans]5tor) and IGBT (insulated gate bipolar transistor).

In5lated Gate Bipolar Tr
ans4stor) is becoming widely used. FIG. 5 shows a schematic view from their surface. In a power MO5FET or an IGBT 1, first insulated gate electrodes 4 are formed, for example, in a stripe shape on a semiconductor substrate 1, and these first insulated gate electrodes 4 are electrically connected to a surrounding second insulated gate electrode 6. are doing. Reference numeral 10 denotes an electrode line that supplies control power to the insulated gate electrodes 4 and 6.

FIG. 6 shows a cross-sectional structure taken along VI-Vl in FIG. 5 (Fuji Jiho VoQ, 61.Na1l, pages 697-7oO).

In FIG. 6, semiconductor substrate 1 has a pair of main surfaces 101.
102 and has a high impurity concentration adjacent to one main surface 101 and has an n+ or p+ substrate region]-1, an n− layer 12 and a lower impurity concentration adjacent to the substrate region 11;
A plurality of two layers 13 each having a higher impurity concentration than the n- layer 12 are formed in the − layer 12 and are geometrically separated from each other. Furthermore, within the two layers 13, two n-middle layers 14 each having a higher impurity concentration are formed separately. On the other main surface 102, the n-J112.2 layer 13 and the n+10 layer 4 are exposed. 2 is a collector electrode that is in ohmic contact with the surface of the substrate region 11, and 3 is an emitter electrode that is in ohmic contact with the two n-middle layers 14 and the two layers 13 located therebetween at 102 on the other main surface. The first insulated gate electrode 4 is formed from the n- layer 12 to the second layer 1 through the insulating film 5.
3 to reach above the n-middle layer 14.

In order to reduce parasitic capacitance, the second insulated gate electrode 6 has a peripheral p upper layer 15 that is thicker than the two layers 13 that are integrally formed so as to be located on the peripheral side of the two layers 13 located on the peripheral edge. is formed through. The emitter electrode 3 is formed by the first insulating film 8. The second insulating gate 1 is insulated and separated from the electrodes 4 and 6.

As mentioned above, power MO5FET and IGBT
is a unit 1- centered around the insulated gate electrode 4 of each node 1.
It is divided into a region (2) in which cells are repeatedly formed and the other peripheral region (2).

To turn on such a semiconductor device, the collector electrode 2 is set to a positive potential with respect to the emitter electrode 3, and then the first . The second insulated gate electrode 4.6 is brought to a positive potential with respect to the emitter electrode 3. As a result, the surface of the first layer 13 adjacent to the insulating film 5 is inverted to nil, and electrons flow into the p-substrate region 11 through the emitter electrode 3, the n-layer 14, the inverted n-layer, and the n- layer 12. As a result, the injection of positive charge pole (2) from the P-substrate region 11 is promoted, and the pole (2) flows into the emitter electrode 3 through the n- layer 12.1 layer 13. Due to the above flow of electrons and holes, a current flows from the collector electrode 12 to the emitter electrode 3. Furthermore, in order to change the on state to the off state, first. The potential of the second insulated gate electrodes 4 and 6 may be removed. The inverted n-layer disappears and the electron current is cut off, resulting in no hole injection and no current flow.

The IGBT has a p+ substrate region 11, a p ten-layer substrate region 11, an n- layer 12 . p layer 13. Since it has a four-layer structure of n10 layers 14, a parasitic thyristor is formed. Once this parasitic thyristor starts operating, the first. The second insulated gates 4 and 6 become uncontrollable, resulting in runaway current and destruction due to Joule heat. This is called latch-up. This latch-up occurs not only in the area but also in the peripheral area (2). Depending on the structure, latch-up may occur more easily in region (2), and the breakdown resistance of the IGBT may be determined by region (2). FIG. 6 shows a structure that takes measures against this problem. In other words, the first layer 13 and the peripheral p-middle layer 15 are brought into contact with each other so that no electron current flows through the n-middle layer 14 in the region (2). In other words, the peripheral p-middle layer 15 is designed so that the peripheral p-middle layer 15 is not easily inverted to n-type under the second insulated gate 6.
The carrier concentration of the insulating film 7 is made higher than that of the single layer 13, and the insulating film 7 is made thicker. As a result, the hole ■ that exists in the area ■
The amount of resistance R under the n-layer M14 is smaller than that in the region ■.
The voltage drop in the 1st layer 13 and the 10 peripheral p layers 15 caused by the p and hole currents becomes lower than the diffusion potential of the 1st layer 13, the peripheral p middle layer 15, and the n middle layer 14 (approximately 0.7 V at room temperature), Latch-up will not occur in normal on state. Furthermore, since the peripheral p-middle layer 15 is short-circuited to the emitter electrode 3 at the boundary between the very nearby regions (1) and (2), a small amount of holes are rapidly collected at the time of turn-off, so that the turn-off time is also shortened.

On the other hand, when the substrate region 11 is an n layer, the power MO3
It is an FET. To turn on the power MO3FET, a positive potential is applied to the collector electrode (drain electrode) 2, and then the first . A positive potential is applied to the second insulated gate electrodes 4 and 6.

As a result, an inversion layer is formed on the surface of the insulating film 5 of the first layer 13,
An electron current flows to the n-layer 14, the inversion layer, the n-layer 12, and the n-substrate region 11, and as a result, a current flows from the drain electrode 2 to the emitter electrode (source electrode) 3. This power M
To turn off the O3FET, the potential of the insulated gate electrode can be removed. As a result, the inversion layer disappears and the current is interrupted. By the way, power M
The O3FET has an n-substrate region 11, an n-layer 12.1 layer 1
3 (peripheral p-middle layer 15). Progress is also being made in using this as a feedback diode. In other words, power MO3
When a positive potential is applied to the source electrode 3 of the FET compared to the train electrode 2, current flows in the forward direction using this diode. At this time, from the 1st layer 13 and the p10 layer 14, the n- layer 1
2 Hehole ■ is injected. Next, at the moment when the potential of the source electrode 3 becomes negative compared to the potential of the drain electrode 2, this hole
is absorbed into the source electrode 3. In this case, the peripheral P middle layer 1
5 is short-circuited to the source electrode 3 in the vicinity of the peripheral p-layer 15, as shown in FIG. 6, the length of the peripheral p-layer 15, which acts as a resistance when holes are absorbed, becomes shorter, and the diode recovers quickly. At this time, the hole (2) current flows through the first layer 13 (peripheral p middle layer 15) below the n layer Jii 114 which is closest to the peripheral region (2).

[Problem to be solved by the invention]

” 2. In the conventional technology, IGBT and power MO3F
Although the structure is designed to reliably prevent the operation of the parasitic thyristor and parasitic transistor when the ET changes rapidly from the on state to the off state, there is a problem in that it is easily destroyed. In other words, the 9th layer below the nth layer 14 closest to the peripheral area ■
The p-n junction is forward biased by the resistance R2 of the layer 13 (peripheral p-middle layer 15), the injected hole current, and the discharge current of the p-n junction, and the p-substrate (n-substrate) 11, n-layer]2.9 layer 13 There was a problem that a parasitic thyristor (parasitic transistor) consisting of , n+J114 would operate.

An object of the present invention is to provide a structure in which a parasitic thyristor or a parasitic transistor does not operate while maintaining high-speed switching, especially turn-off, of an IGBT or a power MO5FEI.

[Means to solve the problem]

The characteristic structure of the semiconductor device of the present invention that achieves the above object is that the nine layers 13 are provided so as to be located on the outermost side of the nine layers 13 arranged in parallel and in contact with the peripheral nine layers 15; Nine layers 13 located on the side or one p layer inside] 1/1 are provided in the 3, and the contact point between the p 10 layers 3 and the second main electrode 3 is closer to the periphery 1 than the n+ layer. It is located in close proximity to the layer.

[Effect]

Because the contact points between the second main electrode 3 and the nine peripheral layers 15 and 13 are closer to the nine peripheral layers 15 than to the nearest nine layers, the Hall current and charging current accumulated around the substrate at turn-off. Since the transistor is quickly pulled out and the hall current and charging current do not operate parasitic transistors or transistors, a turn-off operation can be achieved at high speed and with high breakdown resistance.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing examples thereof.

FIG. 1 shows an embodiment of the semiconductor device of the present invention.
1 has a pair of main surfaces 101 and 102, and between the main surfaces,
p+ or n+ substrate region 1] adjacent to one main surface 101, substrate region 11 and n-512 having a lower impurity concentration than substrate region 1] adjacent to the other main surface 102; surface 102 to n
- The portion extending into the n-layer 12 and exposed to the other main surface "-02 has an elongated shape and has a higher impurity concentration than the n-layer 12, which is arranged in parallel in the longitudinal direction. p Fm −13, each 9 layers 13 from the other main surface 102
The portion extending inward and exposed to the other soil surface 102 is 9
It has an elongated shape with its longitudinal direction being the same as that of the layer 13, and has a higher impurity concentration than the 13th layer 13. The n-layer 14 extends deeper than the 9th layer 13 from the other main surface 102 into the n-layer 12, and has a plurality of layers. This is a semiconductor substrate on which a ring-shaped peripheral nine layer 15 is formed, which surrounds the nine layers 13 and is arranged in contact with the nine layers 13. Among the nine layers 13, the outermost nine layers 13 in the direction perpendicular to the longitudinal direction thereof have one n layer 14, and the other nine layers 13 have two n layers 14. Ten layers 14 are formed respectively. 2 is a first main electrode in ohmic contact with the substrate region 11 on one main surface 1.01 of the semiconductor substrate 1; 3 is the other main surface 10 of the semiconductor substrate 1;
2, the second main electrode is in ohmic contact with the n+ layer 14 and the p+ layer 3. This second main electrode 3 is connected to the peripheral nine layers 1 of the n ten layers 14 in the outermost nine layers 13.
On the 5 side, in the other p-layer 3, the exposed portion between the two n-layers 4 is in ohmic contact with the p-layer 3, respectively. Moreover, at both ends of the nine layers 13 in the longitudinal direction,
Extends to the peripheral side of the second earth dragon 1 Yu 3 or n 10th layer 14 p
It is in ohmic contact with WJ13. 4 is a semiconductor substrate.”
On the other main surface 102 of A second insulated gate electrode 6 is provided on the other main surface 102 of the semiconductor substrate 1 on the second peripheral layer 15 and along the first peripheral layer 5 on the other main surface 102 of the semiconductor substrate 1. , the second insulated gate electrode 4 and the electrode 6 to the second insulated gate 1 are electrically connected. 8 and 9 are insulating films formed on the electrodes 4 and 6 of the first and second insulating gates 1. The second main electrode 3 extends over the insulating film 8 and is connected to the adjacent second main electrode 3 .

According to such a semiconductor device, the outermost portion of the two elongated layers 13 arranged side by side in the longitudinal direction and in the direction perpendicular to the longitudinal direction is in contact with the second main electrode in the nine surrounding layers from the n-soil layer 14. 5, the holes injected into the r)-layer 2 adjacent to the peripheral pN 15 and the charge charged in the pn junction can be smoothly drawn out to the second main electrode 3 at turn-off, and Since there are no parasitic thyristors or parasitic 1-transistors in the stacking direction of the second layer 15, the IGBT or power MO5F has high speed and high breakdown resistance.
You can get ET. Also, the surrounding 9 layers" 5 is 2 layers 1
By increasing the impurity concentration higher than 3, it is possible to further improve the speed and breakdown resistance.

FIG. 2 shows another embodiment of the present invention. The first embodiment shown in FIG. ! 1.3 has a rectangular shape on the other main surface, and accordingly, the n+J 114 formed in the p layer 3 has a rectangular shape. In this embodiment as well, the n10 layers 1-4 formed within the two layers 13 that are on the outermost side of the juxtaposed p layers 3 and in contact with the nine peripheral layers 15 are connected to the second main electrode. 3 and pWJ
3.3 is located farther from the surrounding nine layers 15 than the point of contact with the third layer, and can produce the same effect as the embodiment shown in FIG.

FIG. 3 shows a further different embodiment of the present invention.
The embodiment shown in the figure is the second main electrode 3 and the second layer 13 on the outer circumferential side of the n-soil layer 14 located on the outermost circumferential side, and the two peripheral layers 1
The difference is that the contact area with 5 is increased. In the embodiment shown in FIG. 1, the contact area between the second main electrode 3 and the p layer 3 is approximately equal over the entire other main surface 1.02. For this reason, the contact resistance Rc between the second main electrode 3 and the second layer 13 on the outer periphery side of the n-soil layer 14 located on the outermost periphery side is large, and the voltage drop due to the Hall current and discharge current at turn-off becomes large, causing parasitic There is a risk that the thyristor or the parasitic transistor may operate. In this embodiment, the second main electrode 3 and the second layer 13 and the peripheral 9
Since the contact resistance Rc is reduced by increasing the contact area with the layer 15, the disadvantages that may occur in FIG. 1 can be eliminated. As a result of various experiments, it has been confirmed that it is desirable to keep the voltage drop at turn-off due to contact resistance Rc to 0.1 V or less. Further, according to this embodiment, since the contact resistance Rc is small, holes and charges injected into the n-layer 12 in the on state can be quickly extracted to the second main electrode 3, as shown in FIG. There is also the advantage that high-speed turn-off is possible compared to the embodiment. The second layer 13 and the n-soil layer 14 in the embodiment shown in FIG. 3 can be formed as shown in FIG. 1(b) and FIG. 2.

FIG. 4 shows another embodiment of the present invention, which differs from the embodiment shown in FIG. The difference is that n+li4 is formed in pJW13 on the inner side. In this embodiment as well, the contact point between the second main electrode 3 and the second layer 13 in the two layers 13 is configured to be closer to the nine surrounding layers 15 than to the n soil layer 14. According to this configuration, the n-soil layer 14 is separated from the contact point between the second main electrode 3 and the nearest P layer 3 and the surrounding pJF76 15, which mainly serve as a path for Hall current and charging current during turn-off. Because of this arrangement, parasitic thyristor or parasitic transistor effects can be more reliably eliminated compared to the embodiments shown in FIGS. 1 to 3.

pF! in this example. 13 and n10 layers 1-4 can be formed as shown in FIG. 1(b) and FIG. 2.

Although the following description has been given of typical embodiments of the present invention, the present invention is not limited thereto and can be modified in various ways.

〔Effect of the invention〕

According to the present invention, the accumulated charge of minority carriers and the pn
Since the charge in the junction can be quickly drawn out and the parasitic thyristor and parasitic 1 to 1-run cisister effects in the vicinity of the peripheral region can be prevented, it is possible to realize a semiconductor device that can perform a turn-off operation at high speed and with high breakdown resistance.

[Brief explanation of drawings]

2 is a schematic sectional view and a plan view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is a plan view showing a different embodiment of the present invention, and FIG. 3 is a schematic diagram showing a further different embodiment of the present invention. 4 is a schematic sectional view showing another embodiment of the present invention, FIG. 5 is a plan view of a conventional semiconductor device, and FIG. 6 is a schematic sectional view showing another embodiment of the present invention.
It is a cross-sectional view along the -■ line. ]...Semiconductor substrate, 2...-first main electrode, 3 second
main electrode, 4. first insulated gate electrode, 6. second insulated gate electrode, 11..substrate region, 12- n-layer, 9. Fig. 2 JP-A-12970 (7)

Claims (1)

[Claims] 1. A semiconductor substrate region of a first conductivity type or a second conductivity type having one main surface and having a first main electrode on this main surface; a first conductivity type first semiconductor region having the other main surface formed thereon; and a plurality of second conductivity type regions exposed on the other main surface and partially and regularly formed continuously. A second semiconductor region, a third semiconductor region of the first conductivity type formed in the second semiconductor region, and an insulating film formed on the other main surface where the first semiconductor region is exposed. from the third semiconductor region in one of the adjacent second semiconductor regions to the third semiconductor region in the other second semiconductor region.
a plurality of first insulated gate electrodes formed astride semiconductor regions; a fourth semiconductor region of the second conductivity type exposed on the other main surface formed deeper than the semiconductor region; a second insulated gate electrode electrically connected to the first insulated gate electrode; and a second main electrode in low resistance contact with the second semiconductor region and the third semiconductor region on the other main surface. However, the contact point between the second main electrode and the second semiconductor region in the second semiconductor region that is in contact with the fourth semiconductor region is closer to the fourth semiconductor region than the third semiconductor region. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the impurity concentration of the fourth semiconductor region is higher than that of the second semiconductor region. 3. Having a pair of main surfaces, a first semiconductor region having one conductivity type formed between the main surfaces and adjacent to the other main surface, and a region from the other main surface into the first semiconductor region. a plurality of second semiconductor regions having the other conductivity type, which are separated from each other by the first semiconductor region; a third semiconductor region having one conductivity type; a fourth semiconductor region having the other conductivity type formed in contact with a second semiconductor region; a first main electrode in ohmic contact with one main surface of the semiconductor substrate; the other main surface of the semiconductor substrate. a second main electrode in ohmic contact with the third semiconductor region and the second semiconductor region; on the other main surface of the semiconductor substrate, with an insulating film interposed therebetween;
a first insulated gate electrode provided to extend from a third semiconductor region formed in one of adjacent second semiconductor regions to a third semiconductor region formed in the other; On the other main surface, via an insulating film,
a second insulated gate electrode provided on the fourth semiconductor region along the fourth semiconductor region and electrically connected to the first insulated gate electrode; A semiconductor device characterized in that a contact point between the second main electrode and the second semiconductor region in the second semiconductor region is closer to the fourth semiconductor region than to the third semiconductor region. 4. A semiconductor device according to claim 3, characterized in that the semiconductor substrate has a semiconductor substrate region of one conductivity type adjacent to one main surface and having a higher impurity concentration than the first semiconductor region. . 5. A semiconductor device according to claim 3, wherein the semiconductor substrate has a semiconductor substrate region of the other conductivity type adjacent to one main surface and having a higher impurity concentration than the first semiconductor region. . 6. A semiconductor device according to claim 3, 4, or 5, wherein the fourth semiconductor region has a higher impurity concentration than the second semiconductor region.