JPS5933988B2 - Electrostatic induction thyristor - Google Patents

Description

[Detailed description of the invention] The present invention relates to a static induction thyristor.

In recent years, electrostatic induction thyristors have been put into practical use as thyristors with particularly excellent switching characteristics.

Its general structure is as shown in FIG. 1, where a P-type semiconductor layer 3 and an Nf-type semiconductor layer 3 and an Nf-type semiconductor layer are formed on the front and back surfaces of an N-type semiconductor layer 2 in which a lattice-like or mesh-like P-type semiconductor layer 1 is embedded, respectively. Layer 4 was formed. The P"4" type semiconductor layer 3 and the N'I' type semiconductor layer 4 are called an anode layer and a cathode layer, respectively, and an anode electrode 5 and a cathode electrode 6 are provided on their surfaces so that a current can flow between them. It is formed.

The P-type semiconductor layer 1 is called a gate layer, and when a negative voltage is applied to the cathode electrode 6, a depletion layer T is generated around the P-type semiconductor layer 1, and the anode electrode 5
, the current flowing between the power saw poles 6 is controlled. The voltage-current characteristics showing this state are as shown in the graph in Figure 2,
The vertical axis represents the current, and the horizontal axis represents the anode voltage. First, without applying a voltage to the P-type semiconductor layer 1, which is the gate layer, when a current is passed between the anode electrode 5 and the power source electrode 6, the curve A appears. D1 This has the same characteristics as a P+N-N+ type diode.

When a negative voltage is applied to the gate layer 1 with respect to the cathode electrode 6, a certain anode voltage V
Only a small amount of leakage current flows until it reaches BO, but if the voltage is higher than that, it exhibits negative resistance and becomes conductive. In the case of curve C, the voltage applied to the gate layer 1 is further increased. However, when the temperature of the electrostatic induction thyristor with such a structure increases at its junction, the blocking voltage VBO decreases and it switches at a small rate of voltage increase (Dv/Dt). This drawback made it unsuitable for single power control.

Therefore, the present inventor proposed an electrostatic induction thyristor that improved this drawback and filed an application earlier.

That is, as shown in FIG. 3, an N-type semiconductor layer 8 is formed on an N1-type semiconductor layer 2 in which a P-type semiconductor layer 1 serving as a gate layer is buried, and a lattice-shaped p+ type semiconductor is formed on this surface. layer 3
is formed by selective diffusion or the like, and an anode electrode 5 connected to both the N type semiconductor layer 8 and the P+ type semiconductor layer 3 is formed. Items with the same symbols as in Figure 1 are made of the same material and have the same functions. In addition to such a configuration, a voltage drop occurring in the lateral resistance (sheet resistance) of the N-type semiconductor layer 8 between the anode electrode 5 and the cathode electrode 6 is caused by the voltage drop occurring between the door-shaped semiconductor layer 3 and the N-type semiconductor layer 8. If a current that does not exceed the diffusion potential (0.6 to 0.9) at the junction with the N-type semiconductor layer 8, N-type semiconductor layer 2, and N+-type semiconductor layer 4 flows, This flow is controlled by a depletion layer arising from the P-type semiconductor layer 1 to which voltage is applied.

That is, it exhibits an operation similar to that of a field effect transistor FET in which the N-type semiconductor layer 8 is the drain layer, the P-type semiconductor layer 1 is the gate layer, and the N+-type semiconductor layer 4 is the source layer. As is well known, the withstand voltage of field effect transistors has little dependence on temperature. Then, when the current is increased and the voltage drop generated in the lateral resistance (sheet resistance) of the N-type semiconductor layer 8 exceeds the diffusion potential at the junction between the P+-type semiconductor layer 3 and the N-type semiconductor layer 8, P+
Since the junction between type semiconductor layer 3 and N type semiconductor layer 8 is biased in the forward direction, an operation exactly similar to that shown in FIG. 1 is performed. The shortcomings described above can be overcome by providing the operating characteristics of a field effect transistor FET while the b1 anode current is small (blocking state), and by providing the operating characteristics of a static induction thyristor when the current exceeds a certain value. It has been removed. Although the electrostatic induction thyristor having such a configuration has solved the conventional problems, it has the disadvantage that the voltage drop in the conductive state is several times higher than that of a general thyristor. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electrostatic induction thyristor whose breakdown voltage is less dependent on temperature and whose voltage drop in a conductive state is small.

In order to achieve this object, the present invention provides a structure in which P--
type semiconductor layer, an anode electrode formed by connecting the P~ type semiconductor layer and the N(P) type semiconductor layer, and the N(P) type semiconductor layer;
)-type semiconductor layer, and a P~-type semiconductor layer formed in a region between the cathode layer and the N(P)-type semiconductor layer except for the lower part of the gate layer. It is.

The present invention will be explained below using Examples. FIG. 4 is a sectional view showing an embodiment of the electrostatic induction thyristor according to the present invention.

In this figure, the same reference numerals as those in FIG. 3 are made of the same material and have the same function. A type semiconductor layer 9 is embedded therein. This P-type semiconductor layer 9 is disposed below the p+-type semiconductor layer 3, and the P-type semiconductor layer 1, which will become a gate layer, is provided on the region where the P-type semiconductor layer 9 is not formed. It is starting to be installed. The reason for doing this is to prevent a decrease in the current capacity and generation of leakage current that directly crosses the N-type semiconductor layer 8 and the N''-type semiconductor layer 2 from the anode electrode 5. In addition, when applying a slight positive voltage to the anode electrode 5, a negative voltage to the cando electrode 6, and a negative voltage to the P-type semiconductor layer 1 which is the gate layer with respect to the cathode 1 electrode 6, the voltage around the gate layer increases. A depletion layer is generated and a blocking state occurs.

When the cathode voltage is gradually increased, the potential of the depletion layer 1 is lowered due to the electrostatic induction phenomenon, so that a small amount of current flows between the anode electrode 5 and the cathode electrode 6. When this current is small, as explained in FIG. 3, the electrostatic induction thyristor exhibits the same characteristics as the field effect transistor FET regardless of the P-type semiconductor layer 9, so the temperature dependence of the electrostatic induction thyristor is There is little sex. As the potential of the depletion layer is lowered, the current from the first anode electrode 5 increases, and the voltage drop generated in the lateral resistance (sheet resistance) of the N-type semiconductor layer 8 is reduced between the P+ type semiconductor layer 3 and the N-type semiconductor layer 8. If the diffusion potential at the junction with the layer 8 is exceeded, the current will flow into the N-type semiconductor layer 8 through the p + -type semiconductor layer 3 .

The majority of this current is positive carriers (holes), which enter the depletion layer generated around the gate layer due to a diffusion phenomenon. Since an electric field is applied to this depletion layer in the direction of absorbing minority carriers (holes), the depletion layer further flows into the depletion layer, which further lowers the reverse voltage of the gate layer. The current from the anode electrode 5 increases and turns on. Next, these minority carriers (holes) enter the P-type semiconductor layer 3. This P-type semiconductor layer 9 is used as a base layer,
When considering a bipolar transistor in which the N+ type semiconductor layer 4 is an emitter layer, as is well known, the minority carriers (holes) flowing into the P type semiconductor layer 9 cause a large amount of electrons to be injected from the N+ type semiconductor layer 4. becomes. The holes then diffuse through the P-type semiconductor layer 9, enter the N1-type semiconductor layer 2 and the N-type semiconductor layer 8, and further induce hole injection from the P+-type semiconductor layer 3. Therefore, it has the same characteristics as a thyristor with a PNPN structure, and the voltage drop in the conductive state can be reduced. In this embodiment, an N-type semiconductor layer 8 is formed on the upper surface of the N1-type semiconductor layer 2, and a P+-type semiconductor layer 3 is formed on this surface.
Although the P+ type semiconductor layer 3 is selectively formed, the P+ type semiconductor layer 3 may be formed directly on the N1 type semiconductor layer 2. In this case, the same effect can be obtained if the distance between each p+ type semiconductor layer 3 is shortened and the layers are distributed densely. Furthermore, in this embodiment, the P-type semiconductor layer 1, which is the gate layer, has a lattice-like or mesh-like structure and is embedded in the N-type semiconductor layer 2, as shown in FIG. N
A lattice-like or mesh-like P-type semiconductor layer 1 is formed on the other surface of the ``''-type semiconductor layer 2 to become a gate layer, and an N+-type semiconductor layer 4 to become a cathode layer is formed in a region surrounded by these. In addition to the inductive thyristor, a P-type semiconductor layer 9 may be formed between the N+-type semiconductor layer 4 and the N1-type semiconductor layer 2.

Items with the same symbols as in Figure 4 are made of the same material and have the same functions. Of course, all the semiconductor layers described in this embodiment may be of opposite conductivity type.

As described above, according to the electrostatic induction thyristor according to the present invention, it is possible to obtain one in which the temperature dependence of the withstand voltage is small and the voltage drop in the conductive state is small.

[Brief explanation of drawings]

Figures 1 and 2 are explanatory diagrams and characteristic diagrams showing an example of a conventional electrostatic induction thyristor, Figure 3 is a sectional view showing another example of a conventional electrostatic induction thyristor, and Figure 4 is a cross-sectional diagram showing another example of a conventional electrostatic induction thyristor. The figure is a sectional view showing one embodiment of the electrostatic induction thyristor according to the invention, and FIG. 5 is a sectional view showing another embodiment of the electrostatic induction thyristor according to the invention. DESCRIPTION OF SYMBOLS 1...P type semiconductor layer (gate layer), 2...N type semiconductor layer, 3...P+ type semiconductor layer, 4...N+ type semiconductor layer, 5...Anode electrode, 6...・Cathode electrode,
7... Depletion layer, 8... N type semiconductor layer, 9... P type semiconductor layer.

Claims (1)

[Scope of Claims] 1. A P^+ (N^+) type semiconductor layer selectively formed on one surface of the N(P) type semiconductor layer including the gate layer, and the P^+ (N^+) an anode electrode formed by connecting an N(P) type semiconductor layer and an N(P) type semiconductor layer; a cathode layer formed on the other surface of the N(P) type semiconductor layer; A static induction thyristor comprising: a P(N) type semiconductor layer formed in a region of the ) type semiconductor layer excluding the lower part of the gate layer. 2 The N(P) type semiconductor layer is composed of a double layer of an N^-(P^-) type semiconductor layer and an N(P) type semiconductor layer, and has a P(N) type semiconductor layer.
2. The electrostatic induction thyristor according to claim 1, wherein the type semiconductor layer is formed on the surface of the N(P) type semiconductor layer. 3. The electrostatic induction thyristor according to claim 1, wherein a lattice-like or mesh-like gate layer is interposed in an N(P) type semiconductor layer. 4. The electrostatic induction thyristor according to claim 3, comprising a P(N) type semiconductor layer selectively formed under a region surrounded by a lattice-like or mesh-like gate layer. 5. The electrostatic induction thyristor according to claim 3, comprising a P^+ (N^+) type semiconductor layer selectively formed on a region surrounded by a grid-like or mesh-like gate layer. 6. The electrostatic induction thyristor according to claim 1, which has a gate layer formed in a lattice pattern on the back surface of the N(P) type semiconductor layer. 7. The electrostatic induction thyristor according to claim 6, wherein the cathode layer is formed in a region within the gate layer formed in a lattice shape. 8. The electrostatic induction thyristor according to claim 1, which has a cathode layer formed in a lattice pattern on the surface of the N(P) type semiconductor layer. 9. The electrostatic induction thyristor according to claim 8, wherein a gate layer is formed in a region within the cathode layer formed in a lattice shape.