JPH04102079A - Testing device and method of circuit board - Google Patents

Abstract

PURPOSE:To enable conduction and insulation tests to be performed between a fine-pitch electrode and a normal-pitch electrode by allowing one contact of a probe head for test to contact two or more fine-pitch electrodes of a test board simultaneously. CONSTITUTION:A head 11 and a board 17 are allowed to contact so that one of a plurality of contacts 11a of the probe head for test 11 contacts an electrode 17b of two or more fine-pitch PC1 of the test board 17 by a drive means 15 and a first contact means 12. Therefore, even if the electrode 17b is reduced as compared with a PC of a contact 11a, it need not be contacted individually. Also, a second contact means 13 allows a contact 11a to come into contact with an electrode 17c of a normal-pitch PC2 individually and a measuring means 14 measures electrical state of the board 17, thus enabling conduction test between the electrodes 17b and 17c to be performed. Further, the electrode 17b and a plurality of 11a are physically separated and insulation test viewed from the electrode 17c becomes possible. Namely, even if the electrode 17b is reduced as compared with the PC of the contact 11a, it is not necessary to enable each to be contacted, thus achieving conduction and insulation test between the electrodes 17b and 17c.

Description

[Detailed description of the invention] Overview Industrial field of application Conventional technology (Figs. 11 and 12) Problem to be solved by the invention (Fig. 13) Means for solving the problem (Parts 1 and 2) Figure) Working Examples (Figures 3 to 10) Effects of the Invention (Summary) Circuit board testing equipment, particularly continuity testing and testing of LSI double-sided mounting type circuit boards (hereinafter referred to as SMT boards) including intermediate wiring layers. Regarding the equipment and method for insulation testing, even if the pitch of the footprint of the SMT board becomes narrow, the contact method of the probe pins can be devised without relying on external appearance or visual inspection. A test probe head consisting of a plurality of contacts, and a first contact in which the plurality of contacts of the test probe head are brought into contact with micropitch electrodes of a substrate to be tested, for the purpose of conducting a continuity test and an insulation test. means, second contact means for bringing the plurality of contacts of the test probe head into contact with the normal pitch electrodes of the test board, and bringing the test probe head into contact with the normal pitch electrodes of the test board. second to let
a contacting means, a measuring means for measuring the electrical state of the board under test, a driving means for driving at least the first contacting means, and a control means for controlling input and output of the driving means and the measuring means. one contactor of the test probe head of the first contact means simultaneously contacts two or more micropitch electrodes of the substrate to be tested.

[Industrial application field]

The present invention relates to a circuit board testing device and a testing method thereof, and more specifically, to a device and an insulation test for a surface mount type circuit board (hereinafter referred to as an SMT board) including an intermediate wiring layer. It is about the method.

2. Description of the Related Art In recent years, LSIs (semiconductor integrated circuit devices) have become highly integrated and dense due to demands from users for downsizing and improving performance of electronic devices.

As a result, the number of external terminals is increasing and the terminal pinch interval is also becoming narrower.

By the way, the continuity test and insulation test of the SMT board is performed by LS
Probe pins for testing were individually brought into contact with via balls that connect the footprint on which the I was mounted by soldering, etc., and the front and back wiring patterns including the intermediate wiring layer, and the electrical resistance, etc. thereof, was measured.

However, as LSIs become more highly integrated and densely packed, the footprint pitch interval is becoming narrower in proportion to the reduction in the external terminal pitch.

For this reason, due to the manufacturing limitations of reducing the diameter of the probe pin, it is not possible to individually contact the probe pin to the footprint and measure the electrical resistance, etc., making it necessary to rely on visual inspection of the appearance of the SMT board. invite

This poses a problem in that it becomes difficult to conduct continuity tests and insulation tests on SMT boards that are becoming more highly integrated and densely packed.

Therefore, even if the pitch interval of the SMT board footprint becomes narrow, it is possible to devise a contact method of the probe bin and conduct continuity and insulation tests without relying on external appearance or visual inspection. A device and method that can do this is desired.

[Conventional technology] 11 to 13 are explanatory diagrams related to the conventional example.

FIG. 11 shows a configuration diagram of a conventional SMT board testing apparatus.

In the figure, a device for conducting a continuity test and an insulation test of an SMT board 7 supplies a test voltage or current to a footprint 7a for mounting an LSI on the board 7, and a plurality of devices that take in the resulting voltage or tl current. A test probe head 1 consisting of test probe pins IA, a jig 2 for aligning the probe head L with the test area of the substrate 7, and pin information of each probe pin IA and a measuring device 4. A connecting circuit 3 for matching, and a measuring device 4 for taking in the resulting voltage or current from the footprint 7a and measuring resistance, etc.
and a test data file 5 that stores the test data TD.
and a control section 6 that controls input/output of the test data TD, applied voltage or current VT, and probe information.

The purpose of this device is to prepare a wiring pattern 7c of a surface-mounted SMT board 7 including an intermediate wiring layer 7b as shown in the circle with broken lines as a pretreatment for mounting an LSI or the like on an SMT board 7 by soldering or the like. and the through hole leading to the intermediate pipe m1i7b (
It is used to inspect conduction defects such as via holes (hereinafter referred to as via holes) and insulation defects.

Further, a method of conducting a continuity test and an insulation test of the SMT board 7 using the device is shown in FIG. 12(a).

As shown in (b), first, the test probe pin IA of the almost same pitch PC formed in accordance with the pitch PC of the footprint 7a is aligned with the footprint 7a, and a test voltage is supplied thereto. . Further, the resulting voltage is taken in by the test probe pin IA, and each probe information PD is taken in to the measuring device 4 via the connection circuit 3, and its conduction resistance and insulation resistance are measured.

This makes it possible to conduct continuity tests and insulation tests on the SMT board.

[Problem to be solved by the invention]

By the way, according to the conventional example, when conducting a continuity test and an insulation test of the SMT board 7, the footprint 7a and the board 7 are
The test probe pins IA were individually brought into contact with the via holes connecting the front and back wiring patterns 7c, and the electrical resistance between them was measured. However, due to an increase in the number of external terminals due to higher integration and higher density of LSIs, the pitch PC of the footprint 7a tends to become narrower in proportion to the smaller pitch of the external terminals.

Therefore, as shown in FIG. 13, when the pitch PCx of the footprints 7a is made smaller than the pitch PC of the test probe pins IA, it becomes difficult to bring them into contact with each other individually. It is also conceivable to manufacture a test probe pin IA with a pin diameter that matches the pitch PCx of the fund blind 7a, but there is a limit to the manufacture of the probe pin IA due to measures taken to reduce the contact resistance. For this reason, it is not possible to individually measure electrical resistance etc. by contacting the probe pin IA with the footprint, and the SM
This results in a situation in which the appearance of the T-board 7 must be inspected only by visual inspection.

This makes it difficult to conduct continuity and insulation tests on the SMT substrate 7, which is becoming increasingly highly integrated and dense, resulting in a problem in that its reliability deteriorates.

The present invention was created in view of the problems of the conventional example, and even when the footprint of the SMT substrate becomes narrow, the probe pin can be fixed without relying on external appearance or visual inspection. The purpose of the present invention is to provide a circuit board testing device and a testing method that enable continuity and insulation testing of the circuit board by devising a contact method for the circuit board.

[Means to solve the problem]

FIG. 1 is a principle diagram of a circuit board testing device according to the present invention;
FIG. 2 each shows a principle diagram of the circuit board testing method according to the present invention.

As shown in FIG. 1, the device includes a plurality of contacts 11a.
A test probe head 11 consisting of a plurality of contacts 11a of the test probe head 11 is connected to a substrate under test 17.
a first contact means 12 for bringing a small pinch Pc10 into contact with the scraper 17b, and a plurality of contacts 11a of the pad 11 for the test probe at the normal pitch PC2 of the board under test 17.
a second contacting means 13 for contacting the electrode 17c, a measuring means 14 for measuring the electrical state of the substrate under test 17, a driving means 15 for driving at least the first contacting means 12, and a driving means 15 for driving the first contacting means 12; means 15 and a control means 16 for controlling the input and output of the measuring means 14, one contactor 1 of the test probe head 11 of the first contacting means 12;
1a is two or more fine pitch PCs of the board under test 17;
The method is characterized by simultaneously contacting the electrodes 17b of the test substrate 17 as shown in FIG. 2(a).
This is a method of conducting a continuity test and an insulation test between a plurality of wiring electrodes 17a in which electrodes 17b of fine pitch PCI and electrodes 17c of normal pitch PC2 are wire-connected.
), in advance, step P1
In step P2, the continuity/insulation test mode is determined, and in the case of continuity test mode, in step P2, short-circuiting is performed to simultaneously contact the electrode 17b of the fine pitch PCI and the adjacent electrode 17b of the fine pitch Pct, and then Then, in step P3, conduction test processing is performed on the board under test 17 based on the short circuit processing, and in the case of insulation test mode, in step P4, an open processing is performed to electrically open between the electrodes 17b of the fine pitch PCI. Then, in step P5, an insulation test process is performed on the board under test 17 based on the opening process, thereby achieving the above object.

[For production]

According to the device of the invention, a test probe head 11, a first contact means 12. Second contact means 13 measuring means 14.
A driving means 15 and a control means 16 are provided, and the first contact means 12 simultaneously contacts one contactor 11a of the test probe head 11 with two or more electrodes 17b of the substrate to be tested 17 at a minute pitch Pct. has been done.

For example, first, the drive means 15 or other drive means and the first contact means 12 are used to control the fine pitch PC of the substrate under test 17.
A plurality of contacts 11a of the RAD 11 are aligned and brought into contact with the electrode 17b of the test probe. At this time,
One contact 11a of the probe head 11 simultaneously contacts two or more micropitch PCI electrodes 17b.

Therefore, the minute pinch PCI electrode 1 of the board under test 17
Even if the pitch 7b is smaller than the pitch PC of the contact 11a of the test probe 11, there is no need to contact them individually, and the second contact means 13 makes it possible to 17 normal pitch PC2 electrodes 17c
The contacts 11a of the test probes 11 are individually brought into contact with each other.

Next, the electrical state of the test board 17 is measured by the measuring means 14 . This makes it possible to conduct a continuity test between the electrode 17b of the micro-pinch PCI and the electrode 17c of the normal pitch PC2.

Further, the other driving means are left as they are, and only the driving means 15 is operated to control the minute pitch PC of the test board 17.
The electrode 17b of I and the plurality of contacts 11a of the test probe head 11 are physically separated.

As a result, tl of the normal pitch PC2 of the board under test 17
It becomes possible to perform an insulation test as seen from 17c.

This makes it possible to accurately and reproducibly test conduction defects and insulation defects in intermediate wiring layers and wiring patterns of the test substrate 17, such as SMT substrates, which are becoming increasingly highly integrated and dense. Become.

According to the method of the present invention, as shown in the flowchart of FIG. 2(c), the continuity/insulation test mode is determined in advance in step P1, and in the case of continuity test mode, step P2. In step P3, conduction test processing is performed on the board under test 17 based on the short circuit processing, and in the case of insulation test mode in step Pi, step P4. At P5, an insulation test process is performed on the board under test 17 based on the open process.

For this reason, even if the number of external terminals increases with the increase in integration and density of LSI, and the external terminal pinch is also reduced and the electrodes 17b of fine pitch PCI are increasingly integrated, the SMT substrate It becomes possible to perform continuity and insulation tests with good reliability on the board 17 to be tested, without relying solely on visual inspection of the external appearance of the board 17 to be tested.

This reduces inspection omissions and the like, making it possible to suppress as much as possible electrical failures caused by the board 17 after the LSI is mounted.

(Example) Next, an example of the present invention will be described with reference to the drawings.

3 to 5 are diagrams for explaining a circuit board testing device and its testing method according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of an SMT board testing device according to an embodiment of the present invention. It shows.

In the figure, 21A and 21B are rad 1 to the test probe.
A probe pin for a micro footprint (hereinafter referred to as a probe pin for a micro FP) and a probe pin for a normal pitch, which are an example of Embodiment 1, and are brought into contact with the electrode 27a of the SMT board 27, which is an example of the board 17 under test. It is something.

That is, the probe pin 21A for micro FP contacts the electrode 27b (footprint) of the micro pitch PCI of the SMT board 27, and the probe pin 21B for normal pitch contacts the electrode 27c of the normal pitch PC2. It is something that will be done. In addition, probe bottle 2 for micro FP
As shown in FIG. 10, the main parts of the structure of 1A are a tip portion in which a notch is formed and a spring that presses the tip portion against the electrode 27a.

A first contact jig 22 is an embodiment of the first contact means 12, and is used to hold and fix a plurality of micro FP probe bins 21A. Note that the first contact jig 22 has a Z
The second contact jig 23 is independently moved up and down (in the ±Z force direction) by the direction drive device 25. Also, one micro FP probe pin 21A is connected to the SMT substrate 2.
Two or more electrodes 27b of micropitch PCI of 7 are brought into contact at the same time.

23 is a second contact jig which is an example of the second contact means 13, and includes a plurality of probe bins 21B for normal pitches.
This is to hold and fix. Note that the second contact jig 22
is attached to the main body of the jig.

24A to 24C are a connection circuit [A], a connection circuit (B), and a measurement processing circuit which are one embodiment of the measurement means 14;
This is to measure the electrical state of the MT board 27. That is, the connection circuit (A) 24A and the circuit (B) 24B are as follows.
The pin information of the probe pin 21A for micro FP and the probe pin 21B for normal pitch is transferred to the connectors 241 and 242.
The data is taken in through the measurement processing circuit 24C and matched with the measurement processing circuit 24C. The measurement processing circuit 24C also includes a constant current source,
Voltage source and voltage.

It consists of a current measuring device and the like, and measures the circuit state from the voltage applied to the electrode 27b of the SMT substrate 27 and the current flowing therein during a continuity/insulation test.

Regarding the internal configuration of the connection circuits (A) and CB),
This will be explained in detail in FIG.

Reference numeral 25 denotes a Z-direction drive device 2 which is an embodiment of the drive means 15.
5, which moves the first contact jig 22 independently up and down (in the ±Z force direction.In addition, during the continuity test,
- Move in two directions to connect the plurality of micro FP probe pins 21A to the micro pinch PCI voltage ff of the SMT board 27.
127b, and during an insulation test, move in the +Z force direction to connect multiple micro FP probe bins 21A and 5MTi.
This is to release the contact state of the plate 27 with the electrode 27b at the minute pitch Pct.

26 is a control device which is an example of the control means 16;
First contact jig 22. For example, the control device 'ff26 controls the input/output of the measurement processing circuit 24C, etc., outputs the test control signal S1 to the measurement processing circuit 24C based on the test data TD from the test data file,
It outputs a drive control signal S2 to the Z direction drive device 25. Further, data is transferred to a display device or an analysis device (not shown) based on the test result data from the measurement processing circuit 24C.

27 is an SMT board which is an example of the board under test 17;
As shown in the concave area inside the broken line in the same figure, the electrode (footprint) 2 of a micropitch PCI on which an LSI is mounted by soldering, etc.
7b and electrodes (via holes, etc.) 27c with a normal pitch PC2 that connect the front and back wiring patterns including the intermediate wiring layer are formed. Note that the electrode 27b of the SMT substrate 27 has a fine pitch Pct and the electrode 27c has a normal pitch PC2.
For example, α-a, b-β, 7-c, d-6. e
-e.

Conduction resistance such as f-ζ and the electrode 27C of the normal pitch PC2
Insulation resistance 9, for example, α-β, γ-δ, ε-ζ, etc., as viewed from above is measured.

In addition, 28 is a test unit for the back surface of the SMT board 2.
This unit tests the continuity/insulation of the electrode 27a formed on the back surface of 7. The test unit 28 is almost the same as the test unit on the front side, so a description thereof will be omitted.

Thereby, a continuity test and an insulation test can be performed on the surface-mounted SMT board 27 including the intermediate wiring layer.

FIG. 4 shows a connection circuit [A] according to an embodiment of the present invention.

(B), and FIGS. 5 to 8 show equivalent circuit diagrams during a continuity/insulation test.

That is, FIG. 4 is a configuration diagram showing a connection circuit related to the micro FP probe pin 21A, and in the figure, the connection circuit consists of a pin selection circuit.

The pin selection circuit is made up of switching elements 5WI-3W5 such as relays and MOS transistors, and is controlled by the switch selection signal SS from the control device 26 to select the electrode 27b (short between a and b) with a minute pitch Pct or the electrode 27C with a normal pitch PC2. It selectively outputs pin information such as [α, β].

FIG. 5 is an equivalent circuit diagram during a batch (between α and β) continuity test according to an embodiment of the present invention.

In the figure, when performing a batch continuity test between α and β of electrodes 27c with normal pitch PC2, probe pin 21A for micro FP is connected to electrodes 27b with micro pitch Pct = (a, b).
contact at the same time. Also, the switching element SW3 of the pin selection circuit. Turn Sn4 "ON" and switch the switching elements SWI, Sga2. Sn2. A switch selection signal SS having a content to turn Sn2 rOFFJ is supplied from the control device 26.

As a result, the fine pitch PCI electrode 27b-(ab)
It is possible to perform a batch continuity test between electrodes (via holes, etc.) 27C=α and β with a normal pitch PC2 connecting the front and back wiring patterns including the intermediate wiring layer and the front and back wiring patterns including the intermediate wiring layer.

FIG. 6 is an equivalent circuit diagram during an individual continuity test (between α and a) according to an embodiment of the present invention.

In the figure, when conducting a continuity test between the electrode 27c-α of normal pitch PC2 and the electrode 27b=a of fine pitch PCI, the probe pin 21A for fine FP is connected to the fine pitch PCI.
Switching element SW2 of the pin selection circuit is in contact with electrode 27b=(a, b) of pin selection circuit SW2.I. S-4 is [
Turn on the switching element SWI, Sen3SW5
．． A switch selection signal SS having a content that causes Sn2 to turn rOFFJ is supplied from the control device 26.

As a result, the normal pitch P connecting the electrode 27b=a of the micro-pinch PCI and the front and back wiring patterns including the intermediate wiring layer
A continuity test can be performed between the electrodes 27c and α of C2.

FIG. 7 is an equivalent circuit diagram during an individual continuity test (between β and b) according to an embodiment of the present invention.

In the figure, when conducting a continuity test between the electrode 27C=β of normal pitch PC2 and the electrode 27b=b of micropitch PCI, the probe bin 21A for microFP is connected to the micropitch PCI.
Switching element SW2 of the pin selection circuit is in contact with electrode 27b-(a, b) of pin selection circuit SW2.I. rON the same
, switching element SWI, 5W3SW4.
A switch selection signal SS is supplied from the control device 26 to turn Sn2 rOFF.

As a result, the normal pitch P connecting the fine pitch PCI electrode 27b=b and the front and back wiring patterns including the intermediate wiring layer
A continuity test can be performed between the electrode 27C=β of C2.

FIG. 8 is an equivalent circuit diagram during an insulation (between α and β) test according to an embodiment of the present invention.

In the figure, when performing an insulation test between α and β of the electrode 27c with the normal pitch PC2, the micro FP probe pin 2
1A micropitch PCI electrode 27b=(a.

(b) and be physically separated from the person in a non-contact state. Also, the switching element SW3 of the pin selection circuit. 3W4wo “ON”
”, switching elements SWI, Sn2. S
n2. A switch selection signal SS having a content to turn Sn2 rOFFJ is supplied from the control device 26.

As a result, the electrode (via hole etc.) 27c of the normal pinch PC2 that connects the front and back wiring patterns including the intermediate wiring layer
= Can perform insulation test between α and β.

In this way, according to an apparatus according to an embodiment of the invention,
Micro FP probe pin 21Δ1, normal pitch probe pin 21B, first contact jig 22. Second contact jig 23
．． Connection circuit (A) 24A, connection circuit (B) 24B, measurement processing circuit 24C, Z direction drive device 25, and control device 26
A first contact jig 22 is provided to simultaneously bring the micro FP probe pins 21A into contact with two or more electrodes 27b of the micro pinch Pct of the SMT substrate 27.

For example, first, a plurality of micro FP probe pins 21A are aligned and brought into contact with the micro pitch PCI electrodes 27b of the SMT board 27 by the Z direction drive device 25 or other drive means and the first contact jig 22. be done. At this time, one of the probes 21A simultaneously detects two or more minute pitches Pc.
t contacts the electrode 27b.

For this reason, the electrodes 2 of the SMT substrate 27 have a fine pitch Pct.
Even if the probe pins 7b are smaller than the pitch PC of the micro FP probe pins 21A, there is no need to contact them individually. In addition, the second contact jig 23 allows the SMT
The normal pitch probe pin 21B is similarly brought into contact with the electrode 27c of the normal pitch PC2 on the substrate 27.

Next, connection circuit (A) 24A, connection circuit CB) 24B
The electrical state of the SMT board 27 is measured by the measurement processing circuit 24C. This makes it possible to perform a continuity test between the electrode 27b of the micropitch PCI and the electrode 270 of the normal pinch PC2.

Further, the other driving means are left as they are, and only the Z direction driving device 25 is operated to move the fine pitch PCI electrode 27b of the SMT board 27 and the fine pitch PCI electrode 27.
b are physically separated from the plurality of micro FP probe bins 21A. This makes it possible to perform an insulation test viewed from the electrodes 27c of the normal pitch PC2 of the SMT board 27.

This makes it possible to accurately and reproducibly inspect conduction defects, insulation defects, etc. in intermediate wiring layers and wiring patterns of SMT substrates that are becoming increasingly highly integrated and densely packed.

Next, a method for testing an SMT board according to an embodiment of the present invention will be explained while supplementing the operation of the apparatus.

FIG. 9 is a flowchart of a method for testing an SMT board according to an embodiment of the present invention, and FIG. .

In FIG. 9, the fine pitch PCI electrode 27b of the SMT substrate 27 as shown in FIG. 10(a) and the normal pitch P
When carrying out a continuity test and an insulation test between a plurality of electrodes 27a to which the electrodes 27c of C2, PC3, PC4, etc. are wire-connected, first, in step P1, the SMT board 27 is positioned. At this time, the front surface test unit, the SMT substrate 27, and the back surface test unit 28 as described in the first embodiment are aligned.

Next, in step P2, the first . Second contact jig 22.2
Perform the positioning process in step 3. At this time, multiple micro FPs
The first contact jig 22 in which the probe bin 21A is held and fixed is connected to the electrode 27 of the SMT substrate 27 at a minute pitch Pct.
b. Similarly, a second contact jig 2 holds and fixes a plurality of normal pitch probe pins 21B.
3 is aligned with 1 cold 27C of the normal pitch PC2 of the SMT board 27.

Furthermore, in step P3, the plurality of electrodes 2 of the SMT substrate 27
7a and the micro FP probe pin 21A and the normal pinch probe bottle 21B are brought into contact. At this time, as shown in FIGS. 10(b) and 10(c), the micro FP probe pin 21A is contacted by the Z direction drive device 25. For example, if the electrode 27b of the micro pinch Pct is set to a,
c and d, e and f... are probe pins 2 for micro FP
1A, respectively.

Note that the normal pitch probe pin 21B is brought into contact with another driving means.

Thereafter, in step P4, the continuity/insulation test mode is determined. At this time, in the case of the continuity test mode (YES), a batch continuity test is performed between the electrodes (hereinafter referred to as lands α, β, γ, δ, ε, ζ, etc.) 270 of the normal pitch PC2 in step P5. At this time, one of the micro FP probe pins 21A is the t pole 27b of the micro pitch PCI = (a
, b:l are contacted at the same time. Also, the switching element SW3 of the pin selection circuit. 5114 is rONJ L
, switching elements SWl, SW2. SW5.
By turning SW6 OFF, the electrode 27c-α (via hole, etc.) of normal pitch PC2 connects the fine pitch PCI electrode 27b=(a, b) and the front and back wiring patterns including the intermediate wiring layer.

It is possible to conduct a continuity test between 3 at once (see Figure 5).
.

Next, in step P6, it is determined whether there is an abnormality between lands α, β, T, δε, and ζ. At this time, lands α, β, γ
, δ, ε, and ζ (YF!S), the process moves to step P7, and if there is no abnormality (No), the process returns to step P4.

Here, if there is an abnormality between the lands α and β, then in step P7 the fine pitch PCI electrodes 27b-(a, b
) and the electrode 27c-α of normal pitch PC2. At this time, probe pin 2 for micro FP
1A is connected to the fine pitch PCI electrode 27b= (a,
b), the switching elements SW2. Sn4 is turned on, switching element 5lft, Sn2. 5j15. Sn6 is rO
By performing FFJ, the fine pitch PCI electrode 27
A continuity test can be performed between the electrodes 27C=α of the normal pitch PC2 connecting the front and back wiring patterns including b-a and the intermediate wiring layer (see FIG. 6).

After that, in step P8, the fine pitch PCI electrode 27b is
A second individual continuity test is performed between = (a, b) and the electrode 27c=β of normal pitch PC2. At this time, one of the micro FP probe pins 21A is connected to the electrode 2 of the micro pitch PCI.
7b=(a,b), the switching element SW2. of the pin selection circuit is in contact with (a, b). 5146 is rON, L,
, switching element SWI, Sn2. By rOFFJ of Sn4゜Sn2, minute pitch Pct
It is possible to conduct a continuity test between the electrodes 27b-b and the electrodes 27c-8 of normal pitch PC2 which connect the front and back wiring patterns including the intermediate wiring layer (see FIG. 7).

Also, in step P6, lands α, β, T, and δ are set.

If there is no abnormality between ε and ζ (NO), step P4
Returning to , the process moves to the case of insulation test mode (No).

Therefore, in step P9, the first contact jig 22 is operated to perform Jl-contact processing of the micro FP probe pin 21A. At this time, the first contact jig 22 is connected to the Z direction drive device 25.
Therefore, the second contact jig 23 is independently upward (+2 direction).
direction. As a result, the plurality of micro FP probe pins 21A are physically separated from the micro pitch PCI electrodes 27b of the SMT board 27, and each micro pitch PCI
The electrodes 27b=ab, c, d, e, f, . . . are in an electrically open state.

After that, the land α- of the normal pinch PC2 at the step pH is
Perform insulation test processing from β, γ-δ, and ε-ζ. From this point on, measurements of insulation resistance and the like are performed in the same way as in the conventional example.

In this way, according to the SMT board testing method according to the embodiment of the present invention, as shown in the flowchart of FIG. 9, the conduction/I! The edge test mode is determined, and if it is the continuity test mode, steps P5~
At P8, a batch continuity test is performed on the SMT board 27 based on the short circuit treatment and the first. Perform the second individual continuity test process and step P
4, if the IP and edge test mode is selected, step P9. P
The insulation test processing of the SMT board 27 is performed based on the open processing at IO.

For this reason, even if the number of external terminals increases with the increase in integration and density of LSI, and the pitch of the external terminals is also reduced, and the electrodes 27a of micropitch PCI are increasingly integrated, the SMT substrate It becomes possible to perform a continuity test and an insulation test of the board 27 with good reliability without relying on inspection only by visual inspection of the appearance of the board 27.

This reduces inspection omissions and the like, making it possible to suppress as much as possible electrical failures caused by the board 27 after the LSI is mounted.

[Effects of the Invention] As explained above, the apparatus of the present invention is equipped with a test probe head, a first contact means, a second contact means, a measuring means, a driving means, and a control means. One contact of the test probe end of the contact means is simultaneously contacted with two or more micro-pinch electrodes of the substrate to be tested.

Therefore, even if the micropitch electrodes on the board under test are smaller than the pitch of the contactors on the test probe head, there is no need to make contact with each individual. This makes it possible to perform continuity and insulation tests between electrodes with a normal pitch and electrodes with a normal pitch.

Further, according to the method of the present invention, continuity test processing can be performed in the continuity/insulation test mode based on short circuit processing in which two or more micropinch electrodes are contacted at the same time.

Because of the second reason, the number of external terminals increases as LSIs become highly integrated and dense, and even if the external terminal pitch is reduced and electrodes with minute pitches are increasingly integrated, SMT substrates, etc. Appearance of the board under test.

It becomes possible to conduct a highly reliable continuity test and insulation test of the board without relying on visual inspection alone.

This makes it possible to accurately and reproducibly inspect conduction defects, insulation defects, etc. of intermediate wiring layers, wiring patterns, and the like. This reduces inspection omissions, etc.
This greatly contributes to improving the reliability of the test equipment.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of a circuit board testing device according to the present invention, Fig. 2 is a principle diagram of a circuit board testing method according to the present invention, and Fig. 3 is an SMT board according to an embodiment of the present invention. FIG. 4 is a configuration diagram of a connection circuit according to an embodiment of the present invention, and FIG. 5 is an equivalent circuit during a batch (α-β) continuity test according to an embodiment of the present invention. , Fig. 6 is an equivalent circuit during an individual (between α and 8) continuity test according to an embodiment of the present invention, and Fig. 7 is an equivalent circuit during an individual (between β and 5) continuity test according to an embodiment of the present invention. Equivalent circuit, FIG. 8 is an equivalent circuit diagram during an insulation (α-β) test according to an embodiment of the present invention, FIG. 9 is a flowchart of a U test method for an SMT board according to an embodiment of the present invention, FIG. 10 is an explanatory diagram of the contact method of a micro FP probe bin according to an embodiment of the present invention, FIG. 11 is a configuration diagram of a conventional SMT board testing apparatus, and FIG. Supplementary explanatory diagram of the SMT board testing method, FIG. 13 is a contact state diagram of test probe pins illustrating problems related to the conventional example. (Explanation of symbols) 11... Test probe head, 12... First contact means, 13... Second contact means, 14... Measuring means, 15... Driving means, 16. ...control means, 11a...contact, 17b...micro pitch electrode, 17c...normal pitch t-shape, PCI...micro pitch, PC2...normal pitch.

Claims (2)

[Claims] (1) A test probe head (11) consisting of a plurality of contacts (11a), and the test probe head (11)
a first contact means (12) for bringing a plurality of contactors (11a) into contact with electrodes (17b) of a fine pitch (PC1) of a substrate under test (17);
) to the board under test (17).
a second contact means (13) for contacting the electrodes (17c) with a normal pitch (PC2) of drive means (1) for driving the contact means (12) of
5), and a control means (16) for controlling input and output of the driving means (15) and the measuring means (14), and a test probe head (12) of the first contact means (12).
One contact (11a) of the substrate under test (11)
7) Two or more fine pitch (PC1) electrodes (17b
) A circuit board testing device characterized by simultaneously contacting the circuit board. (2) Micropitch (PC1) electrode (17b) and normal pitch (PC2) electrode (17c) of the board under test (17)
A method of conducting a continuity test and an insulation test between a plurality of wiring electrodes (17a) connected to each other by wiring, the electrode (17b) having the fine pitch (PC1) and the adjacent fine pitch (P
A short-circuiting process is performed to simultaneously contact the electrode (17b) of C1), a continuity test process is performed on the board to be tested (17) based on the short-circuiting process, and the electrode (17b) of the fine pitch (PC1) is subjected to a continuity test process. A method for testing a circuit board, characterized in that an opening process is performed to electrically open the gap, and an insulation test process is performed on the board under test (17) based on the opening process.