JPH0394699U - - Google Patents
Info
- Publication number
- JPH0394699U JPH0394699U JP173990U JP173990U JPH0394699U JP H0394699 U JPH0394699 U JP H0394699U JP 173990 U JP173990 U JP 173990U JP 173990 U JP173990 U JP 173990U JP H0394699 U JPH0394699 U JP H0394699U
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- transistor
- enable input
- final stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003213 activating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
Description
第１図は本考案の第１の実施例の出力回路を示
すブロツク図、第２図は第１図の回路の動作を示
すタイミング図、第３図は本考案の第２の実施例
の出力回路を示すブロツク図、第４図は従来の出
力回路を示すブロツク図、第５図は第４図の回路
の動作を示すタイミング図である。
１，１１，２３……センス・アンプ、２，５，
１２，１５，２４，２９……インバータ、２１，
２２……デイレイ用インバータ、３，８，１３，
１８，２５，４６……２入力ＮＯＲゲート、４，
１４，２６……２入力ＮＡＮＤゲート、６，１６
，２８……Ｐ型最終段トランジスタ・ドライバー
用インバータ、７，１７，２９……Ｎ型最終段ト
ランジスタ・ドイラバー用インバータ、９，１９
，３０……Ｐ型最終段トランジスタ、１０，２０
，３１……Ｎ型最終段トランジスタ、５０……出
力端子。
Fig. 1 is a block diagram showing the output circuit of the first embodiment of the present invention, Fig. 2 is a timing diagram showing the operation of the circuit of Fig. 1, and Fig. 3 is the output of the second embodiment of the invention. FIG. 4 is a block diagram showing a conventional output circuit, and FIG. 5 is a timing diagram showing the operation of the circuit shown in FIG. 4. 1, 11, 23... sense amplifier, 2, 5,
12, 15, 24, 29...Inverter, 21,
22...Delay inverter, 3, 8, 13,
18, 25, 46...2 input NOR gate, 4,
14, 26...2 input NAND gate, 6, 16
, 28... Inverter for P-type final stage transistor driver, 7, 17, 29... Inverter for N-type final stage transistor driver, 9, 19
, 30... P-type final stage transistor, 10, 20
, 31... N-type final stage transistor, 50... output terminal.
Claims (1)
記トランジスタをドライブする出力ドライバと、
前記出力ドライバの制御を行うバツフアとを備え
た出力回路において、外部からのアウト・プツト
・イネーブル入力信号によつてデバイス内部で発
生するアウト・プツト・イネーブル入力信号と、
センス・アンプをアクテイブにする信号との論理
積から得られる信号を、前記バツフアのアクテイ
ブ信号入力とすることを特徴とする出力回路。 a final stage output transistor that outputs to the outside; an output driver that drives the transistor;
an output enable input signal generated within the device in response to an external output enable input signal;
An output circuit characterized in that a signal obtained from a logical product with a signal for activating a sense amplifier is used as an active signal input of the buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP173990U JPH0394699U (en) | 1990-01-12 | 1990-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP173990U JPH0394699U (en) | 1990-01-12 | 1990-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0394699U true JPH0394699U (en) | 1991-09-26 |
Family
ID=31505634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP173990U Pending JPH0394699U (en) | 1990-01-12 | 1990-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0394699U (en) |
-
1990
- 1990-01-12 JP JP173990U patent/JPH0394699U/ja active Pending
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