JPH0378347U - - Google Patents
Info
- Publication number
- JPH0378347U JPH0378347U JP13873689U JP13873689U JPH0378347U JP H0378347 U JPH0378347 U JP H0378347U JP 13873689 U JP13873689 U JP 13873689U JP 13873689 U JP13873689 U JP 13873689U JP H0378347 U JPH0378347 U JP H0378347U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- parity
- memory
- error signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は動作の一例を示すタイムチヤート、
第３図は従来のこの種の装置の構成概念図である
。
１…マイクロプロセツサ、２１〜２ｎ…メモリ
ブロツク、３１〜３ｎ…パリテイチエツク回路、
４…アクセス制御回路、５１〜５ｎ…バツフア、
６…エラー信号管理回路、ＢＳ…内部バス。
Fig. 1 is a configuration block diagram showing one embodiment of the present invention, Fig. 2 is a time chart showing an example of operation,
FIG. 3 is a conceptual diagram of a conventional device of this type. 1... Microprocessor, 21-2n... Memory block, 31-3n... Parity check circuit,
4...Access control circuit, 51-5n...Buffer,
6...Error signal management circuit, BS...Internal bus.
Claims (1)
アクセス制御回路と、 前記マイクロプロセツサがアクセスするメモリ
であつて、小ブロツクに分割され各メモリブロツ
ク毎にバツフア及びバスを介してマイクロプロセ
ツサに接続されるパリテイビツト付のメモリと、 前記メモリブロツク毎に設けられ対応するメモ
リとバツフアの間のデータをモニターし、パリテ
イをチエツクするパリテイチエツク回路と、 これらのパリテイチエツク回路からのパリテイ
エラー信号を受け、前記アクセス制御回路に現サ
イクルエラー信号を伝えるか、前記マイクロプロ
セツサに割込みとして伝えるかの判断を行うエラ
ー信号管理回路とを備えたマイクロプロセツサ装
置。[Claims for Utility Model Registration] A microprocessor, an access control circuit for controlling access of the microprocessor, and a memory accessed by the microprocessor which is divided into small blocks and has a buffer for each memory block. and a memory with a parity bit connected to the microprocessor via a bus; a parity check circuit provided for each memory block to monitor data between the corresponding memory and the buffer and check parity; and an error signal management circuit that receives a parity error signal from a parity check circuit and determines whether to transmit the current cycle error signal to the access control circuit or to the microprocessor as an interrupt. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13873689U JPH0378347U (en) | 1989-11-30 | 1989-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13873689U JPH0378347U (en) | 1989-11-30 | 1989-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0378347U true JPH0378347U (en) | 1991-08-08 |
Family
ID=31685817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13873689U Pending JPH0378347U (en) | 1989-11-30 | 1989-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378347U (en) |
-
1989
- 1989-11-30 JP JP13873689U patent/JPH0378347U/ja active Pending
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