JPH0377689B2 - - Google Patents

Info

Publication number
JPH0377689B2
JPH0377689B2 JP56190254A JP19025481A JPH0377689B2 JP H0377689 B2 JPH0377689 B2 JP H0377689B2 JP 56190254 A JP56190254 A JP 56190254A JP 19025481 A JP19025481 A JP 19025481A JP H0377689 B2 JPH0377689 B2 JP H0377689B2
Authority
JP
Japan
Prior art keywords
channel
input
circuit
output buffer
channel mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56190254A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5892141A (ja
Inventor
Kunimitsu Fujiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56190254A priority Critical patent/JPS5892141A/ja
Publication of JPS5892141A publication Critical patent/JPS5892141A/ja
Publication of JPH0377689B2 publication Critical patent/JPH0377689B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
JP56190254A 1981-11-26 1981-11-26 集積回路装置 Granted JPS5892141A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190254A JPS5892141A (ja) 1981-11-26 1981-11-26 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190254A JPS5892141A (ja) 1981-11-26 1981-11-26 集積回路装置

Publications (2)

Publication Number Publication Date
JPS5892141A JPS5892141A (ja) 1983-06-01
JPH0377689B2 true JPH0377689B2 (ko) 1991-12-11

Family

ID=16255072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190254A Granted JPS5892141A (ja) 1981-11-26 1981-11-26 集積回路装置

Country Status (1)

Country Link
JP (1) JPS5892141A (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60244123A (ja) * 1984-05-18 1985-12-04 Fujitsu Ltd Ｃｍｏｓマスタスライス半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49125066A (ko) * 1973-01-27 1974-11-29

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556134Y2 (ko) * 1971-12-14 1980-02-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49125066A (ko) * 1973-01-27 1974-11-29

Also Published As

Publication number Publication date
JPS5892141A (ja) 1983-06-01

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