JPH0377461U - - Google Patents

Info

Publication number
JPH0377461U
JPH0377461U JP1989138376U JP13837689U JPH0377461U JP H0377461 U JPH0377461 U JP H0377461U JP 1989138376 U JP1989138376 U JP 1989138376U JP 13837689 U JP13837689 U JP 13837689U JP H0377461 U JPH0377461 U JP H0377461U
Authority
JP
Japan
Prior art keywords
lead
electronic component
lead terminal
semiconductor element
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1989138376U
Other languages
English (en)
Other versions
JPH0648877Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989138376U priority Critical patent/JPH0648877Y2/ja
Publication of JPH0377461U publication Critical patent/JPH0377461U/ja
Application granted granted Critical
Publication of JPH0648877Y2 publication Critical patent/JPH0648877Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す半導体装置の
横断平面図、第２図は同じくその縦断側面図、第
３図はリードフレームの平面図、第４図は従来の
半導体装置の横断平面図、第５図は同じくその縦
断側面図、第６図は他の従来例を示す横断平面図
、第７図は同じくその縦断側面図である。 １０……リードフレーム、１１……半導体素子
、１２……電子部品、１３……封止樹脂、１４…
…半導体素子搭載用リード端子、１５，１６，１
７……電子部品搭載用リード端子、１７ａ……不
要リード部、１８……ボンデイングワイヤー、１
９……結線用リード端子、２０……固定部材。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレーム上に半導体素子および電子部品
    が搭載され、これらが封止樹脂にて封止された半
    導体装置であつて、前記リードフレームは、前記
    半導体素子が搭載される半導体素子搭載用リード
    端子と、前記電子部品が搭載される電子部品搭載
    用リード端子と、前記半導体素子と内部結線され
    る結線用リード端子とを備え、前記電子部品搭載
    用リード端子のうち、樹脂封止前に前記封止樹脂
    から露出しないように不要リード部が切断されて
    他のリード端子と電気的に絶縁されるリード端子
    が、固定部材により他のリード端子に機械的に固
    定され、外部との入出力を必要とするリード端子
    のみが前記封止樹脂外に露出されたことを特徴と
    する半導体装置。
JP1989138376U 1989-11-28 1989-11-28 半導体装置 Expired - Fee Related JPH0648877Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989138376U JPH0648877Y2 (ja) 1989-11-28 1989-11-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989138376U JPH0648877Y2 (ja) 1989-11-28 1989-11-28 半導体装置

Publications (2)

Publication Number Publication Date
JPH0377461U true JPH0377461U (ja) 1991-08-05
JPH0648877Y2 JPH0648877Y2 (ja) 1994-12-12

Family

ID=31685480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989138376U Expired - Fee Related JPH0648877Y2 (ja) 1989-11-28 1989-11-28 半導体装置

Country Status (1)

Country Link
JP (1) JPH0648877Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011243626A (ja) * 2010-05-14 2011-12-01 Mitsubishi Electric Corp 半導体モジュールとその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011243626A (ja) * 2010-05-14 2011-12-01 Mitsubishi Electric Corp 半導体モジュールとその製造方法

Also Published As

Publication number Publication date
JPH0648877Y2 (ja) 1994-12-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees