JPH0375903B2 - - Google Patents

Info

Publication number
JPH0375903B2
JPH0375903B2 JP57169114A JP16911482A JPH0375903B2 JP H0375903 B2 JPH0375903 B2 JP H0375903B2 JP 57169114 A JP57169114 A JP 57169114A JP 16911482 A JP16911482 A JP 16911482A JP H0375903 B2 JPH0375903 B2 JP H0375903B2
Authority
JP
Japan
Prior art keywords
addition
bit
digit
stages
partial products
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57169114A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5958543A (ja
Inventor
Atsushi Iwamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57169114A priority Critical patent/JPS5958543A/ja
Publication of JPS5958543A publication Critical patent/JPS5958543A/ja
Publication of JPH0375903B2 publication Critical patent/JPH0375903B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP57169114A 1982-09-28 1982-09-28 高速乗算装置 Granted JPS5958543A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57169114A JPS5958543A (ja) 1982-09-28 1982-09-28 高速乗算装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57169114A JPS5958543A (ja) 1982-09-28 1982-09-28 高速乗算装置

Publications (2)

Publication Number Publication Date
JPS5958543A JPS5958543A (ja) 1984-04-04
JPH0375903B2 true JPH0375903B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-12-03

Family

ID=15880555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57169114A Granted JPS5958543A (ja) 1982-09-28 1982-09-28 高速乗算装置

Country Status (1)

Country Link
JP (1) JPS5958543A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03142627A (ja) * 1989-10-24 1991-06-18 Bipolar Integrated Technol Inc 集積浮動小数点乗算器アーキテクチャ

Also Published As

Publication number Publication date
JPS5958543A (ja) 1984-04-04

Similar Documents

Publication Publication Date Title
EP0185025B1 (en) An xxy bit array multiplier/accumulator circuit
JP2594428B2 (ja) キヤリー伝播遅延を短縮する方法および装置
JP3244506B2 (ja) 小型乗算器
US5010510A (en) Multiplying unit circuit
US3636334A (en) Parallel adder with distributed control to add a plurality of binary numbers
US4130878A (en) Expandable 4 × 8 array multiplier
JPH0456339B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US4441158A (en) Arithmetic operation circuit
US5161119A (en) Weighted-delay column adder and method of organizing same
EP0416869B1 (en) Digital adder/accumulator
JP3556950B2 (ja) 高速算術演算装置のけた上げ先見加算器段の数を減少させる構造及び方法
EP0344226B1 (en) High-speed digital adding system
JPH0375903B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US3125675A (en) jeeves
US3125676A (en) jeeves
JP2608600B2 (ja) 2つの数の和のパリティビットの計算装置
JPS615345A (ja) 直列乗算方法
US5309384A (en) Digital multiplier with carry-sum input
SU898422A1 (ru) Многовходовое суммирующее устройство
SU974370A1 (ru) Устройство дл умножени
JP3477816B2 (ja) トリー加算器及び乗算器
SU363119A1 (ru) Регистр сдвига
JPS63163927A (ja) 乗算回路
JPH05108308A (ja) 乗算回路
JPH044612B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)