JPH0373142B2 - - Google Patents

Info

Publication number
JPH0373142B2
JPH0373142B2 JP60241157A JP24115785A JPH0373142B2 JP H0373142 B2 JPH0373142 B2 JP H0373142B2 JP 60241157 A JP60241157 A JP 60241157A JP 24115785 A JP24115785 A JP 24115785A JP H0373142 B2 JPH0373142 B2 JP H0373142B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
chip
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60241157A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62101044A (ja
Inventor
Yoshitaka Fukuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60241157A priority Critical patent/JPS62101044A/ja
Publication of JPS62101044A publication Critical patent/JPS62101044A/ja
Publication of JPH0373142B2 publication Critical patent/JPH0373142B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP60241157A 1985-10-28 1985-10-28 混成集積回路装置の製造方法 Granted JPS62101044A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60241157A JPS62101044A (ja) 1985-10-28 1985-10-28 混成集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60241157A JPS62101044A (ja) 1985-10-28 1985-10-28 混成集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS62101044A JPS62101044A (ja) 1987-05-11
JPH0373142B2 true JPH0373142B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-11-20

Family

ID=17070108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60241157A Granted JPS62101044A (ja) 1985-10-28 1985-10-28 混成集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS62101044A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111130536B (zh) * 2019-12-09 2023-04-28 宁波大学 一种同时具有老化检测和puf功能的电路

Also Published As

Publication number Publication date
JPS62101044A (ja) 1987-05-11

Similar Documents

Publication Publication Date Title
US5477009A (en) Resealable multichip module and method therefore
US7105366B2 (en) Method for in-line testing of flip-chip semiconductor assemblies
US4560826A (en) Hermetically sealed chip carrier
US3657805A (en) Method of housing semiconductors
CN114050129A (zh) 一种气密性封装差动电容加速度计信号检测电路外壳
US6245582B1 (en) Process for manufacturing semiconductor device and semiconductor component
JP4157715B2 (ja) 半導体装置の製造方法
JPH0373142B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2002016267A (ja) 光素子・電子素子混載モジュール
US6159838A (en) Method of performing rework test on integrated circuit packages
JPH0637401A (ja) 光半導体容器
JPH06169033A (ja) 半導体チップの実装方法
JPS62101051A (ja) 混成集積回路装置の製造方法
JPH08162499A (ja) 半導体装置の製造方法
JPH06120417A (ja) マルチチップモジュールの実装構造及びその製造方法
JPH0337304B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0567727A (ja) 半導体装置用回路基板
JPS6192014A (ja) 表面波デバイスの製造方法
JPH02148861A (ja) マルチチップパッケージの製造方法
JPS59144146A (ja) 混成集積回路装置の製造方法
JPH06201793A (ja) 電子部品、および、これを搭載する回路基板の検査方法
JPH09252023A (ja) 半導体装置およびその製造方法
Mazenko et al. Reliability Investigation of Plastic Encapsulated/Polymer Sealed Hybrid Microcircuits
JPS5893263A (ja) 密閉方法
JPH0199244A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term