JPH0370414B2 - - Google Patents
Info
- Publication number
- JPH0370414B2 JPH0370414B2 JP22559686A JP22559686A JPH0370414B2 JP H0370414 B2 JPH0370414 B2 JP H0370414B2 JP 22559686 A JP22559686 A JP 22559686A JP 22559686 A JP22559686 A JP 22559686A JP H0370414 B2 JPH0370414 B2 JP H0370414B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- circuit
- cmi
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001934 delay Effects 0.000 claims description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 230000004044 response Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22559686A JPS6380628A (ja) | 1986-09-24 | 1986-09-24 | Cmi符号化回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22559686A JPS6380628A (ja) | 1986-09-24 | 1986-09-24 | Cmi符号化回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6380628A JPS6380628A (ja) | 1988-04-11 |
| JPH0370414B2 true JPH0370414B2 (enrdf_load_stackoverflow) | 1991-11-07 |
Family
ID=16831801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22559686A Granted JPS6380628A (ja) | 1986-09-24 | 1986-09-24 | Cmi符号化回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380628A (enrdf_load_stackoverflow) |
-
1986
- 1986-09-24 JP JP22559686A patent/JPS6380628A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6380628A (ja) | 1988-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6260152B1 (en) | Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains | |
| JP2002208844A (ja) | グリッチ除去回路 | |
| JPH0227834A (ja) | 位相整合回路 | |
| TW546816B (en) | Input/output interface and semiconductor integrated circuit having input/output interface | |
| US4786823A (en) | Noise pulse suppressing circuit in digital system | |
| JPH07131448A (ja) | 位相比較回路 | |
| JPS5828981B2 (ja) | Cmiエンコ−ダ | |
| US5306959A (en) | Electrical circuit for generating pulse strings | |
| US6930522B2 (en) | Method and apparatus to delay signal latching | |
| JPS6179318A (ja) | フリツプフロツプ回路 | |
| JPH0370414B2 (enrdf_load_stackoverflow) | ||
| JPH0462624B2 (enrdf_load_stackoverflow) | ||
| JPH0614609B2 (ja) | 論理ゲ−ト・アレイ | |
| JPH0590970A (ja) | Cmiエンコーダ回路 | |
| US4741005A (en) | Counter circuit having flip-flops for synchronizing carry signals between stages | |
| JPS63167496A (ja) | 半導体メモリ装置 | |
| JPH09214297A (ja) | ラッチ回路 | |
| KR20010006850A (ko) | 스큐 포인터 발생 회로 및 방법 | |
| JPH01276327A (ja) | クロック発生回路 | |
| KR910007809B1 (ko) | 디지탈 데이타의 왜곡 보상회로 | |
| JPH0695643B2 (ja) | Cmi符号化回路 | |
| JPH0462625B2 (enrdf_load_stackoverflow) | ||
| JPH0529924A (ja) | 9分周回路 | |
| KR100338402B1 (ko) | 기억장치및그제어방법 | |
| JPS6352809B2 (enrdf_load_stackoverflow) |