JPH0370260B2 - - Google Patents
Info
- Publication number
- JPH0370260B2 JPH0370260B2 JP19406685A JP19406685A JPH0370260B2 JP H0370260 B2 JPH0370260 B2 JP H0370260B2 JP 19406685 A JP19406685 A JP 19406685A JP 19406685 A JP19406685 A JP 19406685A JP H0370260 B2 JPH0370260 B2 JP H0370260B2
- Authority
- JP
- Japan
- Prior art keywords
- access
- key
- storage
- unit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19406685A JPS6263353A (ja) | 1985-09-03 | 1985-09-03 | 記憶装置アクセス制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19406685A JPS6263353A (ja) | 1985-09-03 | 1985-09-03 | 記憶装置アクセス制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6263353A JPS6263353A (ja) | 1987-03-20 |
JPH0370260B2 true JPH0370260B2 (fr) | 1991-11-07 |
Family
ID=16318385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19406685A Granted JPS6263353A (ja) | 1985-09-03 | 1985-09-03 | 記憶装置アクセス制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6263353A (fr) |
-
1985
- 1985-09-03 JP JP19406685A patent/JPS6263353A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6263353A (ja) | 1987-03-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5313602A (en) | Multiprocessor system and method of control over order of transfer of data between buffer storages | |
US4424564A (en) | Data processing system providing dual storage of reference bits | |
JPH0370260B2 (fr) | ||
JPH0540694A (ja) | キヤツシユメモリ装置 | |
US5933856A (en) | System and method for processing of memory data and communication system comprising such system | |
JPH01125644A (ja) | データ転送装置 | |
JPH01251248A (ja) | スタックデータ構造用キャッシュ制御方式 | |
JPS59231665A (ja) | デイスク制御装置 | |
JPH02101552A (ja) | アドレス変換バッファ処理方式 | |
JPS5836434B2 (ja) | バツフアメモリソウチ | |
JPS6073761A (ja) | 記憶保護装置 | |
JP2604604B2 (ja) | スタック制御装置 | |
JPH0526216B2 (fr) | ||
JPS6238743B2 (fr) | ||
JPH0752423B2 (ja) | デ−タ転送制御方式 | |
JPH03127126A (ja) | 情報処理装置 | |
JPS6055454A (ja) | デ−タ転送制御方式 | |
JPH05210586A (ja) | キャッシュメモリ制御回路 | |
JPH0546477A (ja) | キヤツシユメモリ制御方法 | |
JPH02133854A (ja) | 転送可否メモリにアクセス可能なdmaコントローラ | |
JPS6367668A (ja) | マルチプロセサシステム | |
JPH01177661A (ja) | データ転送装置 | |
JPS63752A (ja) | メモリ保護方式 | |
JPH0460729A (ja) | 情報処理装置 | |
JPH02287848A (ja) | キャッシュメモリ制御方式 |