JPH0368171A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease defectives so as to improve a semiconductor device of this design in productivity by a method wherein grooves provided onto a wafer are formed into rugged gridirons. CONSTITUTION:Grid-like grooves 3c, are composed of grooves 3a separated from each other and closed surrounding chip pattern regions A and grooves 3b which connect the corners of the adjacent grooves 3a in a diagonal direction together intersecting each other, are formed at the same time through a mesa etching. The grooves 3c are formed through such a method that the surface of a wafer 3 is masked leaving a grid-like part unmasked after oxidation and then etched. By this setup, the grooves 3c are not straight along a direction in which they extend vertically or horizontally on the wafer 3, so that cracks or fissures hardly occur in the wafer 3 and consequently a semiconductor device of this design can be lessened in defect and improved in productivity.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to improve productivity by reducing manufacturing defects in a method for manufacturing wafers for semiconductor devices such as ICs, and to improve productivity by reducing manufacturing defects. Forming grooves that are provided independently from each other so as to surround the periphery thereof, and grooves that cross each other and connect each corner of the liquid groove and the opposing corners of the grooves adjacent in the diagonal direction of the liquid groove. It consists of processes.

[Industrial application field]

The present invention relates to a semiconductor device manufacturing process in which a groove is formed around a chip pattern by, for example, mesa etching, and in particular, it reduces manufacturing defects by making the thickness of a film such as a resist uniform in the groove part. The present invention relates to a method of manufacturing a semiconductor device that improves productivity.

- In a semiconductor device in which a groove is formed by mesa etching around a chip pattern on the wafer (hereinafter referred to as a mesa type semiconductor device), the groove is formed at a predetermined position corresponding to the chip pattern at the wafer stage. However, measures such as changing the junction position of the P-N junction are taken, but the wafer may crack or crack.
Since defects are likely to occur in the subsequent pattern forming step, a solution to this problem is desired.

(Prior Art) FIG. 2 is a diagram showing a wafer of a conventional mesa-type semiconductor device, and FIG. 3 is a diagram showing a wafer of another mesa-type semiconductor device.

In the figure, for ease of understanding, a case will be described in which a groove is formed in the wafer by mesa etching at an early stage of the wafer etching process.

In FIG. 2, a wafer 1 has grooves 1a formed on its surface by mesa etching in a grid pattern so as to correspond to the size A indicated by the hatching of the required chip patterns to be aligned.

The lattice-shaped grooves 1a created by this mesa-etching are usually created by oxidizing the surface of the wafer 1, leaving only the lattice portions, and then masking them, removing only the oxide film with a fluorine-based chemical, and then adding a mixture of hydrofluoric acid and nitric acid. The silicon of the wafer 1 (St
), but for example, in the case of the figure, 1
It took about 50 seconds for the width W to be 130 μm and the depth d to be 6
A groove having a cross section of about 0 μm and a substantially semicircular shape is formed.

In order to obtain a desired semiconductor chip using such a wafer 1, for example, while rotating the wafer 1 in the direction of arrow R in the figure, a resist or the like is dropped onto the entire surface of the wafer 1 by centrifugal force, and the resist or the like is applied by, for example, 0.5%. After uniformly applying the coating to a thickness of about 1 μm, a predetermined pattern is formed in each area A by a normal masking technique corresponding to the groove 1a, and the same method is repeated several times to form the desired pattern in each area A. A chip pattern is formed, and further as shown in FIG.
As shown in B', it is cut vertically and horizontally along the groove 1a using a cutting saw or the like.

In this case, for example, the surplus of the dropped resist is
After falling into the liquid groove 1a, the liquid flows through the liquid groove 1a and is dissipated and removed from the end portion 1b, so that a film having a uniform thickness is formed, and as a result, a good chip pattern can be obtained.

However, since the grooves 1a are formed vertically and horizontally on the wafer 1, cracks and cracks are likely to occur, resulting in a disadvantage that the yield is reduced and no improvement in productivity can be expected.

FIG. 3 has been devised to eliminate this drawback.

In the figure, a wafer 2 has grooves 28 formed by individually closed mesa etching around a required chip pattern area A similar to that shown in FIG.

In this case, the formation density of the chip pattern on the wafer 2 is somewhat reduced, but since the grooves 2a in the transverse or vertical direction of the wafer 2 are discontinuous, there is no decrease in yield due to cracks or cracks, and the chip pattern is efficiently formed. chip patterns can be formed.

Further, after the chip pattern is formed, the chip pattern is cut into pieces in the middle of the groove 2a as indicated by the dashed lines c and c', so there is an advantage that the groove 23 portion can be used as a part of the chip pattern.

In particular, when the groove 28 portion is used as a part of a chip pattern, it is necessary to form a film of the same thickness on the groove 2a portion when applying a resist, etc. for pattern formation. Become.

However, as described above, the groove 2a is closed.

Therefore, as explained in FIG. 2, if, for example, a resist l~ is dropped while rotating the wafer 2 in the R direction, the resist will be applied to the rotation of the other grooves 2a except for the groove 2a having an opening on the peripheral surface of the wafer 2. It concentrates and stays in the area outside the direction,
The thickness of the resist in the equal groove 28 becomes extremely thick in parts where the thickness of the resist in this region is, for example, several μm or more.

The encircled enlarged view (■) is a plan view of this state, and the resist flows as indicated by the arrow a in the figure and concentrates in the above-mentioned area on the outside in the rotational direction.

Therefore, even if a chip pattern is formed in subsequent processing, the D? of the groove 28? A predetermined pattern cannot be formed only in the fJl region due to poor development.

[Problems to be Solved by the Invention] In the conventional method for manufacturing wafers for semiconductor devices, when grooves are formed in a lattice shape by mesa etching, cracks and cracks are likely to occur in the wafer at the wafer stage, resulting in a reduction in yield. There is a problem that it is not possible to improve
Further, when the liquid groove is closed, there is a problem in that if the groove portion is used as part of a chip pattern, defects are likely to occur during pattern formation, and no improvement in productivity can be expected.

[Means to solve the problem]

The above problem is that grooves are provided independently from each other to surround each chip pattern area on the wafer, and grooves that are diagonally adjacent to each corner of the liquid groove are opposed to each other. The problem is solved by a method of manufacturing a semiconductor device including a step of forming grooves that intersect and connect the corners of the semiconductor device.

[For production]

If the grooves formed on the wafer are made into a lattice shape with unevenness, cranks and cracks can be suppressed, and the resist, etc., will not stay in the grooves during the resist coating process, and the resist, etc. can be coated with a uniform thickness. I can do it.

In the present invention, mesa-etched grooves formed independently to close individual chip patterns are interconnected at each corner of the liquid groove with opposing corners of diagonally adjacent grooves to form a net-like structure as a whole. is formed.

Therefore, since the grooves do not form a linear grid, the wafer will not crack or crack, and since the liquid grooves are formed in a continuous state, resist etc. will not accumulate (<i It is possible to obtain semiconductor device wafers with good productivity that do not cause defects even during turn formation.

〔Example〕

FIG. 1 is a diagram showing an example of a semiconductor device according to the present invention.

In FIG. 1, the wafer 3 has independent grooves 3a on its surface that close and surround the chip pattern area A similar to FIGS. 2 and 3, and grooves 3a adjacent to the grooves 3a in the diagonal direction. The mesh-like grooves 30, which are composed of the grooves 3b intersecting and connecting the opposite corners, are simultaneously formed by the above-mentioned mesa etching.

The mesh-like grooves 30 created by this mesa etching are usually created by oxidizing the surface of the wafer as explained in FIG. After that, the silicon (Si) of the wafer is further etched with a mixture of hydrofluoric acid and nitric acid, and the cross section has a width W of about 130 μm and a depth d of about 60 μm, as shown in Fig. 2. The groove is approximately semicircular.

In the case of such a wafer, since the grooves 3c are not straight in the transverse or vertical direction of the cough wafer 3, the second groove 3c is not straight.
Cracks and cracks in the wafer as explained in the figure are less likely to occur and the yield is not lowered.

Furthermore, when the wafer 3 is rotated in the R direction shown in the figure to apply a resist, etc., the resist, etc. that stays in the area shown in FIG. at least the groove 3a without staying in the groove 3a.
The coating thickness of resist, etc. within 8 can be made almost uniform.

Therefore, the groove 3a portion can be used as part of the chip pattern without causing defects.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that improves productivity by reducing manufacturing defects during pattern formation without causing cracks or cracks in the wafer. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a wafer of a semiconductor device according to the present invention, FIG. 2 is a diagram showing a wafer of a conventional semiconductor device, and FIG. 3 is a diagram showing a wafer of another semiconductor device. In the figure, 3 represents a wafer, and 3a, 3b, and 3c represent grooves. An example of Kaede Eno's half-dedicated device that makes Kaede a must-sing customer post 1'
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Claims (1)

[Claims] Grooves (
3a), and grooves (3b) that intersect and connect each corner of the groove (3a) and the opposing corner of the groove (3a) diagonally adjacent to the groove (3a). 1. A method of manufacturing a semiconductor device, the method comprising the steps of: