JPH0367346B2 - - Google Patents
Info
- Publication number
- JPH0367346B2 JPH0367346B2 JP59014633A JP1463384A JPH0367346B2 JP H0367346 B2 JPH0367346 B2 JP H0367346B2 JP 59014633 A JP59014633 A JP 59014633A JP 1463384 A JP1463384 A JP 1463384A JP H0367346 B2 JPH0367346 B2 JP H0367346B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- electrode
- insulating
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 85
- 239000012535 impurity Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910010413 TiO 2 Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- -1 metals Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Description
【発明の詳細な説明】
本発明は、Ta2O5、TiO2などの誘電体膜を用
いた容量の形成方法に関し、特に、膜中を流れる
リーク電流が少く、また絶縁耐圧の高い誘電体薄
膜を形成する方法に関する。[Detailed Description of the Invention] The present invention relates to a method for forming a capacitor using a dielectric film such as Ta 2 O 5 or TiO 2 , and particularly relates to a method for forming a capacitor using a dielectric film such as Ta 2 O 5 or TiO 2, and in particular, a method for forming a capacitor using a dielectric film that has a low leakage current flowing through the film and a high dielectric strength. The present invention relates to a method of forming a thin film.
近年、MOS型半導体装置が広く用いられ、そ
の集積度は年々高密度化が計られている。従来、
高密度化はパターンを微細化することにより行な
われてた。しかし、ダイナミツク・ランダムアク
セスメモリ（DRAM）の如き半導体装置では、
パターンの微細化は信号に対応した蓄積電荷量の
低下を招き、α線などの放射線によるメモリの誤
動作（ソフトエラー）が発生するという問題を生
ずる。このため、パターンを微細化しても蓄積電
荷量を低下させない手段を講ずる必要がある。従
来、電荷を蓄積する容量部分の絶縁膜を薄くし、
容量値を低下させないことで対処していた。しか
し、膜が薄くなるとピンホールが増大するため充
分な耐圧が得られず歩留りが低下するなど薄膜化
にも限界があつた。 In recent years, MOS type semiconductor devices have been widely used, and their integration density is increasing year by year. Conventionally,
High density was achieved by making the pattern finer. However, in semiconductor devices such as dynamic random access memory (DRAM),
The miniaturization of patterns leads to a decrease in the amount of accumulated charge corresponding to a signal, resulting in the problem of memory malfunctions (soft errors) caused by radiation such as alpha rays. Therefore, it is necessary to take measures that do not reduce the amount of accumulated charge even if the pattern is made finer. Conventionally, by thinning the insulating film in the capacitive part that stores charge,
This problem was dealt with by not reducing the capacitance value. However, as the film becomes thinner, the number of pinholes increases, making it impossible to obtain a sufficient withstand voltage and lowering the yield.There were limits to thinning the film.
通常、容量部分の誘導体材料として、比誘電率
3.9のSiO2が用いられているが、比誘電率の高い
材料を用いれば同じ電極面積でも容量を大きくす
ることが可能となり、従つて、いつそうの微細化
が可能となる。このため、すでに、Ta2O5、
TiO2などの高誘電材料が検討されてきた。これ
らの膜を形成する手段は、例えばTa、Tiなどの
金属材料を真空中で蒸着した後、酸素雰囲気中で
熱処理する、あるいは、陽極酸化するなどの手段
で酸化することにより、もしくはTa2O5、TiO2
などの物質を真空中でスパツタ蒸着する、あるい
はCVD法を用いて堆積するなどの手段で形成さ
れている。しかしながら、これらの手段を用いて
形成された膜は、低電圧の印加でリーク電流が多
く流れるため、未だ実用に耐える段階に至つてい
ない。 Usually, the relative dielectric constant is used as the dielectric material for the capacitor part.
Although SiO 2 with a dielectric constant of 3.9 is used, if a material with a high dielectric constant is used, it is possible to increase the capacitance even with the same electrode area, and therefore, miniaturization becomes possible at any time. Therefore, Ta 2 O 5 ,
High dielectric materials such as TiO 2 have been considered. These films can be formed by, for example, depositing a metal material such as Ta or Ti in a vacuum and then heat-treating it in an oxygen atmosphere, or oxidizing it by anodizing, or using Ta 2 O. 5 , TiO2
These materials are formed by sputter deposition in a vacuum or by CVD. However, films formed using these methods have not yet reached a stage where they can be put to practical use because a large amount of leakage current flows when a low voltage is applied.
この原因としては、蒸着された金属膜が結晶粒
構造をもつており、酸化により形成された誘電体
膜も多結晶構造になつていると考えられ、結晶粒
界を通じてリーク電流が流れるものと考えられ
る。従つて、膜構造を多結晶構造にしない手段を
構ずればリーク電流を低減できるのではないかと
本発明者は考えた。 The reason for this is thought to be that the deposited metal film has a crystal grain structure, and the dielectric film formed by oxidation also has a polycrystalline structure, and leakage current is thought to flow through the grain boundaries. It will be done. Therefore, the inventor thought that the leakage current could be reduced by creating a means to prevent the film structure from becoming a polycrystalline structure.
本発明は、かかる考察にもとづき従来の方法に
よつて形成した膜の絶縁耐圧が低くリーク電流が
大きいという欠点を排除した高品質の膜を実現す
る手段を提供することにあり、その要旨はいつた
ん形成した絶縁膜を完全に非晶質な絶縁膜にする
手段を行うことにある。 Based on this consideration, the present invention provides a means for realizing a high-quality film that eliminates the drawbacks of low dielectric strength and large leakage current of films formed by conventional methods. The object of the present invention is to provide a means for converting a simply formed insulating film into a completely amorphous insulating film.
本発明の特徴は、表面の一部に第１の絶縁膜を
設けた半導体基板上に第１の電極膜パターンを設
け、次に該第１の電極膜パターンの表面を含む前
記第１の絶縁膜表面に、もしくは該第１の電極膜
パターンの表面あるいは該第１の電極膜パターン
の表面を含む前記第１の絶縁膜の表面にいつたん
第２の絶縁膜を設けた後に当該第２の絶縁膜表面
に、又、当該第２の絶縁膜表面を含む前記第１の
絶縁膜表面に、第３の絶縁膜を設け、次に、該第
３の絶縁膜表面に加速せしめたイオンを照射する
ことにより当該第３の絶縁膜を非晶質の絶縁膜と
なし、続いて当該非晶質の絶縁膜を熱処理した後
に前記第１の電極膜の一部をおおう領域の当該第
３の絶縁膜表面に第２の電極膜を設けることによ
り、前記第１の電極膜と第２の電極膜との間に容
量を構成する容量の形成方法にある。 A feature of the present invention is that a first electrode film pattern is provided on a semiconductor substrate having a first insulating film on a part of the surface, and then the first insulating film including the surface of the first electrode film pattern is provided. Once a second insulating film is provided on the film surface, or on the surface of the first electrode film pattern or on the surface of the first insulating film including the surface of the first electrode film pattern, A third insulating film is provided on the surface of the insulating film and on the surface of the first insulating film including the surface of the second insulating film, and then the surface of the third insulating film is irradiated with accelerated ions. By doing so, the third insulating film is made into an amorphous insulating film, and after the amorphous insulating film is heat-treated, the third insulating film in the region covering a part of the first electrode film is heated. A method of forming a capacitor constitutes a capacitor between the first electrode film and the second electrode film by providing a second electrode film on the surface of the film.
次に本発明の実施例を説明する。 Next, embodiments of the present invention will be described.
第１図は、本発明を用いて容量を形成する場合
の一実施例を示しており、その製作工程を説明す
るための断面構造を示している。図において、１
は半導体基板、２および２２は絶縁膜、３は電
極、４は不純物領域、５および５６は絶縁膜、６
はイオンの飛来方向、７は電極をそれぞれ示す。
半導体基板１としてシリコンを、電極３として多
結晶シリコンを絶縁膜５としてTa2O5を用いて容
量を作る工程を順を追つて説明する。 FIG. 1 shows an example of forming a capacitor using the present invention, and shows a cross-sectional structure for explaining the manufacturing process. In the figure, 1
are semiconductor substrates, 2 and 22 are insulating films, 3 are electrodes, 4 are impurity regions, 5 and 56 are insulating films, 6
7 indicates the direction in which the ions fly, and 7 indicates the electrode.
The process of forming a capacitor using silicon as the semiconductor substrate 1, polycrystalline silicon as the electrode 3, and Ta 2 O 5 as the insulating film 5 will be explained step by step.
まず、一導電型を有するシリコン基板１の表面
にSiO2などの絶縁膜２が設けられ、続いて当該
絶縁膜２の一部が選択除去され窓２５が形成され
る（第１図ａ）。 First, an insulating film 2 such as SiO 2 is provided on the surface of a silicon substrate 1 having one conductivity type, and then a portion of the insulating film 2 is selectively removed to form a window 25 (FIG. 1a).
次に、絶縁膜２をマスクとして窓２５からシリ
コン基板の表面に不純物が導入され、該基板１と
逆の導電型を有する不純物領域４が形成され、続
いて多結晶シリコン膜３が気相成長法などの手段
を用いて形成される（第１図ｂ）。該不純物の導
入は、熱拡散法を用いても、あるいはイオン打込
法を用いても良くその選択は自由である。該不純
物領域４は電極として用いるため、高濃度に形成
される必要がある。また、多結晶シリコン膜３は
電極として用いるため、不純物を高濃度に含ませ
る必要がある。かかる不純物の導入は熱拡散法を
用いても、あるいはイオン打込み法を用いても良
く、さらに多結晶シリコン膜形成時に雰囲気中に
含ませても良く、その選択は自由である。なお、
窓２５が形成された後に不純物領域４を形成せず
に多結晶シリコン膜３を形成し、続いて当該多結
晶シリコン膜中に半導体基板１と逆型の不純物を
高濃度に導入し熱処理することにより不純物領域
４を形成しても良く、その選択は自由である。な
お、第１図ｂの構造を形成した後に、多結晶シリ
ンダ膜３を選択的に除去し多結晶パターンとして
も良い。 Next, impurities are introduced into the surface of the silicon substrate through the window 25 using the insulating film 2 as a mask, and an impurity region 4 having a conductivity type opposite to that of the substrate 1 is formed. Subsequently, a polycrystalline silicon film 3 is grown by vapor phase growth. (FIG. 1b). The impurity may be introduced by thermal diffusion or ion implantation, and the choice is free. Since the impurity region 4 is used as an electrode, it needs to be formed at a high concentration. Furthermore, since the polycrystalline silicon film 3 is used as an electrode, it is necessary to contain impurities at a high concentration. Such impurities may be introduced by thermal diffusion or ion implantation, or may be included in the atmosphere during formation of the polycrystalline silicon film, and the choice is free. In addition,
After the window 25 is formed, a polycrystalline silicon film 3 is formed without forming the impurity region 4, and then an impurity of a type opposite to that of the semiconductor substrate 1 is introduced into the polycrystalline silicon film at a high concentration and heat-treated. The impurity region 4 may be formed by any method, and the selection thereof is free. Note that after forming the structure shown in FIG. 1b, the polycrystalline cylinder film 3 may be selectively removed to form a polycrystalline pattern.
次に、前記多結晶シリコン膜３の表面にSiO2
などの絶縁膜２２を形成し、続いて当該絶縁膜２
２の表面にTa2O5膜５が設けられ、続いてAr、
O2、Ta、Mo、Ti、Pt、Ｗなどの物質もしくは
As、Ｐ、Ｂなどの不純物として働く物質６が、
当該膜５にイオン打込みされ、当該膜５が非晶質
の構造を持つ非晶質Ta2O5膜５６に変えられる
（第１図ｃ）。Ta2O5膜５の形成は、例えばTaを
真空中でスパツタ蒸着した後に、酸素雰囲気中で
熱処理する。あるいは陽極酸化するなどの手段で
酸化することにより、もしくはTa2O5を真空中で
スパツタ蒸着する、あるいは気相成長法により堆
積するなどのうちでいずれの手段を用いても選択
は自由である。絶縁膜２２は、多結晶シリコン膜
３とTa2O5膜５との反応を防止するために設けら
れるものであり、大きな容量を得る上では当該膜
２２は薄く形成される必要があり、好ましい膜厚
は50〜100〓である。また、Ta2O5膜５は大きな
容量を得る上から薄くよるのが望ましく、100〜
500〓の膜厚であることが好ましい。イオン打込
みの好ましい条件は、電圧10〜50KeV、打込量
1014〜1016cm-2である。なお、Ta2O5膜５の表面
から奥まで全域を充分に非晶質化するべく、加速
電圧を種々変化させてイオン打込みしても良い。
さらに、当該イオン打込みは、前記Ta2O5膜５を
選択的に除去し、パターンとなした後に行つても
良い。 Next, SiO 2 is deposited on the surface of the polycrystalline silicon film 3.
An insulating film 22 such as the following is formed, and then the insulating film 2
A Ta 2 O 5 film 5 is provided on the surface of 2, followed by Ar,
Substances such as O 2 , Ta, Mo, Ti, Pt, W or
Substances 6 that act as impurities such as As, P, and B are
Ions are implanted into the film 5 to transform it into an amorphous Ta 2 O 5 film 56 having an amorphous structure (FIG. 1c). The Ta 2 O 5 film 5 is formed by, for example, sputter-depositing Ta in a vacuum and then heat-treating it in an oxygen atmosphere. Alternatively, the user is free to choose which method to use, such as by oxidizing by means such as anodic oxidation, by sputter deposition of Ta 2 O 5 in a vacuum, or by depositing by vapor phase epitaxy. . The insulating film 22 is provided to prevent the reaction between the polycrystalline silicon film 3 and the Ta 2 O 5 film 5, and in order to obtain a large capacity, the film 22 needs to be formed thinly, which is preferable. The film thickness is 50 to 100 mm. In addition, it is desirable that the Ta 2 O 5 film 5 be thin in order to obtain a large capacity;
Preferably, the film thickness is 500 mm. The preferred conditions for ion implantation are a voltage of 10 to 50 KeV and an implantation amount.
10 14 to 10 16 cm -2 . Incidentally, in order to sufficiently make the entire region from the surface to the depths of the Ta 2 O 5 film 5 amorphous, ion implantation may be performed while varying the acceleration voltage.
Further, the ion implantation may be performed after the Ta 2 O 5 film 5 is selectively removed and patterned.
次に、600〜800℃の不活性ガス雰囲気中もしく
は酸素あるいは水分を含む雰囲気中で熱処理を行
い、続いて電極パターン７が形成されることによ
り多結晶シリコン膜３、絶縁膜２２、Ta2O5膜５
６、電極７との間に容量が形成される（第１図
ｄ。 Next, heat treatment is performed in an inert gas atmosphere at 600 to 800°C or in an atmosphere containing oxygen or moisture, and then the electrode pattern 7 is formed to form the polycrystalline silicon film 3, the insulating film 22, and the Ta 2 O 5 membrane 5
6, a capacitance is formed between the electrode 7 (FIG. 1d).
当該実施例では、多結晶電極膜３と高濃度不純
物領域４とはオーム接触であるため、高濃度不純
物領域４と電極７との間に電圧を印加することで
容量として機能させることが出来る特徴を持つ。 In this embodiment, since the polycrystalline electrode film 3 and the high concentration impurity region 4 are in ohmic contact, the feature is that by applying a voltage between the high concentration impurity region 4 and the electrode 7, it can function as a capacitor. have.
上記した実施例では、絶縁膜５としてTa2O5膜
を形成することとして説明したが、これは他の絶
縁膜例えばMgO、TiO2、Mb2O5などの絶縁膜を
用いる場合でも、さらにBaTiO3などの強誘電体
膜を用いる場合でも本発明は適用できる。 In the above embodiment, the Ta 2 O 5 film is formed as the insulating film 5, but this also applies even if other insulating films such as MgO, TiO 2 , Mb 2 O 5 , etc. are used. The present invention is applicable even when using a ferroelectric film such as BaTiO 3 .
また、電極３として多結晶シリコン膜を用いる
こととして説明したが、これはMo、Ti、Pt、Ｗ
などの金属を用いても、あるいはシリコンとの合
金膜（シリサイド）を用いても本発明に適用でき
る。 In addition, although it has been explained that a polycrystalline silicon film is used as the electrode 3, this can be applied to Mo, Ti, Pt, W, etc.
The present invention can be applied to metals such as metals, or alloy films with silicon (silicide).
また、絶縁膜２２としてSiO2を用いて説明し
たが、これはSi3N4などの絶縁膜を用いても良
く、さらに、当該絶縁膜２２は電極３と絶縁膜５
との反応を防止するために用いられているもので
あり、電極３と絶縁膜５とが反応しない物質の組
合せ、例えば電極３としてMoSiを、絶縁膜５と
してTa2O5を用いた場合には設ける必要はない。 Furthermore, although SiO 2 is used as the insulating film 22 in the explanation, an insulating film such as Si 3 N 4 may also be used.
This is used to prevent the reaction between the electrode 3 and the insulating film 5, and the combination of substances that do not cause the electrode 3 and the insulating film 5 to react, for example, when MoSi is used as the electrode 3 and Ta 2 O 5 is used as the insulating film 5. There is no need to provide it.
第１図は、本発明の一実施例を説明するための
断面図である。
図において、１は半導体基板、２は絶縁膜、３
は電極、４は不純物領域、５は絶縁膜、６はイオ
ンの飛来方向、７は電極、２５は窓、２２は絶縁
膜、５６は非晶質膜、をそれぞれ示す。
FIG. 1 is a sectional view for explaining one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a semiconductor substrate.
4 is an electrode, 4 is an impurity region, 5 is an insulating film, 6 is an ion flying direction, 7 is an electrode, 25 is a window, 22 is an insulating film, and 56 is an amorphous film.
Claims (1)
る工程と、該第一の絶縁膜上に第２の絶縁膜を設
ける工程と、該第２の絶縁膜に加速せしめたイオ
ンを照射することにより前記第２の絶縁膜を非晶
質化する工程と、その後熱処理する工程とを有す
ることを特徴とする半導体装置の製造方法。1. A step of providing a first insulating film on one main surface of a semiconductor substrate, a step of providing a second insulating film on the first insulating film, and irradiating the second insulating film with accelerated ions. A method for manufacturing a semiconductor device, comprising the steps of: amorphizing the second insulating film by amorphizing the second insulating film; and then performing heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1463384A JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1463384A JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60160155A JPS60160155A (en) | 1985-08-21 |
| JPH0367346B2 true JPH0367346B2 (en) | 1991-10-22 |
Family
ID=11866596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1463384A Granted JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160155A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0754846B2 (en) * | 1985-11-29 | 1995-06-07 | 株式会社日立製作所 | Capacitor manufacturing method |
| JPS6380969U (en) * | 1986-11-17 | 1988-05-27 | ||
| US4943012A (en) * | 1987-02-09 | 1990-07-24 | Ryobi Ltd. | Double bearing fishing reel |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60107838A (en) * | 1983-11-17 | 1985-06-13 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-01-30 JP JP1463384A patent/JPS60160155A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60107838A (en) * | 1983-11-17 | 1985-06-13 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60160155A (en) | 1985-08-21 |
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