JPS605531A - Formation of insulating film - Google Patents

Formation of insulating film

Info

Publication number
JPS605531A
JPS605531A JP58113149A JP11314983A JPS605531A JP S605531 A JPS605531 A JP S605531A JP 58113149 A JP58113149 A JP 58113149A JP 11314983 A JP11314983 A JP 11314983A JP S605531 A JPS605531 A JP S605531A
Authority
JP
Japan
Prior art keywords
film
amorphous
oxidation
ta2o5
tantalum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58113149A
Other languages
Japanese (ja)
Inventor
Yasuaki Hokari
穂苅 泰明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58113149A priority Critical patent/JPS605531A/en
Publication of JPS605531A publication Critical patent/JPS605531A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to form a dielectric film, through which leakage current little flows and whose insulating withstand voltage is high, by a method wherein at least a part of the surface of a metal film, which has been turned a part of the surface into an amorphous substance by irradiating ions, is oxidized. CONSTITUTION:A Ta film 2 is formed on the surface of a silicon substrate 1 by such a technique as a vacuum evaporation one, etc. This film 2 is oxidized afterwards and converted into a Ta2O5. A thin one is desirable as the film for obtaining a large capacity. The film has been usually made into a polycrystalline structure. Then, such substances as Ar, O2, Ta, etc., are ionized and an amorphous Ta film 21, whose surface has an amorphous structure, is formed by performing an ion-implantation in the Ta film 2. After that, the amorphous tantalum film 21 is converted into t Ta2O5 film 25 by being performed an oxidation in the atmosphere of oxidation or by being performed an anodic oxidation in the solution of oxalic acid. As the Ta2O5 film 25 formed in such a way is formed due to the oxidation of an amorphous tantalum, the film structure is amorphous. After this, an electrode is formed on the surface of the Ta2O5 film 25 and an MOS structure is constituted.

Description

【発明の詳細な説明】 本発明は、Ta2O,、Tio、、などの誘電体膜の形
成方法に関し、特に、膜中分流れるリークm流が少く、
また絶縁1圧の尚い誘電体膜を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a dielectric film such as Ta2O, Tio, etc., and in particular, the present invention relates to a method for forming a dielectric film such as Ta2O, Tio, etc.
The present invention also relates to a method of forming an insulating dielectric film having a single voltage.

近年、MOS 型半導体装置が広く用いられ、その果槓
度は年々^密度化がHFられている。従来、高密度化は
パターンを微細化することにより行なわれてきた。しか
し、ダイナミック・ランタムアクセスメモ1,1 (L
)1(AM )の如き半導体装置では、パターンの微油
1化は信号に対比、した蓄積電荷量の低下を州き α線
などの放射線によるメモリの誤動作(ノットエン−)が
発生ずるという問題を生ずる。このため、パターン化$
 +1ntl化しても畜積軍。
In recent years, MOS type semiconductor devices have been widely used, and their density is increasing year by year. Hitherto, higher density has been achieved by making patterns finer. However, dynamic random access memo 1, 1 (L
)1 (AM), the use of a slight oil in the pattern causes a decrease in the amount of accumulated charge relative to the signal, which can lead to memory malfunctions (not-en-) caused by radiation such as alpha rays. arise. For this reason, patterning $
Even if it becomes +1 ntl, it is an accumulation army.

荷量を低下させない手段をiδする必要かある。従来、
電荷を蓄積する容量部分の絶縁膜を助くシ、容量値を低
下させないことで対処しでいた。
Is it necessary to find a way to prevent the load from decreasing? Conventionally,
The solution was to protect the insulating film in the capacitive part that stores charge and not reduce the capacitance value.

しかし、膜が薄くなるとピンポールが増大するため充分
な耐圧が得られず歩留りが低圧するなど、薄膜化にも限
界かぁ−)だ。
However, as the film becomes thinner, the number of pin poles increases, making it impossible to obtain sufficient withstand pressure and lowering the yield.Therefore, there are limits to thinning the film.

通常、容量部分の誘電体材料として、比誘電率3.9の
5IO2が用しられてbるが、比誘−率の高いI料を用
すれば同じ電極面槓でも容量を犬さくすることがム」能
となシ、従って、いっそうの%B化がir]−能となる
。このため、すでに、Ta2O,、T i 02などの
高誘電材料が検討されてきた。これらの膜を形成する手
段は、例えはfil a、 Ill iなどの金属拐料
を真空中で蒸着した後、酸素雰囲気中で熱処理する、あ
るいは、陽極酸化するなどの手段で酸化することによシ
、形成されている。しかしながら、これらの手段を用い
てJし成きれた膜は、低電圧の印加でリーク−流が多く
流れるため、未だ実用に副える段階に至−+7いない。
Normally, 5IO2 with a dielectric constant of 3.9 is used as the dielectric material for the capacitor part, but if an I material with a high dielectric constant is used, the capacitance can be reduced even with the same electrode surface. Therefore, further %B conversion becomes ir]-function. For this reason, high dielectric materials such as Ta2O, Ti02, etc. have already been considered. The means for forming these films is, for example, by depositing metal particles such as fil a and Ill i in vacuum and then oxidizing them by heat treatment in an oxygen atmosphere or by anodic oxidation. Yes, it is being formed. However, films produced using these methods have not yet reached a stage where they can be put to practical use because a large amount of leakage current flows when a low voltage is applied.

この原因としてtri、感層された金属j漠が結晶粒構
造をもっCお9、酸化ンこより形成された訪電体J漠も
多結晶構造になっC−ると考えられ、結晶粒昇を進じて
リーク電流が流J1.るものと考えらJl、る。
The cause of this is thought to be that the sensitized metal layer has a crystal grain structure, and the contact layer formed by oxidation also has a polycrystalline structure, causing the crystal grains to rise. As the leakage current continues to flow, J1. Jl, Ru.

従って、1艮44!を造を多結晶構造にしない手段を湧
ずILばリーク電流を低減できるのではないかと本発明
者は考えた。
Therefore, 1 barge is 44! The inventor thought that it would be possible to reduce the leakage current by finding a way to avoid making the structure a polycrystalline structure.

本発明は、かかる考察にもとづき従来の方法によって形
成した膜の絶縁110j圧が低くリーク電流が大きいと
いう欠点を排除しlこ尚品質の膜を実現する手段を提供
することにあり、その要旨は金属膜を非晶質化する手段
を有った区に獣化することにあ4)。以下、本発明を実
/1Ii1例を用いて詳細に説明する。
Based on this consideration, the present invention aims to eliminate the disadvantages of low insulation 110j voltage and large leakage current of films formed by conventional methods, and to provide a means for realizing films of higher quality. The goal is to turn the metal film into a beast that has the means to make it amorphous4). Hereinafter, the present invention will be explained in detail using one example of Practical/1Ii.

第1図は、MO8型容量を形成する場合に本発を適用し
た場合を例にとり、その工程を説明するための断面構造
図である、図において1は半導体基板、2は金属膜、2
Jは非晶質の金14%層、25は絶縁膜、3はイオンの
飛来方向をそ71.それ示す。
FIG. 1 is a cross-sectional structural diagram for explaining the process, taking as an example the case where the present invention is applied to form an MO8 type capacitor. In the figure, 1 is a semiconductor substrate, 2 is a metal film,
J is an amorphous gold 14% layer, 25 is an insulating film, 3 is an ion flying direction 71. Show it.

半導体基板lとしてシリコン范板を、金属膜2としてT
a膜を用い、MO8容量を作ることとし、製造工程を順
を追ってh発明する。
A silicon flexible plate is used as the semiconductor substrate l, and T is used as the metal film 2.
We decided to create an MO8 capacity using a film, and invented the manufacturing process step by step.

まず、シリコン基板10表面にTa膜2を真空蒸着など
の手法で形成する(第1図a)。当該膜は、後に酸化さ
れTa、O,に変えられるものであシ、大きな容量を得
る上で薄い方が4讐しく、200〜soo X程度の膜
厚が好ましい。形成した当該膜2は、通常多結晶イ4造
となっている。
First, a Ta film 2 is formed on the surface of a silicon substrate 10 by a method such as vacuum evaporation (FIG. 1a). The film can be oxidized and converted into Ta, O, etc., and in order to obtain a large capacity, the thinner the film, the better, and a film thickness of about 200 to soo X is preferable. The formed film 2 is usually a polycrystalline structure.

次に、Ar102、Taなどの物質をイオンとなし、前
記Ta膜2にイオン打込みすることにより当該膜表面を
非晶質な構造を持つ非晶質’J’ a膜21が形成され
る(第1図b)。Ta膜2は博j挨であるので、イオン
打込みは例えば加速電圧lO〜30KeVの条件で10
14〜1016cm’のイオンを打ち込めは充分良質の
非晶質膜が形成される。当該イオン打込みではTa膜2
の厚さ方向全体が充分に非晶質となるように、加速電圧
を変化きしめてイオン打込みしても良い。この時、前記
シリコン基板1の表…工も非晶質化されるが、後の工程
で熱処理を行うこと圧よシ結晶性が回ゆするので実用上
問題とはなし)ない。捷だTa膜2の表向Wイオン打込
みのマスクとなるマスク膜のパターンを設はタンタル膜
の一部分にのみイオン打込みを行なってもよい。
Next, a substance such as Ar102 or Ta is ionized and ion-implanted into the Ta film 2, thereby forming an amorphous 'J' a film 21 having an amorphous structure on the film surface. Figure 1 b). Since the Ta film 2 is of high quality, the ion implantation is performed, for example, at an acceleration voltage of 10 to 30 KeV.
If ions of 14 to 1016 cm' are implanted, an amorphous film of sufficient quality is formed. In this ion implantation, Ta film 2
Ion implantation may be performed by changing the accelerating voltage so that the entire thickness direction becomes sufficiently amorphous. At this time, the surface of the silicon substrate 1 is also made amorphous, but this is not a practical problem since the crystallinity is restored by heat treatment in a later step. If a mask film pattern is provided to serve as a mask for W ion implantation into the surface of the uncut Ta film 2, ions may be implanted only into a portion of the tantalum film.

当該イオン打込みでは、ヒ素、リン、ボロンな7 どの
不純物イオンを打込むことによっても、前記タンタル膜
2を非晶質化すゐことは可能でち9、この場合にはシリ
コン基板1の表向に不純物領域が形成されることになる
。刀1かる不純物領域の形成は、本発明を他の構造の半
導体装置に適用する場合の応用範囲が広くな9好ま1.
b0非晶質タンタル膜21が形成ぢれた後、酸化雰囲気
中400〜500Cの温度で酸化することにより、もし
くはしゅ二)酸浴液中で陽極酸化することにより当該非
晶質タンタル膜21がTa、0.膜25に変えられる(
第1図C)。ここで形成されたTa205険25は、非
晶質のタンタルの酸化によυ形成されたものであるため
、膜構造は非晶質である。この後、Ta2O,膜25表
面に電極が形成されMO8構造が構成される。また非晶
質′ra膜21の全体でなく表面の一部分のみをTa2
05 膜に変えてもよい。
In the ion implantation, it is possible to make the tantalum film 2 amorphous by implanting impurity ions such as arsenic, phosphorus, and boron. An impurity region will be formed. Formation of the impurity region according to the above method has a wide range of application when the present invention is applied to semiconductor devices of other structures.9 Preferably 1.
b0 After the amorphous tantalum film 21 is formed, the amorphous tantalum film 21 is oxidized at a temperature of 400 to 500 C in an oxidizing atmosphere, or by anodic oxidation in an acid bath. Ta, 0. can be changed to membrane 25 (
Figure 1C). Since the Ta205 film 25 formed here is formed by oxidation of amorphous tantalum, the film structure is amorphous. Thereafter, an electrode is formed on the surface of the Ta2O film 25 to form an MO8 structure. In addition, only a part of the surface of the amorphous 'ra film 21 is coated with Ta2.
05 May be changed to a membrane.

なお、本工程の熱処理でTa膜2とシリコン基板1とが
多少反応し、シリコン基板1表面にタンタルシリサイド
層が形成されるためが、容量を形成する目的上は問題は
ない。しかしMO8容量としての電気的特性(特にTa
2O,とシリコンの界面特性)は劣化するため、これを
改善するためには、シリコン基板1表面にあらかじめ〜
さ50〜150オングストロームの5i02膜を形成し
た後にTa膜2を形成するのが望ましい。
Note that the Ta film 2 and the silicon substrate 1 react to some extent during the heat treatment in this step, and a tantalum silicide layer is formed on the surface of the silicon substrate 1, but this poses no problem for the purpose of forming a capacitor. However, the electrical characteristics (especially Ta
2O, and silicon) will deteriorate, so in order to improve this, it is necessary to
It is desirable to form the Ta film 2 after forming the 5i02 film with a thickness of 50 to 150 angstroms.

本発明を用いて形成したMO8容量のり−ク屯流量を調
べたところ、従来法に比べ約2桁リーク軍流が低減し、
充分良好の膜が形成されていることが判明した。
When we investigated the flow rate of MO8 capacity leakage formed using the present invention, we found that the leakage flow rate was reduced by about two orders of magnitude compared to the conventional method.
It was found that a sufficiently good film was formed.

第2図は、本発明を用いて容量を形成する場合の他の実
施例を示しておυ、その製作工程を説明するための断面
構造をボしている。図において、第1図と同記号は同機
能を有する物質を示しておシ、4は絶縁膜、5は不純物
領域、6は電極である。半導体基板1にシリコンを、金
属膜2にタンタルを用いて容量を作る工程f:1@を追
って説明する まず、−導電型を有するノリコン基板1の表面に、5I
O2などの絶縁膜4が設けられ、続いて当該絶縁膜4の
一部が選択除去され窓45が形成される(第2図a)。
FIG. 2 shows another embodiment in which a capacitor is formed using the present invention, and shows a cross-sectional structure for explaining the manufacturing process. In the figure, the same symbols as in FIG. 1 indicate substances having the same functions, 4 is an insulating film, 5 is an impurity region, and 6 is an electrode. The process f:1@ of creating a capacitor using silicon for the semiconductor substrate 1 and tantalum for the metal film 2 will be explained in detail.
An insulating film 4 such as O2 is provided, and then a portion of the insulating film 4 is selectively removed to form a window 45 (FIG. 2a).

次に、絶縁膜4をマスクとして窓45からシリコン基板
10表面に不純物が導入され、該基板1と逆の導電型を
有する不純物領域5が形成され、絖いてタンタル膜2が
真を蒸着法などの手段を用いて形成さ7Lる(第2図&
))。当該不純物の導入は、熱拡敵法を用いても、ある
いはイオン打込み法を用いでも良くその選択は自由であ
る。該不純物領域5は電極として用いるため、尚濃度に
形成される必要がある。寸だ、タンタル膜2け、一部分
は電極として用いるため、厚く形成される必要があシ、
その好ましい厚さは0.3〜1 ミクロンである。
Next, impurities are introduced into the surface of the silicon substrate 10 through the window 45 using the insulating film 4 as a mask, and an impurity region 5 having a conductivity type opposite to that of the substrate 1 is formed. 7L is formed using the means of (Fig. 2 &
)). The impurity may be introduced by thermal expansion method or ion implantation method, and the choice is free. Since the impurity region 5 is used as an electrode, it needs to be formed at a high concentration. There are two tantalum films, part of which is used as an electrode, so it needs to be thick.
Its preferred thickness is 0.3-1 micron.

次に、当該膜2つの表面にA r X(1)2 、’J
、’ aなとの物質3がイオン打込みきれ、当該膜2つ
の次面Vこ非晶質な構造を持つ非晶質タンタル膜21が
形成される(■2図c)1、イオン打込みの好ましい条
件は、電圧10〜20 KeV、打込み量10 〜10
cmであり、タンタル膜20表面の100〜300ス“
ングストロームの領域が非晶質のメンタル膜21 とな
る。またTa膜2の表面にイオン打込みのマスクとなる
マスク膜のパターン全段けTa膜2の一部とによシ、も
しくはしゅう酸溶液中で陽極酸化することによシ、非晶
質タンタル膜21がTa2U3膜25に変えられ、i続
いて電極パターン6が形成されることによpTa膜、’
l’a;Ua 膜25.111M 6とのjUj I/
C容量が構成される(紀2図d)。当該工程で酸化の鉛
件を17Lぶことにより非晶質タンタル膜21の表面C
Dり多−1’ a 20.膜に変えても、あるいけ昌該
膜21に加えてタンタル膜2の表面をもlT a 2+
、)、B!AK変えても特性上何ら問題は生じない。
Next, A r X (1) 2 , 'J
, 'A material 3 is ion-implanted, and an amorphous tantalum film 21 having an amorphous structure is formed on the second surface of the film (Fig. 2c) 1. Preferred ion implantation method The conditions are: voltage 10-20 KeV, implantation amount 10-10
cm, and 100 to 300 squares on the surface of the tantalum film 20.
The angstrom region becomes an amorphous mental film 21. In addition, an amorphous tantalum film can be formed on the surface of the Ta film 2 by removing a part of the Ta film 2 from all stages of the mask film pattern that serves as a mask for ion implantation, or by anodic oxidation in an oxalic acid solution. 21 is changed to a Ta2U3 film 25, and then an electrode pattern 6 is formed to form a pTa film,'
l'a; Ua membrane 25.111M 6 with jUj I/
C capacity is configured (Fig. 2 d). In this process, the surface C of the amorphous tantalum film 21 is reduced by 17L of lead oxide.
Drita-1' a 20. Even if it is changed to a film, in addition to the film 21, the surface of the tantalum film 2 is also lT a 2+
, ), B! Changing the AK will not cause any problems in terms of characteristics.

しかし、’1’ a 205膜25の下部:(Tはタン
タル膜2が残されている必決15;ある。
However, '1' a 205 below the film 25: (T is a must 15 where the tantalum film 2 remains.

当該実施例では l1la膜2と高繞匪不純物領域5と
はオーム接触でβるため、高値rtt不純物領域5と電
極6との向(置比圧を印加ず、t′・ことで容量を動作
させろことが出来る’ib長を持つ。
In this embodiment, since the l1la film 2 and the high-temperature impurity region 5 are in ohmic contact with each other, the capacitance can be operated by t It has an 'ib length that can be used.

上記(,7た2つの実施例では、i’a股を用いてTa
2O,、を形成することとして説明したが、ξれに[他
の金属、ドlえばAA’、 Mg、T1、Nbなどを用
いても、また、ノリj)との合≦1ミ通lモしくけ多結
晶シリコン耐、倹4・どを用い″(も、本発明は適用で
き4・。
In the above (, 7) two embodiments, the i'a crotch is used to
2O, . However, even if other metals, such as AA', Mg, T1, Nb, etc., are used, it is also possible to form The present invention can also be applied if a polycrystalline silicon material is used.

また、金属膜2 X?非晶ゴ)化する工程を、イメーン
打込法の手段τハjいて行っ7こが、これは金PA膜2
を非晶質化できれば(t!、lv月−二段を用い′ても
ぞの辷択ri目由でa)/−0−例としでAr、02 
なとのイスーンを数100■で加速し、前記金属膜20
表面に衝突させたいわゆるスパッタ法を採用して1、同
様の効果を得ることが出来る。この場合、スパッタによ
多金属膜表面が多少除去はれるが、金属S+予め厚く形
成しておけば問題はない。
Also, metal film 2X? The step of making the gold PA film 2 amorphous was carried out using the image implantation method 7.
If it is possible to make it amorphous (t!, lv month - using the second stage, it is a) / - 0 - as an example, Ar, 02
The speed of the metal film 20 is accelerated by several hundreds of seconds, and the metal film 20
A similar effect can be obtained by employing a so-called sputtering method in which the material is bombarded with a surface. In this case, the surface of the polymetal film may be removed to some extent by sputtering, but there is no problem if the metal S+ is formed thickly in advance.

【図面の簡単な説明】[Brief explanation of drawings]

第」図は、本発明の一実施例を説明するための図、第2
図は他の実施例を説明するための図で、各工程図におけ
る平県体装置の断面を示す。図におりて、lは半導体基
板、2は金属膜、21は非晶質の金属層、25は絶縁)
摸、3はイオンの飛来方向、4は絶縁膜、5は不純物領
域、6は電極をそれぞれ示す。 代i里人弁理」:自派 晋 第1図 j i= 第2図 1d)
Figure 2 is a diagram for explaining one embodiment of the present invention.
The figure is a diagram for explaining another embodiment, and shows a cross section of the Hikentai device in each process drawing. In the figure, l is a semiconductor substrate, 2 is a metal film, 21 is an amorphous metal layer, and 25 is an insulator)
In the figure, 3 indicates the direction in which ions fly, 4 indicates an insulating film, 5 indicates an impurity region, and 6 indicates an electrode. ``Representative Liton Attorney'': Jiha Shin Figure 1 j i = Figure 2 1d)

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に、もしくは光面に絶縁膜を設けた半導体
基板上に金属膜を設け、次に該金属膜表面に加速せしめ
たイオンを照射することによシ、少なくとも金属膜表面
の一部を非晶質の金属膜となし、続いて該非晶質の金属
膜の少なくとも表面の一部を酸化することによシ絶縁膜
とすることを特徴とした絶縁膜の形成方法。
A metal film is provided on a semiconductor substrate or a semiconductor substrate with an insulating film provided on the optical surface, and then at least a part of the metal film surface is irradiated with accelerated ions to the surface of the metal film. 1. A method for forming an insulating film, comprising forming an amorphous metal film and then oxidizing at least a part of the surface of the amorphous metal film to form an insulating film.
JP58113149A 1983-06-23 1983-06-23 Formation of insulating film Pending JPS605531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58113149A JPS605531A (en) 1983-06-23 1983-06-23 Formation of insulating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58113149A JPS605531A (en) 1983-06-23 1983-06-23 Formation of insulating film

Publications (1)

Publication Number Publication Date
JPS605531A true JPS605531A (en) 1985-01-12

Family

ID=14604805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58113149A Pending JPS605531A (en) 1983-06-23 1983-06-23 Formation of insulating film

Country Status (1)

Country Link
JP (1) JPS605531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62153373A (en) * 1985-12-27 1987-07-08 Mitsui Toatsu Chem Inc Flame-retardant adhesive composition for flexible printed circuit board
US6521930B2 (en) 2000-06-07 2003-02-18 Nec Corporation Semiconductor device having Ta2O5 thin film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62153373A (en) * 1985-12-27 1987-07-08 Mitsui Toatsu Chem Inc Flame-retardant adhesive composition for flexible printed circuit board
US6521930B2 (en) 2000-06-07 2003-02-18 Nec Corporation Semiconductor device having Ta2O5 thin film

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