JPS60107838A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60107838A
JPS60107838A JP21662983A JP21662983A JPS60107838A JP S60107838 A JPS60107838 A JP S60107838A JP 21662983 A JP21662983 A JP 21662983A JP 21662983 A JP21662983 A JP 21662983A JP S60107838 A JPS60107838 A JP S60107838A
Authority
JP
Japan
Prior art keywords
film
insulating film
ta2o5
substrate
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21662983A
Other languages
Japanese (ja)
Inventor
Yasuaki Hokari
穂苅 泰明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21662983A priority Critical patent/JPS60107838A/en
Publication of JPS60107838A publication Critical patent/JPS60107838A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a film, leakage currents therefrom are little and dielectric strength thereof is high, by laminating and applying first and second insulating films on the surface of a semiconductor substrate, implanting accelerated ions to the second insulating film to bring the second insulating film to an amorphous state and changing the second insulating film to a compact film through heat treatment when a dielectric film having high relative permitivity in Ta2O5, TiO2, etc. is formed on the surface of the substrate. CONSTITUTION:An SiO2 film 2 and a Ta2O5 film 3 are laminated and applied on an Si substrate 1, and ions of Ar, O2, Ta, etc. are implanted to the film 3 to change the film 3 into a Ta2O5 film 31 having amorphous structure. The surface of the substrate 1 is also brought to an amorphous state at that time, but a change into the amorphous state is not at issue practically because the change is recovered in a subsequent heat treatment process. The film 31 is turned into a Ta2O5 film 35 having compact structure through heat treatment at 600-800 deg.C in an inert gas atmosphere or an oxidizing atmosphere. Accordingly, an electrode is formed on the film 35, and MOS capacitance is shaped.

Description

【発明の詳細な説明】 本発明は、’ Ta205. Tie2などの比誘電率
の高い誘電体膜の形成方法に関し、特に、膜中を流れる
リーク電流が少く、また絶縁耐圧の高い誘電体膜を形成
する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides 'Ta205. The present invention relates to a method of forming a dielectric film with a high relative permittivity such as Tie2, and particularly relates to a method of forming a dielectric film with a low leakage current flowing through the film and a high dielectric strength.

近年、MO8型半導体装置が広く用いられ、その集積度
は年々高密度化が計られている。従来、高密度化はパタ
ーンを微細化することによシ行なわれてきた。しかし、
ダイナミ、り・ランダムアクセスメモリ(DRAM)の
如き半導体装置ズは、パターンの微細化は信号に対応し
た蓄積電荷量の低下を招き、α線などの放射線によるメ
モリの誤動作(ン7トエ2−)が発生するという問題が
生じている。このため、パターンを微細化しても蓄積電
荷量を低下させない手段を講する必要がある。
In recent years, MO8 type semiconductor devices have been widely used, and their integration density is increasing year by year. Hitherto, densification has been achieved by making patterns finer. but,
In semiconductor devices such as dynamic and random access memories (DRAMs), miniaturization of patterns leads to a decrease in the amount of accumulated charge corresponding to signals, and memory malfunctions due to radiation such as alpha rays (N7 toe 2-). The problem is that this occurs. Therefore, it is necessary to take measures that do not reduce the amount of accumulated charge even if the pattern is made finer.

従来、電荷を蓄積す、BMO8容愈部分の絶縁膜を薄く
シ、容量値を従下させないことで対処していた。しかし
、絶縁膜が薄くなるとピンホールが増大するため充分な
耐圧が得られず歩留9が低圧するなど、薄膜化にも限界
があった。
Conventionally, this problem has been dealt with by making the insulating film in the BMO8 capacitor part, which stores charge, thinner so that the capacitance value does not decrease. However, as the insulating film becomes thinner, the number of pinholes increases, making it impossible to obtain a sufficient withstand voltage, resulting in a low yield rate of 9, and there are limits to making the film thinner.

通常、容量部分の絶縁膜を構成する誘電体材料として、
比誘電率3.9の8i0.が用いられているが、比誘電
率の高い材料を用いれば同じ電極面積でも容量を大きく
することが可能となり、従って、い、そうの微細化が可
能となる。仁のため、すでに、 Ta2O,、Tie、
などの高誘電材料が検討されてきた。これらの膜を形成
する手段は、例えばTa。
Usually, as a dielectric material that constitutes the insulating film of the capacitive part,
8i0. with a dielectric constant of 3.9. However, if a material with a high dielectric constant is used, it is possible to increase the capacitance even with the same electrode area, and therefore, it becomes possible to miniaturize the electrode. For Jin, we already have Ta2O,, Tie,
High dielectric materials such as The means for forming these films is, for example, Ta.

Tiなどの金属材料を真空中で蒸着した後、酸素雰囲気
中で熱処理、あるいは陽極酸化などの手段で酸化するこ
とによシ、もしくはTa2O,、TiO2などの絶縁物
質を、真空中でスバ、り蒸着する、あるいは気相成長法
により堆積するなどの手段で形成されている。しかしな
がら、これらの手段を用いて形成された膜は、低電圧の
印加でリーク電流が多く流れるため、末だ実用に耐える
段階に至っていない。
After depositing a metal material such as Ti in a vacuum, it is oxidized by heat treatment in an oxygen atmosphere or by anodic oxidation, or an insulating material such as Ta2O, TiO2 is deposited in a vacuum. It is formed by vapor deposition or deposition using a vapor phase growth method. However, films formed using these methods have not reached the stage where they can be put to practical use because a large amount of leakage current flows when a low voltage is applied.

この原因としては、形成された絶縁膜が多結晶構造にな
っており、その結晶粒界を通じてリーク電流が流れるも
のと考えられる0従りて、膜構造を多結晶構造にしない
手段t−講ずればリーク電流を低減できるのではないか
と本発明者は考えた。
The reason for this is thought to be that the formed insulating film has a polycrystalline structure, and leakage current flows through the grain boundaries. The inventor thought that leakage current could be reduced.

本発明は、かかる考察にもとづき半導体装置において従
来の方法によって形成した高比誘電率の絶縁膜の絶縁耐
圧が低くリーク電流が大きいという欠点を排除し、高品
質の膜を実現する手段を提供することにある。すなわち
、本発明は半導体基板表面、もしくは該半導体基板上に
設けられた第1の絶縁膜の表面に第2の絶縁膜を設け、
次に該第2の絶縁膜表面に加速せしめたイオンを照射す
ることによp1該第2の絶縁膜を非晶質化し、続いて熱
処理を行うことによシ、該第2の絶縁膜を緻密な膜とす
る工程を有することを特徴とする半導体装置の製造方法
に関するものである。
Based on this consideration, the present invention eliminates the drawbacks of low dielectric strength voltage and large leakage current of high dielectric constant insulating films formed by conventional methods in semiconductor devices, and provides means for realizing high-quality films. There is a particular thing. That is, the present invention provides a second insulating film on the surface of a semiconductor substrate or on the surface of a first insulating film provided on the semiconductor substrate,
Next, the second insulating film is made amorphous by irradiating the surface of the second insulating film with accelerated ions, and then heat treatment is performed to make the second insulating film amorphous. The present invention relates to a method of manufacturing a semiconductor device characterized by including a step of forming a dense film.

以下、本発明を実施例を用いて詳細に説明する。Hereinafter, the present invention will be explained in detail using examples.

第1図ないし第3図は、MO8型容量の形成に本発明を
適用した場合を例にとシ、その工程を説明するための断
面構造図である。図において1は半導体基板、2は第1
の絶縁膜、3は第2の絶縁膜、4はイオンの飛来方向を
それぞれ示す。以下、半導体基板lとしてシリコン基板
を、第1の絶縁膜2としてSin、を、第2の絶縁膜3
としてTa、0.。
FIGS. 1 to 3 are cross-sectional structural views for explaining the process, taking as an example the case where the present invention is applied to forming an MO8 type capacitor. In the figure, 1 is the semiconductor substrate, 2 is the first
3 indicates the second insulating film, and 4 indicates the ion flying direction. Hereinafter, a silicon substrate will be used as the semiconductor substrate l, a silicon substrate will be used as the first insulating film 2, and a silicon substrate will be used as the second insulating film 3.
As Ta, 0. .

膜を用いたMO8容量の製造工程を順を追って説明する
The manufacturing process of an MO8 capacitor using a membrane will be explained step by step.

まず、シリコン基板1の表面にSin、膜2が、続いて
’ra、o、膜3が形成される(第1図)os’02膜
2は、 Ta1O,膜3を形成す之過程でシリコン基板
1との反応を防止するために設けられるものであるが、
比誘電率が3.9と小さいので、大きなMO8容量を構
成する上から薄いことが望ましく、50〜100への膜
厚にするのが好ましい。また、Ta、0.膜3は、例え
ばTaを真空中で蒸着した後に、酸素雰囲気中で熱処理
する、あるいは陽極酸化をするなどの手段、もしくはT
a2O5を真空中でスバ、り蒸着する、あるいは気相成
長法により堆積するなどの手段のいずれを用いて形成し
ても選択は自由である0当然Ta 、 0.膜3も大き
なMO8容量を得るためには薄い方が望ましく、200
〜500八程度の膜厚が好ましい0形成した’ra、o
First, a Sin film 2 is formed on the surface of a silicon substrate 1, and then a 'ra, o film 3 is formed (Fig. 1). Although it is provided to prevent reaction with the substrate 1,
Since the dielectric constant is as small as 3.9, it is desirable that the film be thin in order to form a large MO8 capacitance, and the film thickness is preferably 50 to 100. Also, Ta, 0. The film 3 can be formed by, for example, depositing Ta in a vacuum and then heat-treating it in an oxygen atmosphere or anodizing it, or by depositing Ta in a vacuum.
A2O5 can be formed by vapor deposition in a vacuum or by vapor phase epitaxy, which can be freely selected.Of course, Ta, 0. The membrane 3 is also preferably thinner in order to obtain a large MO8 capacity, and the thickness of the membrane 3 is 200
It is preferable that the film thickness is about ~5008.
.

膜3は、X線解析によれば非晶質構造であると観察され
るが、電気的特性評価からは完全な非晶質とはなってい
ない0 次にs At、 02+ Taなどの物質をイオンとな
し、前記Ta*O,膜3にイオン打込みすることによシ
Ta、0.膜3は非晶質な構造を持つ’ra、o、膜3
1に変えらレル(第2図)o Ta1O,膜3は薄膜で
あるので、イオン打込みは例えば加速電圧10〜50K
eVの条件でドース量10〜10 備のイオンを打込め
ば充分良質の非晶質膜が形成される0 前記イオン打込みではTa、Os膜3の厚さ方向全体が
充分に非晶質となるように、加速電圧を変化せしめてイ
オン打込みしても良い。この時、前記シリコン基板1の
表面も非晶質化されるが、後の工程で熱処理を行うこと
によ多結晶性が回復するので実用上問題とはならない。
Film 3 is observed to have an amorphous structure according to X-ray analysis, but it is not completely amorphous from electrical property evaluation. By implanting ions into the Ta*O film 3, Ta, 0. Film 3 has an amorphous structure.
Since the film 3 is a thin film, the ion implantation is performed at an acceleration voltage of 10 to 50K, for example.
If ions are implanted at a dose of 10 to 10 eV under the condition, an amorphous film of sufficient quality will be formed. With the above ion implantation, the entire thickness direction of the Ta, Os film 3 becomes sufficiently amorphous. Ion implantation may be performed by changing the acceleration voltage as shown in FIG. At this time, the surface of the silicon substrate 1 is also made amorphous, but this does not pose a practical problem since the polycrystallinity is restored by heat treatment in a later step.

またTa、0.膜3の表面にイオン打込みのマスクとな
るマスク膜のノくターンを設はタンク1mの一部分にの
みイオン打込みを行なってもよい。なお前記イオン打込
みでは、ヒ素、リン、ボロyなどの不純物イオンを打込
むことによっても、前記Ta、0.膜3を非晶質化する
ことは可能でアシ、この場合にはシリコン基板10表面
に不純物領域の形成は、本発明を他の構造の半導体装置
に適用する場合の応用範囲が広くなシ好ましい。
Also, Ta, 0. Ion implantation may be performed only in a portion of the tank 1 m by providing a mask film notch on the surface of the membrane 3 to serve as a mask for ion implantation. In the ion implantation, the Ta, 0. It is possible to make the film 3 amorphous, but in this case, forming an impurity region on the surface of the silicon substrate 10 is preferable since the present invention can be applied to a wide range of semiconductor devices with other structures. .

非晶質Ta、O,膜31が形成された後、不活性ガス雰
囲気中もしくは酸化雰i気中600〜800℃の温度で
熱処理することによシ、非晶質Ta、0.膜31が緻密
な構造を持つTa 、 05膜35に変えられる(第3
図)。この後、緻密な構造を持つTa20゜膜35表面
に電極が形成され、MO8容量が形成される。
After the amorphous Ta, O. film 31 is formed, the amorphous Ta, O. The film 31 is changed to a Ta,05 film 35 with a dense structure (third
figure). Thereafter, an electrode is formed on the surface of the Ta20° film 35 having a dense structure, and an MO8 capacitor is formed.

本発明を用いて形成したMOB容量のリーク電流量を調
べたところ、従来法に比べ約2桁リーク電流が低減し、
充分良好の膜が形成されることが判明した。この効果は
、’ra、o、膜をいったん完全な非晶質膜に変えたこ
とにあることは明らかである0 なお、上記説明では誘電体材料としてTa、0.膜を形
成するとして説明したが、本発明はTie、。
When the amount of leakage current of the MOB capacitor formed using the present invention was investigated, the leakage current was reduced by about two orders of magnitude compared to the conventional method.
It was found that a sufficiently good film was formed. It is clear that this effect is due to the fact that the 'ra, o, film is once changed to a completely amorphous film. In the above explanation, the dielectric material is Ta, 0. Although it has been described that a film is formed, the present invention is based on Tie.

MgO,Nb、O,などの誘電体、もしくはBaTiO
sなどの強誘電体にも同様に適用ができる。
Dielectric materials such as MgO, Nb, O, or BaTiO
The present invention can be similarly applied to ferroelectric materials such as s.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の一実施例を説明するだめ
の各工程における半導体装置の断面図である。1・・・
・・・半導体基板、2・・・・・・第1の絶縁膜、3・
・・・・・第2の絶縁膜、4・・・・・・イオンの飛来
方向、31・・・・・・非晶質化された第2の絶縁膜、
35・・・・・・緻密な構造を持つ第2の絶縁膜。
1 to 3 are cross-sectional views of a semiconductor device at various steps for explaining an embodiment of the present invention. 1...
... Semiconductor substrate, 2... First insulating film, 3.
... second insulating film, 4 ... ion flying direction, 31 ... amorphous second insulating film,
35...Second insulating film with a dense structure.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面、もしくは該半導体基板上に設けられた
第1の絶縁膜の表面に第2の絶縁膜を設け、次に該第2
の絶縁膜表面に加速せしめたイオンを照射することによ
シ、該第2の絶縁膜を非晶質化し、続いて熱処理を行う
ことによシ該第2の絶縁膜を緻密な膜とする工程を有す
ることを特徴とする半導体装置の製造方法。
A second insulating film is provided on the surface of the semiconductor substrate or the surface of the first insulating film provided on the semiconductor substrate, and then the second insulating film is
The second insulating film is made amorphous by irradiating the surface of the insulating film with accelerated ions, and then heat treatment is performed to make the second insulating film a dense film. 1. A method for manufacturing a semiconductor device, comprising the steps of:
JP21662983A 1983-11-17 1983-11-17 Manufacture of semiconductor device Pending JPS60107838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21662983A JPS60107838A (en) 1983-11-17 1983-11-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21662983A JPS60107838A (en) 1983-11-17 1983-11-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60107838A true JPS60107838A (en) 1985-06-13

Family

ID=16691423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21662983A Pending JPS60107838A (en) 1983-11-17 1983-11-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60107838A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160155A (en) * 1984-01-30 1985-08-21 Nec Corp Method for forming capacitance element
JPH01128530A (en) * 1987-11-13 1989-05-22 Fujitsu Ltd Manufacture of semiconductor device
KR100351450B1 (en) * 1999-12-30 2002-09-09 주식회사 하이닉스반도체 Non-volatile memory device and method for fabricating the same
US7042033B2 (en) 1998-06-30 2006-05-09 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160155A (en) * 1984-01-30 1985-08-21 Nec Corp Method for forming capacitance element
JPH0367346B2 (en) * 1984-01-30 1991-10-22 Nippon Electric Co
JPH01128530A (en) * 1987-11-13 1989-05-22 Fujitsu Ltd Manufacture of semiconductor device
US7042033B2 (en) 1998-06-30 2006-05-09 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator
KR100351450B1 (en) * 1999-12-30 2002-09-09 주식회사 하이닉스반도체 Non-volatile memory device and method for fabricating the same

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