JPS60160155A - Method for forming capacitance element - Google Patents
Method for forming capacitance elementInfo
- Publication number
- JPS60160155A JPS60160155A JP1463384A JP1463384A JPS60160155A JP S60160155 A JPS60160155 A JP S60160155A JP 1463384 A JP1463384 A JP 1463384A JP 1463384 A JP1463384 A JP 1463384A JP S60160155 A JPS60160155 A JP S60160155A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- electrode
- capacitance element
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 238000001947 vapour-phase growth Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、Ｔａｇ’ｓ、Ｔｉ０ｚ などの誘電体膜を用
いた容量の形成方法に関し、特に、膜中ｔ−流れるリー
ク電流が少＜、また絶縁耐圧の高い誘電体薄膜を形成す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a capacitor using a dielectric film such as Tag's or TiOz, and particularly relates to a method for forming a capacitor using a dielectric film such as Tag's or TiOz, and in particular, a method for forming a capacitor using a dielectric film with a low leakage current flowing in the film and a high dielectric strength. The present invention relates to a method of forming a thin film.
近年、ＭＯ８型半導体装置が広く用いられ、その集積度
は年々高密度化が計られている。従来。In recent years, MO8 type semiconductor devices have been widely used, and their integration density is increasing year by year. Conventional.
高密度化はパターンを微細化することにより行なわれて
きた。しかし、ダイナミック・ランダムアクセスメモリ
（ＤＲＡＭ）の如き半導体装置では、パターンの微細化
は信号に対応した蓄積電荷量の低下を招き、α線などの
放射線によるメモリの誤動作（ソフトエラー）が発生す
るという問題を生ずる。このため、パターンを微細化し
ても蓄積電荷量を低下させない手段を講する必要がある
。従来、電荷を蓄積する容量部分の絶縁膜を薄くシ。High density has been achieved by making patterns finer. However, in semiconductor devices such as dynamic random access memories (DRAMs), miniaturization of patterns leads to a decrease in the amount of stored charge corresponding to signals, which can lead to memory malfunctions (soft errors) due to radiation such as alpha rays. cause problems. Therefore, it is necessary to take measures that do not reduce the amount of accumulated charge even if the pattern is made finer. Conventionally, the insulating film in the capacitor area that stores charge was made thinner.
−量値を低下させないことで対処していた。しかし、膜
が薄くなるとピンホールが増大するため充分な耐圧が得
られず歩留りが低下するなど薄膜化にも限界があった。-The problem was dealt with by not reducing the quantity value. However, as the film becomes thinner, the number of pinholes increases, making it impossible to obtain a sufficient withstand voltage and lowering the yield.There are limits to thinning the film.
通常、容量部分の誘電体材料として、比誘電率３．９の
５ｉ０２が用いられているが、比誘電率の高い材料を用
いれば同じ電極面積でも容量を大きくすることが可能と
なシ、従って、いっそうの微細化が可能となる。このた
め、すでに、Ｔａ２０５゜ＴｉＯ２などの高誘電材料が
検討されてきた。これらの膜を形成する手段は、例えば
Ｔａ、 Ｔｉなどの金属材料を真空中で蒸着した後、酸
素雰囲気中で熱処理する、あ之いは、陽極酸化する、な
どの手段で酸化することにより、もしくはＴａ２０５．
Ｔｉ０ｚなどの物質を真空中でスパッタ蒸着する、ある
いはＣＶＤ法を用いて堆積するなどの手段で形成されて
いる。しかしながら、これらの手段を用いて形成された
膜は、低電圧の印加でリーク電流が多く流れるため、未
だ笑用に耐える段階に至っていない。Normally, 5i02 with a dielectric constant of 3.9 is used as the dielectric material for the capacitor part, but if a material with a high dielectric constant is used, it is possible to increase the capacitance with the same electrode area. , further miniaturization becomes possible. For this reason, high dielectric materials such as Ta205°TiO2 have already been considered. The means for forming these films is, for example, by depositing a metal material such as Ta or Ti in a vacuum and then oxidizing it by heat treatment in an oxygen atmosphere, or by anodizing. Or Ta205.
It is formed by sputter deposition of a substance such as Ti0z in a vacuum or by CVD. However, films formed using these methods have not yet reached a stage where they can withstand commercial use because a large amount of leakage current flows when a low voltage is applied.
この原因としては、蒸着された金属膜が結晶粒構造をも
っており、酸化により形成された誘電体膜も多結晶構造
になっていると考えられ、結晶粒界を通じてリーク電流
が流れるものと考えられる。The reason for this is thought to be that the deposited metal film has a crystal grain structure, and the dielectric film formed by oxidation also has a polycrystalline structure, and that leakage current flows through the grain boundaries.
従って、膜構造を多結晶構造にし々い手段を構すればリ
ーク電流を低減できるのではないかと本発明者は考えた
。Therefore, the inventor thought that the leakage current could be reduced by making the film structure a polycrystalline structure.
本発明は、かかる考察にもとづき従来の方法によって形
成した膜の絶縁耐圧が低くリーク電流が大きいという欠
点を排除した高品質の膜を実現する手段を提供すること
にあシ、その要旨はいったん形成した絶ｌｉｉ＆膜を完
全に非晶質な絶縁膜にする手段を行うことにある。Based on this consideration, the present invention aims to provide a means for realizing a high-quality film that eliminates the drawbacks of low dielectric strength and large leakage current of films formed by conventional methods. The object of the present invention is to provide a means for converting a completely amorphous insulating film into a completely amorphous insulating film.
本発明の特徴は、表面の一部に第１の絶縁膜を設けた半
導体基板上に第１の電極膜パターンを設け１次に該第１
の電極膜パターンの表面を含む前記第１の絶縁膜表面に
、もしくは該第１の電極膜パターンの表面あるいは該第
１の電極膜パターンの表面を含む前記第１の絶縁膜の表
面にいったん第２の絶縁膜を設けた後に当該第２の絶縁
膜表面に、又は当賦第２の絶縁膜表面を含む前記第１の
絶縁膜表面に、ｆＪｃ３の絶縁膜上膜け、次に、該第３
の絶縁膜表面に加速せしめたイオンを照射することによ
ル轟該ｌ＠３の絶縁膜を非晶質の絶縁膜となし、続いて
当該非晶、質の絶縁膜を熱処理した後に前記１１！１の
電極膜の一部をおおう領域の当該第３の絶縁膜表面に第
２の電極膜を設けることにより、前記１ｍ！１の電極膜
と第２の電極膜との間に容量を構成する容量の形成方法
にある。A feature of the present invention is that a first electrode film pattern is provided on a semiconductor substrate having a first insulating film provided on a part of the surface.
Once on the surface of the first insulating film including the surface of the electrode film pattern, or on the surface of the first insulating film including the surface of the first electrode film pattern or the surface of the first electrode film pattern, After providing the second insulating film, an insulating film of fJc3 is formed on the surface of the second insulating film or on the surface of the first insulating film including the second insulating film surface; 3
By irradiating the surface of the insulating film with accelerated ions, the insulating film of 1. By providing the second electrode film on the surface of the third insulating film in the area covering a part of the electrode film of !1, the 1 m! A method of forming a capacitor constitutes a capacitor between a first electrode film and a second electrode film.
次に本発明の詳細な説明する。Next, the present invention will be explained in detail.
第１図は１本発明を用いて容量を形成する場合の一実施
例を示しており、その製作工程を説明するための断面構
造を示している０図において、１は半導体基板、２およ
び２２は絶縁膜、３は電極、４は不純物領域、５および
５６は絶縁膜、６はイオンの飛来方向、７は電極をそれ
ぞれ示す、半導体基板１としてシリコンを、電極３とし
て多結晶シリコンを絶縁膜５としてＴａ２０５を用いて
容量を作る工程を順を追って説明する。FIG. 1 shows an example of forming a capacitor using the present invention, and in FIG. 3 is an insulating film, 3 is an electrode, 4 is an impurity region, 5 and 56 are insulating films, 6 is an ion flying direction, and 7 is an electrode. The semiconductor substrate 1 is made of silicon, and the electrode 3 is made of polycrystalline silicon. 5, the process of creating a capacitor using Ta205 will be explained step by step.
まず、−導電型を有するシリコン基板ｌの表面に５ｉＵ
２などの絶縁膜２が設けられ、続いて当該絶縁膜２の一
部が選択除去され窓２５が形成される（第１図（ａ）
）。First, 5iU was applied to the surface of a silicon substrate l having a − conductivity type.
An insulating film 2 such as 2 is provided, and then a part of the insulating film 2 is selectively removed to form a window 25 (FIG. 1(a)).
).
次に、絶縁膜２をマスクとして窓２５からシリコン基板
の表面に不純物が導入され、該基板１と逆の導電型を有
する不純物領域４が形成され、続いて多結晶シリコン膜
３が気相成長法などの手段を用いて形成されるＣｌｒｌ
図（ｂ） ）、該不純物の導入は、熱拡散法を用いても
、あるいはイオン打込法を用いても良くその選択は自由
である。該不純物領域４は電極として用いるため、高濃
度に形成される必要がある。また、多結晶シリコン膜３
は電極として用いるため、不純物を高濃度に含ませる必
要がある。かかる不純物の導入は熱拡散法を用いても、
あるいはイオン打込み法を用いても良く、さらに多結晶
シリコン膜形成時に雰囲気中に含ませても良く、その選
択は自由である。なお、窓２５が形成された後に不純物
領域４を形成せずに多結晶シリコン膜３を形成し、続い
て当該多結晶シリコン膜中に半導体基板１と逆型の不純
物を高濃度に導入し熱処理することにより不純物領域４
を形成しても良く、その選択は自由である。なお、第１
図１ｂ）の構造を形成した後に、多結晶シリコン膜３を
選択的に除去し多結晶パターンとしても良い。Next, impurities are introduced into the surface of the silicon substrate through the window 25 using the insulating film 2 as a mask, and an impurity region 4 having a conductivity type opposite to that of the substrate 1 is formed. Subsequently, a polycrystalline silicon film 3 is grown by vapor phase growth. Clrl formed using methods such as
In Figure (b)), the impurity may be introduced using a thermal diffusion method or an ion implantation method, and the choice is free. Since the impurity region 4 is used as an electrode, it needs to be formed at a high concentration. In addition, polycrystalline silicon film 3
Since it is used as an electrode, it is necessary to contain impurities at a high concentration. Even if the thermal diffusion method is used to introduce such impurities,
Alternatively, an ion implantation method may be used, and furthermore, it may be included in the atmosphere when forming the polycrystalline silicon film, and the selection is free. Note that after the window 25 is formed, the polycrystalline silicon film 3 is formed without forming the impurity region 4, and then an impurity of the type opposite to that of the semiconductor substrate 1 is introduced into the polycrystalline silicon film at a high concentration and then heat-treated. By doing so, the impurity region 4
may be formed, and the choice is free. In addition, the first
After forming the structure shown in FIG. 1b), the polycrystalline silicon film 3 may be selectively removed to form a polycrystalline pattern.
次に、前記多結晶シリコン膜３の表面に８ｉ０２などの
絶縁膜２２を形成し、続いて当該絶縁膜２２の表面にＴ
ａ２０５膜５が設けられ、続いて＠ Ａｒ。Next, an insulating film 22 such as 8i02 is formed on the surface of the polycrystalline silicon film 3, and then T
A205 membrane 5 is provided followed by @Ar.
０２． Ｔａ、 Ｍｏ、 Ｔｉ、 Ｐｔ、 Ｗなどの物
質もしくはＡｓ５Ｐ、Ｂなどの不純物として働く物質６
が、当該膜５にイ′オン打込みされ、当該膜５が非晶質
の構造を持つ非晶質’ｌ’！２０３膜５６に変えられる
（第１図ｆｃ）Ｌ Ｔａｓ＋Ｏｓ膜５の形成は、例えば
Ｔａｉ真空中でスバ、り蒸着した後に、酸素雰囲気中で
熱処理する。あるいは陽極酸化をするなどの手段で酸化
することによシ、もしくはＴａ２０５’ｉ真空中でスパ
ッタ蒸着する、あるいは気相成長法により堆積するなど
のうちでいずれの手段を用いても選択は自由である。絶
縁膜２２は、多結晶シリコン膜３とＴａ２Ｑｓ膜５との
反応を防止するために設けられるものであり、大きな容
ｔ’を得る上では当該膜２２は薄く形成される必要があ
り、好ましい膜厚は５０〜１００Ａであるｅ ｔｆｒ−
１Ｔａ２０ｓ膜５は大きな容量を得る上から薄くよるの
が望ましく％ １００〜５００Ａの膜厚であることが好
ましい、イオン打込みの好ましい条件は、電圧１０〜５
０ＫｅＶ、打込量１０ 〜１０ ｃｍ である。02. Substances such as Ta, Mo, Ti, Pt, and W, or substances that act as impurities such as As5P and B6
is ion-implanted into the film 5, and the film 5 becomes an amorphous 'l'! having an amorphous structure. The L Tas+Os film 5, which is converted into the 203 film 56 (FIG. 1fc), is formed by, for example, vapor deposition in a Tai vacuum, followed by heat treatment in an oxygen atmosphere. Alternatively, you are free to choose which method you want to use, such as oxidizing it by anodic oxidation, sputtering Ta205'i in a vacuum, or depositing it by vapor phase growth. be. The insulating film 22 is provided to prevent the reaction between the polycrystalline silicon film 3 and the Ta2Qs film 5, and in order to obtain a large capacitance t', the film 22 needs to be formed thinly, and a preferable film is The thickness is 50-100A.
The 1Ta20s film 5 is desirably thin in order to obtain a large capacity, and preferably has a film thickness of 100 to 500 A. The preferred conditions for ion implantation are a voltage of 10 to 5%.
0 KeV, and the implantation amount was 10 to 10 cm.
なお、Ｔａ２０５膜５の表面から奥まで全域を充分に非
晶質化するべく、加速電圧を稲々変化させてイオン打込
みしても良い、さらに、当該イオン打込みは、前記Ｔａ
２０５膜５を選択的に除去し、パターンとなした後に行
りても良い。In addition, in order to sufficiently make the entire area from the surface to the depths of the Ta205 film 5 amorphous, ion implantation may be performed by changing the accelerating voltage.
This may be performed after selectively removing the 205 film 5 and forming a pattern.
次に、６００〜８００℃の不活性ガス雰囲気中もしくは
酸素あるいは水分を含む雰囲気中で熱処理を行い、続い
て電極パターン７が形成されることによシ多結晶シリコ
ン膜３、絶縁ｒｍ ２２ 、 Ｔａ２’ｓ膜５６．電極
７との間に容量が形成される（第１図（ｄ）。Next, heat treatment is performed in an inert gas atmosphere at 600 to 800°C or in an atmosphere containing oxygen or moisture, and then an electrode pattern 7 is formed, thereby removing the polycrystalline silicon film 3, the insulation rm22, and Ta2. 's membrane 56. A capacitance is formed between the electrode 7 and the electrode 7 (FIG. 1(d)).
当該実施例では、多結晶電極膜３と高濃度不純物領域４
とはオーム接触であるため、高濃度不純物領域４と電極
７との間に電圧全印加することで容量として機能させる
ことが出来る特徴を持つ。In this embodiment, a polycrystalline electrode film 3 and a high concentration impurity region 4
Since this is an ohmic contact, it has the characteristic that it can function as a capacitor by applying a full voltage between the high concentration impurity region 4 and the electrode 7.
上記した実施例では、絶縁膜５としてＴａ２０５膜を形
成することとして説明したが、これは他の絶縁膜例えば
ＭｇＯ，Ｔｉ０ｚ、 Ｍｂ２０ｓ などの絶縁膜を用い
る場合でも、さらにＢａＴｉ０ａ などの強誘電体膜を
用いる場合でも不発明は適用できる。In the above embodiment, a Ta205 film is formed as the insulating film 5, but this also applies when other insulating films such as MgO, Ti0z, Mb20s, etc. are used, or a ferroelectric film such as BaTi0a is used. Non-invention can be applied even when using.
また、電極３として多結晶シリコン膜を用いることとし
て説明したが、これはＭｏ、 Ｔｉ、 Ｐｔ、 Ｗなど
の金属を用いても、あるいはシリコンとの合金膜（シリ
サイド）を用いても本発明に適用できる拳
また、絶縁膜２２として８ｉ０ｚを用いて説明したが、
これは５ｉａＮ４などの絶縁膜を用いても良く、さらに
、当該絶縁膜２２は電極３と絶縁膜５との反応を防止す
るために用いられるものであシ、電極３と絶縁膜５とが
反応しない物質の組合せ。In addition, although the explanation has been made based on the use of a polycrystalline silicon film as the electrode 3, the present invention can also be applied to the use of metals such as Mo, Ti, Pt, W, or an alloy film (silicide) with silicon. In addition, although the explanation has been made using 8i0z as the insulating film 22,
An insulating film such as 5iaN4 may be used for this, and the insulating film 22 is used to prevent the reaction between the electrode 3 and the insulating film 5. Combinations of substances that do not.
例えば電極３としてＭｏ５ｉｔ−１絶縁膜５としてＴａ
２０５を用いた場合には設ける必要はない。For example, Mo5it-1 is used as the electrode 3; Ta is used as the insulating film 5;
205, it is not necessary to provide it.
第１図は、本発明の一実施例を説明するための断面図で
ある。
図において、１は半導体基板、２は絶縁膜、３は電極、
４は不純物領域、５は絶縁膜、６はイオンの飛来方向、
７は電極、２５は窓、２２は絶縁膜、５６は非晶質膜、
をそれぞれ示す。
篤 ／ 図FIG. 1 is a sectional view for explaining one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is an electrode,
4 is an impurity region, 5 is an insulating film, 6 is an ion flying direction,
7 is an electrode, 25 is a window, 22 is an insulating film, 56 is an amorphous film,
are shown respectively. Atsushi/Figure
Claims (1)
の電極膜パターンを設け５次に該第１の電極膜上に第２
の絶縁膜を設け、該第２の絶縁膜上に第３の絶縁膜を設
け、しかる後、該第３の絶縁膜表面に加速せしめたイオ
ンを照射することによフ該第３の絶縁膜を非晶質の絶縁
膜となし１次に該非晶質の絶縁膜を熱処理した後に該第
３の絶縁膜表面に第２の電極膜を設けることにより、前
記第１の電極膜と第２の一極膜との間に容量を構成する
こと′ｆｒ、特徴とした容量の形成方法。A first insulating film is formed on a semiconductor substrate with a first insulating film provided on a part of the surface.
A second electrode film pattern is provided on the first electrode film.
A third insulating film is provided on the second insulating film, and then the third insulating film is removed by irradiating the surface of the third insulating film with accelerated ions. is made into an amorphous insulating film, firstly, the amorphous insulating film is heat-treated, and then a second electrode film is provided on the surface of the third insulating film. Forming a capacitor between a monopolar film and a monopolar film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1463384A JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1463384A JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60160155A true JPS60160155A (en) | 1985-08-21 |
| JPH0367346B2 JPH0367346B2 (en) | 1991-10-22 |
Family
ID=11866596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1463384A Granted JPS60160155A (en) | 1984-01-30 | 1984-01-30 | Method for forming capacitance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160155A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128167A (en) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | Capacitor |
| US4813626A (en) * | 1986-11-17 | 1989-03-21 | Ryobi Limited | Drag control device in spinning type fishing reel |
| US4943012A (en) * | 1987-02-09 | 1990-07-24 | Ryobi Ltd. | Double bearing fishing reel |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60107838A (en) * | 1983-11-17 | 1985-06-13 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-01-30 JP JP1463384A patent/JPS60160155A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60107838A (en) * | 1983-11-17 | 1985-06-13 | Nec Corp | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128167A (en) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | Capacitor |
| US4813626A (en) * | 1986-11-17 | 1989-03-21 | Ryobi Limited | Drag control device in spinning type fishing reel |
| US4943012A (en) * | 1987-02-09 | 1990-07-24 | Ryobi Ltd. | Double bearing fishing reel |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0367346B2 (en) | 1991-10-22 |
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