JPH0652774B2 - Thin film capacitor - Google Patents
Thin film capacitorInfo
- Publication number
- JPH0652774B2 JPH0652774B2 JP24687890A JP24687890A JPH0652774B2 JP H0652774 B2 JPH0652774 B2 JP H0652774B2 JP 24687890 A JP24687890 A JP 24687890A JP 24687890 A JP24687890 A JP 24687890A JP H0652774 B2 JPH0652774 B2 JP H0652774B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric
- thin film
- electrode
- film capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコン電極上に形成された薄膜キャパシタの
構造に関し、特にシリコン電極上に第１及び第２の材料
からなる導電層が形成され、その上に誘電体薄膜及び上
部電極が順に積層形成された構造を有する薄膜キャパシ
タに関する。Description: TECHNICAL FIELD The present invention relates to a structure of a thin film capacitor formed on a silicon electrode, and in particular, a conductive layer made of a first material and a second material is formed on the silicon electrode, The present invention relates to a thin film capacitor having a structure in which a dielectric thin film and an upper electrode are sequentially stacked.
従来、この種の薄膜キャパシタとしては、シリコン電極
上に直接にスパッタ法により誘電体膜，上部電極を順に
積層形成した構造（特願平1-217918号）、又はシリコン
電極上にTa,Tiなどの少なくとも１種類の高融点金属か
らなる第１層及びPt,Pdの少なくとも１種の材料からな
る第２層とから構成される導電層上に誘電体膜、上部電
極を順に積層形成した構造（特願平1-238484号）のもの
がある。Conventionally, as a thin film capacitor of this type, a structure in which a dielectric film and an upper electrode are sequentially laminated directly on a silicon electrode by a sputtering method (Japanese Patent Application No. 1-217918), or Ta, Ti, etc. are formed on the silicon electrode. A structure in which a dielectric film and an upper electrode are sequentially stacked on a conductive layer composed of a first layer composed of at least one kind of refractory metal and a second layer composed of at least one material of Pt and Pd ( Japanese Patent Application No. 1-238484).
〔発明が解決しようとする課題〕 上述した従来の構造の薄膜キャパシタにおいて、シリコ
ン電極上に直接にスパッタ法により誘電体を形成した場
合には、シリコン電極表面が誘電体を形成するときに酸
化され誘電率の高い誘電体を形成してもシリコン電極と
誘電体との界面に存在する低誘電率の二酸化シリコンの
ために薄膜キャパシタ全体の容量を大きくすることが制
限されるという欠点がある。また、シリコン電極に第１
及び第２の材料からなる導電層を形成し、その上に誘電
体、上部電極を順に積層形成した構造の場合には、誘電
体膜の堆積時及び熱処理時にシリコン電極からシリコン
が第１の導電層を拡散して第２の導電層に達し、第２の
導電層の材料とシリサイドを形成し、さらに誘電体との
界面に低誘電率の酸化物を形成することとなり、薄膜キ
ャパシタ全体の容量を大きくするためには、シリコン電
極からのシリコンが第２の導電層へ拡散するのを制御す
る必要があり、第２の導電層の厚みを十分に厚くし、ま
た誘電体膜の堆積及び熱処理温度の上限を制限しなけれ
ばならないが、導電層を厚くすると薄膜キャパシタ素子
製作プロセスにおいて導電層の加工性が悪くなり、また
誘電体膜の堆積及び熱処理温度の上限を制限すると誘電
体膜自身の誘電率を大きくすることが困難になるという
欠点がある。[Problems to be Solved by the Invention] In the above-mentioned conventional thin film capacitor, when a dielectric is directly formed on the silicon electrode by a sputtering method, the surface of the silicon electrode is oxidized when the dielectric is formed. Even if a dielectric having a high dielectric constant is formed, there is a drawback that the capacitance of the entire thin film capacitor is limited due to the low dielectric constant silicon dioxide existing at the interface between the silicon electrode and the dielectric. In addition, the first
In the case of a structure in which a conductive layer made of a second material is formed and a dielectric and an upper electrode are sequentially stacked on the conductive layer, silicon is first conductive from the silicon electrode during deposition of the dielectric film and heat treatment. The layer diffuses to reach the second conductive layer, forms a silicide with the material of the second conductive layer, and further forms an oxide having a low dielectric constant at the interface with the dielectric. In order to increase the thickness, it is necessary to control the diffusion of silicon from the silicon electrode into the second conductive layer, the thickness of the second conductive layer should be made sufficiently thick, and the deposition and heat treatment of the dielectric film should be performed. Although the upper limit of the temperature must be limited, if the conductive layer is thickened, the workability of the conductive layer deteriorates in the thin film capacitor element manufacturing process, and if the upper limit of the deposition and heat treatment temperature of the dielectric film is limited, the dielectric film itself cannot be processed. Permittivity There is a drawback that it is difficult to increase.
本発明の目的はシリコン電極からのシリコンの導電層と
誘電体膜の界面への拡散を防止した薄膜キャパシタを提
供することにある。It is an object of the present invention to provide a thin film capacitor which prevents diffusion of silicon from a silicon electrode to the interface between a conductive layer and a dielectric film.
前記目的を達成するため、本発明に係る薄膜キャパシタ
においては、導電層と、誘電体と、上部電極とを有する
薄膜キャパシタであって、 導電層と上部電極とは、誘電体を間に介装して積層形成
されたものであり、 導電層は、シリコン電極上に形成された第１層と、該第
１層上に形成された第２層とから構成されたものであ
り、 第１層は、Ｂ，Ｐ，As，Ｎ，Arの少なくとも１種の元素
をイオン注入したTa,Tiの少なくとも１種の材料からな
るものであり、 第２層は、Pt,Pdの少なくとも１種の材料からなるもの
である。To achieve the above object, a thin film capacitor according to the present invention is a thin film capacitor having a conductive layer, a dielectric, and an upper electrode, wherein the conductive layer and the upper electrode have a dielectric interposed therebetween. The conductive layer is composed of a first layer formed on the silicon electrode and a second layer formed on the first layer. Is made of at least one material of Ta and Ti in which at least one element of B, P, As, N and Ar is ion-implanted, and the second layer is made of at least one material of Pt and Pd. It consists of
シリコン電極上に形成される第１の導電層がＢ，Ｐ，A
s，Ｎ，Arの少なくとも１種の元素をイオン注入したTa,
Tiなどの少なくとも１種類の高融点金属からなり、第１
の導電層上に形成される第２の導電層がPt,Pdの少なく
とも１種類の材料からなり、この第１及び第２の導電層
の組からなる導電層上に誘電体膜、上部電極が順に積層
形成されている。したがって、シリコン電極からのシリ
コンが第２の導電層に拡散されることが制限され、シリ
サイドの形成が防止されることとなる。The first conductive layer formed on the silicon electrode is B, P, A
Ta ion-implanted with at least one element of s, N and Ar,
It consists of at least one refractory metal such as Ti.
The second conductive layer formed on the conductive layer of at least one of Pt and Pd, and the dielectric film and the upper electrode on the conductive layer formed of the set of the first and second conductive layers. The layers are formed in order. Therefore, the diffusion of silicon from the silicon electrode into the second conductive layer is restricted, and the formation of silicide is prevented.
〔実施例〕 次に、本発明について図面を参照して説明する。EXAMPLES Next, the present invention will be described with reference to the drawings.
（実施例１） 第１図は、本発明の実施例１を示す縦断面図であって、
誘電体としてSrTiO3を使用した薄膜キャパシタを示すも
のである。(Embodiment 1) FIG. 1 is a vertical sectional view showing Embodiment 1 of the present invention.
It shows a thin film capacitor using SrTiO 3 as a dielectric.
図において、１はＰ型シリコン基板、２はＮ型拡散層、
３はＰをイオン注入したTi層、４はPt層、５はSrTiO
3層、６はAl電極である。作製プロセスは公知の半導体
集積回路作製プロセスを使用した。Ｐ型シリコン基板１
上に薄膜キャパシタの下部電極となるＮ型拡散層２を作
製し、Ｎ型拡散層２上にTi層３をスパッタ法により10〜
100nm堆積し、Ti層３に、Ｐをエネルギー40〜100keV、
ドーズ量1011〜1016cm-2でイオン注入する。その後、ス
パッタ法によりTi層３上にPt層４を10〜100nm堆積し、
さらにPt層４上にSrTiO3層５を基板温度400℃で100〜30
0nm堆積し、その後酸素中で450℃、２時間の熱処理を行
い、光リソグラフィー及びプラズマエッチング技術によ
りSrTiO3層５・Pt層４・Ti層３を第１図の形状に加工す
る。最後に、上部電極としてAl電極６を1.0μｍ堆積
し、光リソグラフィー及びプラズマエッチングによりAl
電極６を加工して第１図に示す構造の薄膜キャパシタを
作製した。In the figure, 1 is a P-type silicon substrate, 2 is an N-type diffusion layer,
3 is a Ti layer in which P is ion-implanted, 4 is a Pt layer, 5 is SrTiO
3 layers and 6 are Al electrodes. As the manufacturing process, a known semiconductor integrated circuit manufacturing process was used. P-type silicon substrate 1
An N-type diffusion layer 2 which will be the lower electrode of the thin film capacitor is formed on the top, and a Ti layer 3 is formed on the N-type diffusion layer 2 by a sputtering method.
100 nm of P is deposited on the Ti layer 3 with energy of 40 to 100 keV,
Ion implantation is performed at a dose of 10 11 to 10 16 cm -2 . After that, a Pt layer 4 is deposited on the Ti layer 3 by a sputtering method to a thickness of 10 to 100 nm,
Furthermore, an SrTiO 3 layer 5 is formed on the Pt layer 4 at a substrate temperature of 400 ° C. for 100 to 30
After 0 nm deposition, heat treatment is performed in oxygen at 450 ° C. for 2 hours, and the SrTiO 3 layer 5, Pt layer 4 and Ti layer 3 are processed into the shape shown in FIG. 1 by photolithography and plasma etching technology. Finally, an Al electrode 6 was deposited to a thickness of 1.0 μm as an upper electrode, and Al was formed by photolithography and plasma etching.
The electrode 6 was processed to produce a thin film capacitor having the structure shown in FIG.
本発明の薄膜キャパシタでは、Ti層３にイオン注入して
いないものに比べて耐熱性が50℃以上改善され、より高
温の熱処理にも耐えることができるため、誘電体の誘電
率を大きくすることができる。また、実施例では、Ｐを
イオン注入しているが、注入エネルギーを選ぶことによ
り、Ｂ，As，Ｎ，Arイオンを注入しても同様の効果があ
る。In the thin film capacitor of the present invention, the heat resistance is improved by 50 ° C. or more as compared with the one in which the Ti layer 3 is not ion-implanted, and it is possible to withstand the heat treatment at a higher temperature. Therefore, the dielectric constant of the dielectric should be increased. You can Although P is ion-implanted in the embodiment, the same effect can be obtained by implanting B, As, N, Ar ions by selecting the implantation energy.
（実施例２） 第２図は本発明の実施例２を示す縦断面図である。(Embodiment 2) FIG. 2 is a vertical sectional view showing Embodiment 2 of the present invention.
図において、11はＰ型シリコン基板、12はＮ型拡散層、
13はＰ型拡散層、14及び15はＢをイオン注入したTa及び
Ti層、16はPt層、17は誘電体となるSrTiO3層、18は上部
電極となるAl電極である。In the figure, 11 is a P-type silicon substrate, 12 is an N-type diffusion layer,
13 is a P-type diffusion layer, and 14 and 15 are Ta and B in which B is ion-implanted.
A Ti layer, 16 is a Pt layer, 17 is a SrTiO 3 layer serving as a dielectric, and 18 is an Al electrode serving as an upper electrode.
作製プロセスは実施例１と同様であるが、イオン注入は
Ta層14及びTi層15を堆積した後、Ｂをエネルギー20〜40
keV、ドーズ量1011〜1016cm-2でイオン注入した。ま
た、Ta層14の厚さは10〜100nm、Ti層15の厚さは10〜100
nm、SrTiO3層17の厚さは100〜300nm、Al電極18は1.0μｍ
である。The fabrication process is the same as in Example 1, but the ion implantation is
After depositing the Ta layer 14 and the Ti layer 15, the B energy is 20 to 40
Ion implantation was performed with keV and a dose amount of 10 11 to 10 16 cm -2 . The Ta layer 14 has a thickness of 10 to 100 nm, and the Ti layer 15 has a thickness of 10 to 100 nm.
nm, the thickness of the SrTiO 3 layer 17 is 100 to 300 nm, and the Al electrode 18 is 1.0 μm
Is.
以上説明したように本発明は、シリコン電極上に形成さ
れる導電層が第１層と第１層上に形成される第２層とか
ら構成され、第１層がＢ，Ｐ，As，Ｎ，Arの少なくとも
１種の元素をイオン注入されたTa,Tiの少なくとも１種
の材料からなり、第２層がPt,Pdの少なくとも１種の材
料からなる構造であるため、シリコン電極からのシリコ
ンの第２層の拡散を制限し、第２層の材料とシリサイド
を形成することを防ぐことにより、導電層の第１層の膜
厚をあまり厚くすることなく、耐熱性の改善をすること
ができ、誘電体の誘電率を大きくすることができる効果
がある。As described above, in the present invention, the conductive layer formed on the silicon electrode is composed of the first layer and the second layer formed on the first layer, and the first layer is B, P, As, N. , Ar from which at least one element of Ar is ion-implanted, and the second layer is composed of at least one material of Pt and Pd. By restricting the diffusion of the second layer and preventing the formation of silicide with the material of the second layer, the heat resistance can be improved without making the thickness of the first layer of the conductive layer too large. Therefore, there is an effect that the dielectric constant of the dielectric can be increased.
第１図は、本発明の実施例１を示す縦断面図、第２図は
本発明の実施例２を示す縦断面図である。 1,11…Ｐ型シリコン基板、2,12…Ｎ型拡散層 ３…Ti層（Ｐイオン注入済み）、4,16…Pt層 5,17…SrTiO3層、6,18…Al電極 13…Ｐ型拡散層、14…Ta層（Ｂイオン注入済み） 15…Ti層（Ｂイオン注入済み）FIG. 1 is a vertical sectional view showing a first embodiment of the present invention, and FIG. 2 is a vertical sectional view showing a second embodiment of the present invention. 1,11 ... P type silicon substrate, 2,12 ... N type diffusion layer 3 ... Ti layer (P ion implantation completed), 4,16 ... Pt layer 5,17 ... SrTiO 3 layer, 6,18 ... Al electrode 13 ... P-type diffusion layer, 14 ... Ta layer (B ion implanted) 15 ... Ti layer (B ion implanted)
Claims (1)
薄膜キャパシタであって、 導電層と上部電極とは、誘電体を間に介装して積層形成
されたものであり、 導電層は、シリコン電極上に形成された第１層と、該第
１層上に形成された第２層とから構成されたものであ
り、 第１層は、Ｂ，Ｐ，As，Ｎ，Arの少なくとも１種の元素
をイオン注入したTa,Tiの少なくとも１種の材料からな
るものであり、 第２層は、Pt,Pdの少なくとも１種の材料からなるもの
であることを特徴とする薄膜キャパシタ。1. A thin film capacitor having a conductive layer, a dielectric, and an upper electrode, wherein the conductive layer and the upper electrode are laminated and formed with a dielectric interposed therebetween. The layer is composed of a first layer formed on a silicon electrode and a second layer formed on the first layer, and the first layer is B, P, As, N, Ar. Is made of at least one material of Ta and Ti, which is ion-implanted with at least one of these elements, and the second layer is made of at least one material of Pt and Pd. Capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24687890A JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24687890A JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04125958A JPH04125958A (en) | 1992-04-27 |
| JPH0652774B2 true JPH0652774B2 (en) | 1994-07-06 |
Family
ID=17155085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24687890A Expired - Lifetime JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0652774B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693595A (en) * | 1995-06-06 | 1997-12-02 | Northrop Grumman Corporation | Integrated thin-film terminations for high temperature superconducting microwave components |
| KR100393197B1 (en) * | 1996-10-31 | 2003-11-01 | 삼성전자주식회사 | Ferroelectric capacitor and manufacturing method thereof |
| CN105070786B (en) * | 2015-07-28 | 2017-03-08 | 昆明物理研究所 | A kind of reading circuit extraction electrode of resistance to high temperature oxidation and preparation method thereof |
-
1990
- 1990-09-17 JP JP24687890A patent/JPH0652774B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04125958A (en) | 1992-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2573384B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| JP3717039B2 (en) | Ferroelectric memory transistor and manufacturing method thereof | |
| US4959745A (en) | Capacitor and method for producing the same | |
| JPH0465548B2 (en) | ||
| JPS61226959A (en) | Semiconductor device and manufacture thereof | |
| JP2788835B2 (en) | Thin film capacitor and method of manufacturing the same | |
| JPH0574940B2 (en) | ||
| US6403441B1 (en) | Method for fabricating storage capacitor using high dielectric constant material | |
| JPH04119666A (en) | Manufacture of integrated circuit | |
| US6333534B1 (en) | Semiconductor device and method of fabricating | |
| JPH0652774B2 (en) | Thin film capacitor | |
| DE19824774A1 (en) | Capacitor production in a transistor-containing semiconductor component especially a DRAM | |
| JPH0982915A (en) | Manufacture of semiconductor device | |
| JPH06125057A (en) | Semiconductor memory containing ferroelectric film | |
| JPH07263674A (en) | Field effect semiconductor device and its manufacture | |
| JPS60193333A (en) | Manufacture of semiconductor device | |
| JPS6262472B2 (en) | ||
| JPH0367346B2 (en) | ||
| JPS6044823B2 (en) | Manufacturing method of semiconductor device | |
| JPS62142363A (en) | Semiconductor memory device and manufacture thereof | |
| KR920010201B1 (en) | Semidonductor device and method for manufacturing of the same | |
| JPH01220856A (en) | Semiconductor device | |
| JP2721167B2 (en) | Semiconductor storage device | |
| JPS62293772A (en) | Semiconductor device | |
| JPH03148860A (en) | Semiconductor memory and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 13 Free format text: PAYMENT UNTIL: 20070706 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 14 Free format text: PAYMENT UNTIL: 20080706 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 15 Free format text: PAYMENT UNTIL: 20090706 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 16 Free format text: PAYMENT UNTIL: 20100706 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110706 Year of fee payment: 17 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 17 Free format text: PAYMENT UNTIL: 20110706 |