JPS58134464A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58134464A
JPS58134464A JP57016902A JP1690282A JPS58134464A JP S58134464 A JPS58134464 A JP S58134464A JP 57016902 A JP57016902 A JP 57016902A JP 1690282 A JP1690282 A JP 1690282A JP S58134464 A JPS58134464 A JP S58134464A
Authority
JP
Japan
Prior art keywords
film
ta2o5
capacitor
oxidized
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57016902A
Other languages
Japanese (ja)
Inventor
Hitoshi Hasegawa
長谷川 斉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57016902A priority Critical patent/JPS58134464A/en
Publication of JPS58134464A publication Critical patent/JPS58134464A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a capacitor having large capacity density and small leakage current by superposing Ta2O5, Ta on an Si and oxidizing it to form a Ta2O5 film. CONSTITUTION:An N type polysilicon film 8 to becomes the electrode of the capacity of a memory cell by connecting to the N<+> type drain 6 of an FET is formed, a Ta2O5 9 is sputtered in approx. 10nm, and Ta film 10 is then sputtered in more than 50nm. It is then treated at approx. 800 deg.C in vacuum to improve the crystallinity of the film 10, oxidized to form a Ta2O5 film 11 together with the film 9, a polysilicon electrode 12 is attached, memory cells are individually isolated, and a capacitor is formed. The film 10 is oxidized in dry O2, but the Ta is not silicided to the polysilicon 8 due to the intermediary of the film 9, and the temperature and the time can be widely selected. When N2 is flowed to the trichloroethylene surface at 0 deg.C, introduced together with the O2 to a treating chamber and oxidized in an atmosphere including Cl2, it is effective to reduce the leakage current of the Ta2O5 formed of the Ta.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置、4!KMOSグイナオックランダ
ムアクセスメモリ等のコンデンサの誘電体とする酸化タ
ンタル膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to semiconductor devices, 4! The present invention relates to a method for manufacturing a tantalum oxide film used as a dielectric of a capacitor such as a KMOS Guinaoch random access memory.

(bl  技術の背景 半導体集積回路にコンデンサ素子を設ける代表的な例と
してMO8ダイナZツクツンダムアクセスメモリ(以下
M08 RAMという)がある。
Background of the Technology A typical example of providing a capacitor element in a semiconductor integrated circuit is the MO8 Dyna Z Tsukundam Access Memory (hereinafter referred to as M08 RAM).

MO8RAMの読出し信号を少しでも大きくし、また雑
音電圧による誤動作を防止する九めにも、MOS RA
Mの該コンデンサにはできる限シ大きい静電容量を4た
せることか必要である。
MOS RA
It is necessary that the capacitor M has as large a capacitance as possible.

仁のコンデンサの容量を大きくするために1MO8RA
Mの平面配置に工夫を加え、更には多層化によりてコン
デンサ面積を最大とする方法が提案され、また他の方法
としては、従来OMO8構造のコンデンサの誘電体を構
成している二酸化シリコン(810,)の比誘電率が3
.8程度と小さいのに対して、これよりも比誘電率の大
きい窒化シリコン(8ゑ−N−)(as冨5〜7)、更
に酸化タンクk (Tm、0. ) (を魯=20〜2
B )等を誘電体とすることによって、容量密度を増加
させることが提案されている・ (C)  従来技術と問題点 シリコン基板もしくは基板上に設けられた多結晶シリコ
ン層等のシリコン(St)層上に、タンク# (TI)
 @をスパッタリング法、電子ビーム法等によって形成
する場合において、通常のTaのシリサイド化反応温度
よシ遥に低温で69で、50℃極度もしくは高くとも1
00℃を起えないにもかかわらず、Taと81との関に
化学反応が生ずる。
1MO8RA to increase the capacitance of the capacitor
A method has been proposed to maximize the capacitor area by modifying the planar arrangement of M and further by adding multiple layers.Another method is to use silicon dioxide (810 , ) has a relative dielectric constant of 3
.. Although it is small at about 8, silicon nitride (8ゑ-N-) (as density 5~7), which has a larger dielectric constant than this, and an oxidation tank k (Tm, 0.) (L=20~ 2
It has been proposed to increase the capacitance density by using B) etc. as a dielectric. (C) Conventional technology and problems Silicon (St) such as a silicon substrate or a polycrystalline silicon layer provided on a substrate On the layer, tank # (TI)
When forming @ by sputtering method, electron beam method, etc., the temperature is much lower than the normal Ta silicidation reaction temperature, 50°C extreme or at most 1
Although the temperature does not rise to 00°C, a chemical reaction occurs between Ta and 81.

又、S1層上に形成されたTdll熱処理もしくは熱酸
化のためKTi膜形成温度以上に加熱する場合において
も、Tiのシリサイド化反応が進行する。
Furthermore, even when the Tdll formed on the S1 layer is heated to a temperature higher than the KTi film formation temperature for heat treatment or thermal oxidation, the silicidation reaction of Ti proceeds.

この様に8i f含むTa膜を熱酸化法もしくは陽極酸
化法等によりて酸化してTa10g膜とし、これを誘電
体とすゐコンデンサを形成した場合には、タンタル単体
面上yc Tm、 O,膜を形成した場合に比較して漏
れ電流が大でありて、MOS RAM等の電荷の蓄積を
目的とする用途においては特に大きい問題となる。
In this way, when a Ta film containing 8if is oxidized to a 10g Ta film by thermal oxidation or anodic oxidation, and this is used as a dielectric to form a capacitor, yc Tm, O, The leakage current is large compared to the case where a film is formed, and this becomes a particularly serious problem in applications where the purpose is to accumulate charge, such as in MOS RAM.

またS&層上KTag O@膜を直接にスパッタリング
法等によシ形成する方法もあるが、この方法によって形
成されるTa10B膜は組織に欠陥を生じ易くコンデン
サの誘電体とするに難点がある。
There is also a method of directly forming a KTag O@ film on the S& layer by sputtering or the like, but the Ta10B film formed by this method tends to have defects in its structure and is difficult to use as a dielectric for a capacitor.

(dl  発明の目的 本発明は、シリコン基板もしくは基板上に設けられた多
結晶シリコン層勢のシリコン層上に、コンデンサの誘電
体として漏れ電流が少く、半導体装置の工業的生産にな
じむ酸化タンタル績を形成する製造方法を提供すること
を目的とする。
(dl Purpose of the Invention The present invention provides a tantalum oxide material, which has low leakage current and is suitable for industrial production of semiconductor devices, as a dielectric material of a capacitor, on a silicon substrate or a silicon layer of a polycrystalline silicon layer provided on a substrate. The purpose is to provide a manufacturing method for forming.

(e)発明の構成 本発明の前記目的は、咳シリコン層上Ktず酸化タンタ
ル膜を設け、該酸化タンタル膜上にメンタル膜を設は九
後該タン〉ル膜を酸化せしめて駿費化させるに先立って
、前記タンタル膜に予め熱処理を施して、その組織内の
欠陥を除去してもよい0 (f)  発明の実施例 以下本発明を実施例によシ図面を参照して具体的に説明
する。
(e) Structure of the Invention The object of the present invention is to provide a tantalum oxide film on a silicon layer, to form a mental film on the tantalum oxide film, and then to oxidize the tantalum film. The tantalum film may be subjected to heat treatment in advance to remove defects in its structure (f) Embodiments of the Invention The present invention will be described below in detail with reference to the drawings. Explain.

第1図乃至第3図は、MOS RAMのメモリーセルの
コンデンサの誘電体の形成に就いての本発明の実施例を
示す断面図である。
1 to 3 are cross-sectional views illustrating an embodiment of the present invention for forming a dielectric of a capacitor of a memory cell of a MOS RAM.

・□、。・□,.

第1図は本発明奥−前の状態を示し、P型シリコン基板
1上に840.よりなるフィールド絶縁膜2、ゲート絶
縁膜3を設け、ゲート絶縁膜3を介して多結晶シリコン
よシなるゲート電[141形成する。ソース又はドレイ
ンとなるn++域5及び6を形成後、該基体面上に8i
0.よりなる絶縁1[7t−設け、n+領領域面面上骸
絶縁膜7を選択的に除去して、多結晶シリコン膜8を形
成している。
FIG. 1 shows the back and front states of the present invention, in which 840. A field insulating film 2 and a gate insulating film 3 are provided, and a gate electrode 141 made of polycrystalline silicon is formed through the gate insulating film 3. After forming n++ regions 5 and 6 that will become sources or drains, 8i
0. A polycrystalline silicon film 8 is formed by selectively removing the insulation film 7 on the n+ region surface.

この多結晶シリコン膜8は目的どするメモリーセルのコ
ンデンサの一方の電極となるものであり、ソース及びド
レインと同じ(njJKドープされる。
This polycrystalline silicon film 8 becomes one electrode of the capacitor of the intended memory cell, and is doped with the same (njJK) doping as the source and drain.

第2図は本発萌の方法によりT町01膜9及びT1膜1
0を形成し大状態を示す。すなわち、前記多結晶シリコ
ン膜8上KtずTa、 C%膜9を厚さ例えば10#1
程度に形成する。このTm、O,膜9の形成は電子ビー
ム法でも可能であるがスパッタリング法により更に良い
結果が得られる。続いてこのTag O6g 9上fc
Ta膜10を厚さ例えば5〇−程度に形成する。この厚
さは10−程度以上の値を任意に選択することができる
。とのT1膜10の形成も電子ビーム真空蒸着法でも可
能であるがスパッタリング法が好ましい。
Figure 2 shows T-town 01 membrane 9 and T1 membrane 1 obtained by the method of this invention.
0 is formed to indicate a large state. That is, the Kt, Ta, C% film 9 is formed on the polycrystalline silicon film 8 to a thickness of, for example, 10#1.
Form to a certain degree. The Tm, O, film 9 can be formed by an electron beam method, but even better results can be obtained by a sputtering method. Next, this Tag O6g 9 upper fc
A Ta film 10 is formed to a thickness of, for example, about 50 mm. This thickness can be arbitrarily selected to be about 10- or more. The T1 film 10 can also be formed by electron beam vacuum evaporation, but sputtering is preferred.

Ta1llO形成後真空中において温度800℃程度の
熱処理を施すならばTa膜10の結晶性の向上、或いは
結晶粒の増大により、よシ高品質な膜が得られる事が期
待出来、これより形成されるTa1O1膜の膜質に大き
く影醤する。
If heat treatment is performed at a temperature of about 800° C. in a vacuum after Ta1IO is formed, it is expected that a film of higher quality will be obtained due to improvement of the crystallinity of the Ta film 10 or increase in crystal grains. This greatly affects the quality of the Ta1O1 film.

T1膜10形成後、或いは前記熱処理後KTajl11
0を酸化して、Ta、 0−膜1とともK Tag 0
1膜lit形成する。第3図はこのTa、O,−膜11
上に電極とする多結晶シリコン膜12を設け、メモリー
セル毎に分割してコンダン+1形成し大状態を示す。
After forming the T1 film 10 or after the heat treatment, KTajl11
By oxidizing 0, Ta, 0-film 1 and K Tag 0
One film lit is formed. FIG. 3 shows this Ta,O,- film 11.
A polycrystalline silicon film 12 serving as an electrode is provided thereon and divided into memory cells to form a conductor +1 to show a large state.

Ta Jig 10の酸化は例えば乾燥酸素tS気中で
温度500”CIIItK加熱するととによりてなされ
るが、この酸化のための加熱或いは前記Ta1110C
)熱地3!に*−いて−前記従来技術の場合とは異なり
てTal0@膜9が多結晶シリコン膜8との間に介在す
るために%T麿のシリサイド化を生ぜず、温度及び時間
を幅広く選択することができゐ。
Oxidation of Ta Jig 10 is carried out, for example, by heating at a temperature of 500"CIIItK in a dry oxygen tS atmosphere.
) Atsushi 3! Unlike the case of the prior art described above, since the Tal0@ film 9 is interposed between the polycrystalline silicon film 8, silicidation of %T does not occur, and the temperature and time can be selected over a wide range. I can do it.

−★たTm膜10より形成され九Tl*0*mlの漏れ
電流を減少せしめる酸化法として、本発明者が別途提案
する塩素を含んだ雰囲気中における酸化法があゐ。との
酸化法は、例えば、0℃のFリタロ見 1 図 晃 2 図 !3Il!l
As an oxidation method for reducing the leakage current of 9 Tl*0*ml formed from the -★ Tm film 10, there is an oxidation method in an atmosphere containing chlorine, which is proposed separately by the present inventor. For example, the oxidation method at 0°C is shown in Figure 1. 3Il! l

Claims (1)

【特許請求の範囲】[Claims] シリコン層上に酸化タンタル膜を設け、該酸化タンタル
膜上にタンタル膜を設は喪後、骸タンタル膜を酸化せし
めて酸化タンタル膜を形成する工程を含むことtq#黴
とする半導体装置の製造方法。
Manufacture of a semiconductor device comprising a step of providing a tantalum oxide film on a silicon layer, and after forming a tantalum film on the tantalum oxide film, oxidizing the skeleton tantalum film to form a tantalum oxide film. Method.
JP57016902A 1982-02-04 1982-02-04 Manufacture of semiconductor device Pending JPS58134464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57016902A JPS58134464A (en) 1982-02-04 1982-02-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57016902A JPS58134464A (en) 1982-02-04 1982-02-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58134464A true JPS58134464A (en) 1983-08-10

Family

ID=11929069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57016902A Pending JPS58134464A (en) 1982-02-04 1982-02-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58134464A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108941A (en) * 1986-12-05 1992-04-28 Texas Instrument Incorporated Method of making metal-to-polysilicon capacitor
US5202280A (en) * 1991-06-06 1993-04-13 Nec Corporation Method for fabricating a semiconductor device
US6187693B1 (en) 1998-11-13 2001-02-13 Nec Corporation Heat treatment of a tantalum oxide film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108941A (en) * 1986-12-05 1992-04-28 Texas Instrument Incorporated Method of making metal-to-polysilicon capacitor
US5202280A (en) * 1991-06-06 1993-04-13 Nec Corporation Method for fabricating a semiconductor device
US6187693B1 (en) 1998-11-13 2001-02-13 Nec Corporation Heat treatment of a tantalum oxide film

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