JPH0145746B2 - - Google Patents

Info

Publication number
JPH0145746B2
JPH0145746B2 JP56108403A JP10840381A JPH0145746B2 JP H0145746 B2 JPH0145746 B2 JP H0145746B2 JP 56108403 A JP56108403 A JP 56108403A JP 10840381 A JP10840381 A JP 10840381A JP H0145746 B2 JPH0145746 B2 JP H0145746B2
Authority
JP
Japan
Prior art keywords
layer
capacitor
tantalum
present
tasi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56108403A
Other languages
Japanese (ja)
Other versions
JPS5810852A (en
Inventor
Kanetake Takasaki
Yoshimi Shiotani
Kenji Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56108403A priority Critical patent/JPS5810852A/en
Publication of JPS5810852A publication Critical patent/JPS5810852A/en
Publication of JPH0145746B2 publication Critical patent/JPH0145746B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に半導体装置を
構成するキヤパシタの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a capacitor that constitutes a semiconductor device.

ダイナミツクRAM(Random Access
Memory)等構成要素としてキヤパシタを有する
半導体装置においては、チツプ中に占めるキヤパ
シタの面積が大きく、このことが上記半導体装置
の微細化、高密度化を阻害する。
Dynamic RAM (Random Access
In a semiconductor device having a capacitor as a component such as a memory, the capacitor occupies a large area in a chip, which hinders miniaturization and high density of the semiconductor device.

そこで上記キヤパシタを小形化するため、誘電
体材料として誘電率のきわめて大きいタンタル
(Ta)の酸化物を用いた構造が試みられている。
即ち第1図a,bはその例を示す要部断面図で、
同図aは単結晶シリコン(Si)または多結晶シリ
コン(Si)層1上にTa2O5のようなタンタル
(Ta)の酸化物層2を介して多結晶シリコン層3
を形成した構造、同図bは単結晶シリコンまたは
多結晶シリコン層1上にタンタル(Ta)層4、
Ta2O5層2、多結晶シリコン層3を積層したキヤ
パシタである。
Therefore, in order to downsize the capacitor, attempts have been made to create a structure using tantalum (Ta) oxide, which has an extremely high dielectric constant, as the dielectric material.
That is, FIGS. 1a and 1b are sectional views of essential parts showing an example of this,
In the figure a, a polycrystalline silicon layer 3 is formed on a single crystal silicon (Si) or polycrystalline silicon (Si) layer 1 through a tantalum (Ta) oxide layer 2 such as Ta 2 O 5 .
Figure b shows a structure in which a tantalum (Ta) layer 4 is formed on a monocrystalline silicon or polycrystalline silicon layer 1,
This is a capacitor in which a Ta 2 O 5 layer 2 and a polycrystalline silicon layer 3 are laminated.

上記2つの例に用いたTa2O5は従来のキヤパシ
タの誘電体材料としてて用いられている二酸化シ
リコン(SiO2)に較べて誘電率が約7倍である
ので、上記構造によれば同一容量のキヤパシタを
著しく小形化し得る。しかし上記構造では引き続
く高温処理工程において、Ta2O5層とシリコン層
との間及びTa層とシリコン層との間で相互拡散
が生じてTa2O5層の絶縁性が損なわれ、洩れ電流
が流れる。そのため誘電体材料としてタンタルの
酸化物を用いたキヤパシタは素子を微細化する目
的から有望視されながら実用にならなかつた。
Ta 2 O 5 used in the above two examples has a dielectric constant about 7 times that of silicon dioxide (SiO 2 ) used as a dielectric material for conventional capacitors, so according to the above structure, they are the same. The capacitor can be significantly downsized. However, in the above structure, during the subsequent high-temperature treatment process, interdiffusion occurs between the Ta 2 O 5 layer and the silicon layer, and between the Ta layer and the silicon layer, impairing the insulation properties of the Ta 2 O 5 layer, resulting in leakage current. flows. Therefore, although capacitors using tantalum oxide as a dielectric material were seen as promising for the purpose of miniaturizing devices, they were not put into practical use.

本発明は上記難点を解消するためになされたも
ので、誘電体材料としてタンタルの酸化物を用い
たキヤパシタの洩れ電流を生じることのない改良
された構造を提供することを目的とし、この目的
は本発明において、2層のタンタル硅化物層の間
にタンタル酸化物層がはさまれた構造により達成
される。
The present invention has been made to solve the above-mentioned problems, and its purpose is to provide an improved structure of a capacitor that uses tantalum oxide as a dielectric material and does not cause leakage current. In the present invention, this is achieved by a structure in which a tantalum oxide layer is sandwiched between two tantalum silicide layers.

第2図は、本発明の第1の実施例の構造を示す
要部断面図で、シリコン基板1上に第1のTaSi2
層5、Ta2O5層2、第2のTaSi2層6を積層して
キヤパシタを形成した。このようにシリコン層と
Ta2O5層との間にタンタル(Ta)の硅化のTaSi2
層を介在せしめた構造としたことにより、高温処
理による相互拡散が抑制され、1200[℃]まで加
熱しても洩れ電流の発生は認められなかつた。
FIG. 2 is a sectional view of a main part showing the structure of the first embodiment of the present invention, in which a first TaSi 2 film is deposited on a silicon substrate 1.
Layer 5, Ta 2 O 5 layer 2, and second TaSi 2 layer 6 were laminated to form a capacitor. In this way, the silicon layer
TaSi 2 of tantalum (Ta) silicide between 5 layers of Ta 2 O
By adopting a structure with intervening layers, mutual diffusion caused by high-temperature treatment was suppressed, and no leakage current was observed even when heated to 1200 [°C].

第3図は本発明の第2の実施例を示す要部断面
図で、本発明に係るキヤパシタを用いて作成した
ダイナミツクRAMのメモリセルを示す。同図に
おいて、8は素子領域を画定するフイールド酸化
膜、9はゲート酸化膜、10はゲート電極、11
はドレイン領域、12はソース領域である。なお
前記第1図ないし第3図と同一部分は同一符号で
示してある。
FIG. 3 is a cross-sectional view of a main part of a second embodiment of the present invention, showing a memory cell of a dynamic RAM fabricated using a capacitor according to the present invention. In the figure, 8 is a field oxide film that defines the device region, 9 is a gate oxide film, 10 is a gate electrode, and 11 is a gate oxide film.
is a drain region, and 12 is a source region. Note that the same parts as in FIGS. 1 to 3 are designated by the same reference numerals.

同図に見られるごとくこのメモリセルは、ドレ
イン領域11表面からフイールド酸化膜8上に延
長して形成された第1のTaSi2層5、Ta2O5
2、第2のTaSi2層6でキヤパシタを構成し、し
かも上記第1のTaSi2層5にドレイン領域11の
引き出し電極を兼ねさせた例である。
As seen in the figure, this memory cell consists of a first TaSi 2 layer 5, a Ta 2 O 5 layer 2, and a second TaSi 2 layer 6, which are formed extending from the surface of the drain region 11 onto the field oxide film 8. This is an example in which a capacitor is constructed, and the first TaSi 2 layer 5 also serves as an extraction electrode for the drain region 11.

上記キヤパシタを形成するには、例えば上記3
層をCVD(化学気相成長)法、プラズマCVD法、
スパツタ法、或いはイオンビームデポジシヨン法
等で被着せしめたのち、CF4のようなフロロカー
ボン系ガスを反応ガスとするプラズマエツチング
法等によりパターニングすればよい。なお、
Ta2O5層はTaSi2層を陽極酸化して形成すること
もできる。
In order to form the above capacitor, for example, the above 3
layer by CVD (chemical vapor deposition) method, plasma CVD method,
After deposition by a sputtering method or an ion beam deposition method, patterning may be performed by a plasma etching method using a fluorocarbon gas such as CF 4 as a reaction gas. In addition,
The Ta 2 O 5 layer can also be formed by anodizing a TaSi 2 layer.

このように形成した本実施例のダイナミツク
RAMは、Ta2O5の誘電率が非常に大きいため、
通常の如くSiO2層を誘電体層に用いた場合に較
べキヤパシタをきわめて小さくすることができ、
従つて素子を微細化、高密度化することができ
る。
The dynamics of this example formed in this way
RAM is made of Ta2O5 because its dielectric constant is very large.
Compared to the usual case where two SiO layers are used as the dielectric layer, the capacitor can be made extremely small.
Therefore, it is possible to miniaturize the device and increase its density.

第4図は第3図のメモリセルを用いて構成した
ダイナミツクRAMのメモリセル領域の一部を示
す回路構成図で、13はMOSFET、14はキヤ
パシタ、WLはワードライン、BLはビツトライ
ンを示す。
FIG. 4 is a circuit configuration diagram showing a part of the memory cell area of a dynamic RAM constructed using the memory cells of FIG. 3, in which 13 is a MOSFET, 14 is a capacitor, WL is a word line, and BL is a bit line.

なお本発明を実施するに当り誘電体層としては
前述のTa2O5に代えて他のタンタル(Ta)の酸
化TaXSiYOZを用いてもよい。
In carrying out the present invention, other tantalum (Ta) oxide Ta X Si Y O Z may be used as the dielectric layer in place of the aforementioned Ta 2 O 5 .

以上説明した如く本発明によれば、誘電体にタ
ンタル(Ta)の酸化物を用いたキヤパシタが実
用化され、その結果キヤパシタを構成要素として
具備する半導体装置を微細化、高密度化すること
ができる。
As explained above, according to the present invention, a capacitor using tantalum (Ta) oxide as a dielectric material is put into practical use, and as a result, it is possible to miniaturize and increase the density of a semiconductor device that includes a capacitor as a component. can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは従来のキヤパシタを示す要部断
面図、第2図は本発明の第1の実施例を示す要部
断面図で本発明の要部であるキヤパシタの基本構
造を示し、第3図は本発明の第2の実施例を示す
要部断面図で、本発明を用いて構成したダイナミ
ツクRAMを示し、第4図は上記ダイナミツク
RAMのメモリセル領域の一部を示す回路構成図
である。 図において、1は半導体基板または層、2はタ
ンタルの酸化物層、5及び6はタンタルの硅化物
層を示す。
Figures 1a and b are sectional views of the main parts of a conventional capacitor, and Figure 2 is a sectional view of the main parts of a first embodiment of the present invention, showing the basic structure of the capacitor, which is the main part of the present invention. FIG. 3 is a sectional view of a main part of a second embodiment of the present invention, showing a dynamic RAM constructed using the present invention, and FIG.
FIG. 2 is a circuit configuration diagram showing a part of a memory cell area of a RAM. In the figure, 1 is a semiconductor substrate or layer, 2 is a tantalum oxide layer, and 5 and 6 are tantalum silicide layers.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板表面にキヤパシタが形成されてな
る半導体装置において、前記キヤパシタは2層の
タンタル硅化物層の間にタンタル酸化物層がはさ
まれてなることを特徴とする半導体装置。
1. A semiconductor device in which a capacitor is formed on the surface of a semiconductor substrate, wherein the capacitor is formed by sandwiching a tantalum oxide layer between two tantalum silicate layers.
JP56108403A 1981-07-10 1981-07-10 Semiconductor device Granted JPS5810852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56108403A JPS5810852A (en) 1981-07-10 1981-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56108403A JPS5810852A (en) 1981-07-10 1981-07-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5810852A JPS5810852A (en) 1983-01-21
JPH0145746B2 true JPH0145746B2 (en) 1989-10-04

Family

ID=14483864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56108403A Granted JPS5810852A (en) 1981-07-10 1981-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5810852A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072261A (en) * 1983-09-28 1985-04-24 Fujitsu Ltd Semiconductor memory
JPS60111451A (en) * 1983-11-21 1985-06-17 Toshiba Corp Semiconductor device and manufacture thereof
JPS61150368A (en) * 1984-12-25 1986-07-09 Nec Corp Semiconductor device
JPS61196566A (en) * 1985-02-26 1986-08-30 Mitsubishi Electric Corp Semiconductor device
JPH04242970A (en) * 1991-01-01 1992-08-31 Tadahiro Omi Dynamic semiconductor memory
DE19937503C1 (en) * 1999-08-09 2001-01-04 Siemens Ag Etching oxide films of a ferroelectric bismuth-containing mixed oxide comprises applying an oxide film to a substrate, contacting with an etching solution, and removing the etching solution

Also Published As

Publication number Publication date
JPS5810852A (en) 1983-01-21

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