JPH0145746B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a capacitor that constitutes a semiconductor device.

Dynamic RAM (Random Access
In a semiconductor device having a capacitor as a component such as a memory, the capacitor occupies a large area in a chip, which hinders miniaturization and high density of the semiconductor device.

Therefore, in order to downsize the capacitor, attempts have been made to create a structure using tantalum (Ta) oxide, which has an extremely high dielectric constant, as the dielectric material.
That is, FIGS. 1a and 1b are sectional views of essential parts showing an example of this,
In the figure a, a polycrystalline silicon layer 3 is formed on a single crystal silicon (Si) or polycrystalline silicon (Si) layer 1 through a tantalum (Ta) oxide layer 2 such as Ta ₂ O ₅ .
Figure b shows a structure in which a tantalum (Ta) layer 4 is formed on a monocrystalline silicon or polycrystalline silicon layer 1,
This is a capacitor in which a Ta ₂ O ₅ layer 2 and a polycrystalline silicon layer 3 are laminated.

Ta ₂ O ₅ used in the above two examples has a dielectric constant about 7 times that of silicon dioxide (SiO ₂ ) used as a dielectric material for conventional capacitors, so according to the above structure, they are the same. The capacitor can be significantly downsized. However, in the above structure, during the subsequent high-temperature treatment process, interdiffusion occurs between the Ta ₂ O ₅ layer and the silicon layer, and between the Ta layer and the silicon layer, impairing the insulation properties of the Ta ₂ O ₅ layer, resulting in leakage current. flows. Therefore, although capacitors using tantalum oxide as a dielectric material were seen as promising for the purpose of miniaturizing devices, they were not put into practical use.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide an improved structure of a capacitor that uses tantalum oxide as a dielectric material and does not cause leakage current. In the present invention, this is achieved by a structure in which a tantalum oxide layer is sandwiched between two tantalum silicide layers.

FIG. 2 is a sectional view of a main part showing the structure of the first embodiment of the present invention, in which a first TaSi ₂ film is deposited on a silicon substrate 1.
Layer 5, Ta ₂ O ₅ layer 2, and second TaSi ₂ layer 6 were laminated to form a capacitor. In this way, the silicon layer
TaSi ₂ of tantalum (Ta) silicide between ₅ layers of Ta ₂ O
By adopting a structure with intervening layers, mutual diffusion caused by high-temperature treatment was suppressed, and no leakage current was observed even when heated to 1200 [°C].

FIG. 3 is a cross-sectional view of a main part of a second embodiment of the present invention, showing a memory cell of a dynamic RAM fabricated using a capacitor according to the present invention. In the figure, 8 is a field oxide film that defines the device region, 9 is a gate oxide film, 10 is a gate electrode, and 11 is a gate oxide film.
is a drain region, and 12 is a source region. Note that the same parts as in FIGS. 1 to 3 are designated by the same reference numerals.

As seen in the figure, this memory cell consists of a first TaSi ₂ layer 5, a Ta ₂ O ₅ layer 2, and a second TaSi 2 layer 6, which are formed extending from the surface of the drain region 11 onto the field oxide _film 8. This is an example in which a capacitor is constructed, and the first TaSi ₂ layer 5 also serves as an extraction electrode for the drain region 11.

In order to form the above capacitor, for example, the above 3
layer by CVD (chemical vapor deposition) method, plasma CVD method,
After deposition by a sputtering method or an ion beam deposition method, patterning may be performed by a plasma etching method using a fluorocarbon gas such as CF ₄ as a reaction gas. In addition,
The Ta ₂ O ₅ layer can also be formed by anodizing a TaSi ₂ layer.

The dynamics of this example formed in this way
RAM is _made of _Ta2O5 because its dielectric constant is very large.
Compared to the usual case where _two SiO layers are used as the dielectric layer, the capacitor can be made extremely small.
Therefore, it is possible to miniaturize the device and increase its density.

FIG. 4 is a circuit configuration diagram showing a part of the memory cell area of a dynamic RAM constructed using the memory cells of FIG. 3, in which 13 is a MOSFET, 14 is a capacitor, WL is a word line, and BL is a bit line.

In carrying out the present invention, other tantalum (Ta) oxide Ta _X Si _Y O _Z may be used as the dielectric layer in place of the aforementioned Ta ₂ O ₅ .

As explained above, according to the present invention, a capacitor using tantalum (Ta) oxide as a dielectric material is put into practical use, and as a result, it is possible to miniaturize and increase the density of a semiconductor device that includes a capacitor as a component. can.

[Brief explanation of drawings]

Figures 1a and b are sectional views of the main parts of a conventional capacitor, and Figure 2 is a sectional view of the main parts of a first embodiment of the present invention, showing the basic structure of the capacitor, which is the main part of the present invention. FIG. 3 is a sectional view of a main part of a second embodiment of the present invention, showing a dynamic RAM constructed using the present invention, and FIG.
FIG. 2 is a circuit configuration diagram showing a part of a memory cell area of a RAM. In the figure, 1 is a semiconductor substrate or layer, 2 is a tantalum oxide layer, and 5 and 6 are tantalum silicide layers.

Claims (1)

[Claims] 1. A semiconductor device in which a capacitor is formed on the surface of a semiconductor substrate, wherein the capacitor is formed by sandwiching a tantalum oxide layer between two tantalum silicate layers.