JPS60111451A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60111451A JPS60111451A JP21905583A JP21905583A JPS60111451A JP S60111451 A JPS60111451 A JP S60111451A JP 21905583 A JP21905583 A JP 21905583A JP 21905583 A JP21905583 A JP 21905583A JP S60111451 A JPS60111451 A JP S60111451A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- metal silicide
- tasix
- ta2o5
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000203 mixture Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、キャノfシタ用誘電体を改良した半導体装置
及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device with an improved dielectric for a canopy and a method for manufacturing the same.
周知の如く、半導体装置例えばダイナミックRA M
(dRAM)の集積化は、現在256にビットを実現さ
れるまで進み、この高集積化によりキャパシタの面積は
必然的に縮小されている。As is well known, semiconductor devices such as dynamic RAM
The integration of dRAM (dRAM) has progressed to the point where 256 bits have now been realized, and this higher integration necessarily reduces the area of the capacitor.
ところで、キャパシタ容量C8は、下地層となる半導体
基板との容量を無視した場合、以下の式により決定され
る。Incidentally, the capacitor capacitance C8 is determined by the following formula, when the capacitance with the semiconductor substrate serving as the base layer is ignored.
なお、式(1)において、εは誘電率を、Sはキヤ・母
シタ面積を、dは誘電体膜厚を夫々示す。In Equation (1), ε represents a dielectric constant, S represents a capacitance/mother area, and d represents a dielectric film thickness.
同式において、キャパシタ容量を大きくするには、第1
の手段として誘電体膜厚dを薄くすることが考えられる
。これについては、膜形成の改良などによりかなりの薄
膜化が可能となっている。例えば、256 RAMにお
いて、S i O,でt = 200〜250Aの膜厚
となっている。しかしながら、5102の場合、誘電率
が3.9と低く、また膜厚的にも耐圧の観点からみると
、〜100Aが限界と考えられている。また第2の手段
として、Si3N4. Ta、O,等の高誘電率の誘電
体の使用が考えられる。しかしながら、これらの誘電体
は、プロセス的、信頼性的にも実用の域に達していない
。なお、最近、Taをスパッタ法により形成して’ra
2o、を誘電体と使用する報告が数件なされているが、
耐圧、リーク特性の面において不十分な特性となってい
る。更に、第3の手段として、キャノ4シタ面積を大き
くすることが考えられるが、素子の高集積化に適さない
。In the same equation, in order to increase the capacitance of the capacitor, the first
As a means of achieving this, it is possible to reduce the dielectric film thickness d. Regarding this, improvements in film formation have made it possible to make the film considerably thinner. For example, in a 256 RAM, the film thickness is S i O, and t = 200 to 250A. However, in the case of 5102, the dielectric constant is as low as 3.9, and in terms of film thickness, ~100 A is considered to be the limit from the viewpoint of breakdown voltage. Moreover, as a second means, Si3N4. It is conceivable to use a dielectric material with a high dielectric constant such as Ta, O, or the like. However, these dielectrics have not yet reached the level of practical use in terms of process and reliability. Recently, Ta has been formed by sputtering and 'ra
There have been several reports on the use of 2o as a dielectric material, but
It has insufficient characteristics in terms of withstand voltage and leakage characteristics. Furthermore, as a third means, it may be possible to increase the area of the canopy, but this is not suitable for high integration of elements.
本発明は、上記事情に鑑みてなされたもので、キャノ9
シタ容量を増して耐圧、リーク特性を向上した半導体装
置及びその製造方法を提供することを目的とするもので
ある。The present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a semiconductor device which has improved breakdown voltage and leakage characteristics by increasing the capacitance of the capacitor, and a method for manufacturing the same.
本願第1の発明は、半導体基板上に金属ケイ化物層の酸
化により得られる酸化物層を形成し、更にこの酸化物層
上に電極を形成した構造とすることによって、耐圧、リ
ーク特性の向上を図ったことを骨子とする。The first invention of the present application has a structure in which an oxide layer obtained by oxidizing a metal silicide layer is formed on a semiconductor substrate, and an electrode is further formed on this oxide layer, thereby improving breakdown voltage and leakage characteristics. The main points of this plan are to:
本願第2の発明は、半導体基板上に金属ケイ化物層を形
成した後、この金属ケイ化物層を酸化して酸化物層を形
成し、しかる後この酸化物層上に電極を形成することに
よって、本願第1の発明と同様な効果を得るものである
。The second invention of the present application is to form a metal silicide layer on a semiconductor substrate, oxidize the metal silicide layer to form an oxide layer, and then form an electrode on the oxide layer. , the same effect as the first invention of the present application can be obtained.
以下、本発明を図を参照して説明する。 Hereinafter, the present invention will be explained with reference to the drawings.
まず、表面の結晶方位(1oo)のシリコン基板11上
に、金属ケイ化物層として例えばTaSix調整可能で
ある。つづいて、1000℃の高温にて酸化を行なった
。その結果、Ta5iX層12は、2TaSix十y0
2= Ta205+zSiQ□となり、基板11上にS
iO2層13 、Ta20a層14が夫々形成された(
第1図(b)図示)。次いで、Ta、O,層14上にA
I又はP型不純物をドープした多結晶シリコン層を蒸着
した後、・臂ターニングして電極15を形成した(第1
図(e)図示)。First, a metal silicide layer, for example TaSix, can be prepared on a silicon substrate 11 with a surface crystal orientation (1oo). Subsequently, oxidation was performed at a high temperature of 1000°C. As a result, the Ta5iX layer 12 is 2TaSix + y0
2=Ta205+zSiQ□, and S on the substrate 11
An iO2 layer 13 and a Ta20a layer 14 were formed (
(Illustrated in FIG. 1(b)). Next, A is applied on the Ta, O, layer 14.
After depositing a polycrystalline silicon layer doped with I- or P-type impurities, the electrodes 15 were formed by turning the elbows (first
Figure (e) shown).
本発明に係る半導体装置は、第1図(e)に示す如く、
シリコン基板11上にSiO2層13、Ta2O,層1
4を順次形成し、この’ra、o、層14上に層積4上
を形成した構瀝となっている。As shown in FIG. 1(e), the semiconductor device according to the present invention has the following features:
SiO2 layer 13, Ta2O, layer 1 on silicon substrate 11
4 are sequentially formed, and the layer stack 4 is formed on these 'ra, o, and layers 14.
しかして、本発明によれば、基板11上にTa5iX層
12を形成した後、高温で酸化することにより基板11
上に8102層13、’ra、o。According to the present invention, after forming the Ta5iX layer 12 on the substrate 11, the substrate 11 is oxidized at high temperature.
8102 layer 13,'ra,o on top.
層14を夫々形成し、しかる後’ra2o。層14上に
電極15を形成することにより、第1図(e)のような
構造を有している。従って、基板11界面の膜質が良好
となり、リーク特性、耐圧の改善を達成することができ
る。以下、これについて詳述する。第1〜図(c)にお
いて、誘電体を形成する’ra、o、層14、s io
x層13の夫kF)膜厚なjl+tl!、夫々の宕量を
C1、C2と仮定すると、トータル誘電率Cは、
となる3、式(2)において、tIpt2の比は各々誘
電体の密度、分子量と反応式によりめることが可能であ
る。ここで、第1表に示すTa、0.。Form each layer 14 and then 'ra2o. By forming the electrode 15 on the layer 14, a structure as shown in FIG. 1(e) is obtained. Therefore, the film quality at the interface of the substrate 11 becomes good, and leakage characteristics and breakdown voltage can be improved. This will be explained in detail below. 1 to (c), 'ra, o, layers 14, sio forming the dielectric
x layer 13 husband kF) film thickness jl+tl! , and assuming that the respective capacitances are C1 and C2, the total dielectric constant C becomes 3. In equation (2), the ratio of tIpt2 can be determined by the density, molecular weight, and reaction formula of each dielectric. be. Here, Ta shown in Table 1, 0. .
5io2層の密度〜誘電率の値をもとに、Ta5izの
組成比又と2層のトータル誘電率、第2図に示すように
なる。Based on the density to dielectric constant values of the 5io2 layer, the composition ratio of Ta5iz and the total dielectric constant of the two layers are as shown in FIG.
第 1 表
同図により、X=0即ちTaのみ蒸着したときの誘電率
は28となって、’ratoaと一致し、まfc x
=勾でSiO2の誘電率は3.9とはソ等しく、その間
任意の値を得ることを確認できる。即ち、誘電率を任意
の値にすることによってキャパシタ容量を増すことがで
きるとともに、基板1ノの界面が5io2層13となる
ため耐圧、リーク特性を向上できる。According to Table 1 and the same figure, when X=0, that is, when only Ta is deposited, the dielectric constant is 28, which coincides with 'ratoa, and fc x
= slope, the dielectric constant of SiO2 is equal to 3.9, and it can be confirmed that any value can be obtained between them. That is, by setting the dielectric constant to an arbitrary value, the capacitor capacity can be increased, and since the interface between the substrate 1 and the substrate 1 becomes the 5io2 layer 13, the withstand voltage and leakage characteristics can be improved.
なお、上記実施例では、酸化処理を高温(1000℃)
で行なった場合について述べたが、これに限らず、60
0〜900℃の低温で酸化を行なってもよい。この場合
、第3図に示す如く、シリコン基板1ノ上に5in2と
T jLl o、との混合物層16が形成される。なお
、容量計算は、上記実施例の考えを適用できる。また、
上記実施例では、基板11上にTa5iX層12を蒸着
した後、酸化処理を施して基板11上に5102層、’
ra2o、層14を夫層形4したが、これに限らず、上
記温度範囲で長時間酸化処理を行なって第4図に示す如
く、基板11上に薄いS 102層17、及びSin、
層と’ra、o、との混合物層18を形成してもよい。In addition, in the above example, the oxidation treatment was performed at a high temperature (1000°C).
Although we have described the case where the
Oxidation may be carried out at low temperatures of 0 to 900°C. In this case, as shown in FIG. 3, a mixture layer 16 of 5in2 and TjLlo is formed on the silicon substrate 1. Note that the idea of the above embodiment can be applied to the capacity calculation. Also,
In the above embodiment, after the Ta5iX layer 12 is deposited on the substrate 11, oxidation treatment is performed to form 5102 layers on the substrate 11.
RA2O, layer 14 is formed in the double layer type 4, but the present invention is not limited to this. By performing oxidation treatment for a long time in the above temperature range, as shown in FIG.
A mixture layer 18 of 'ra,o' and 'ra,o' may be formed.
かかる場合、第2図の関係を維持できる。なお、第S図
は、Ta5iXを900℃で15分酸化処理を施したと
きのオージェ分析の特性図を示す。同図により、酸化初
期にTaが析出していることが確認できるが、更に15
分はどの酸化処理によって析出したTaを完全に酸化し
てT a20.とし、Ta、O,とS i O2の混合
絶縁体を形成できた。In such a case, the relationship shown in FIG. 2 can be maintained. In addition, FIG. S shows a characteristic diagram of Auger analysis when Ta5iX is subjected to oxidation treatment at 900° C. for 15 minutes. From the same figure, it can be confirmed that Ta is precipitated at the initial stage of oxidation, but 15
What oxidation treatment is used to completely oxidize the precipitated Ta and reduce Ta to 20. As a result, a mixed insulator of Ta, O, and SiO2 could be formed.
また、上記実施例では、金属ケイ化物層としてTa5i
z層を用いたが、これに限らず、例えばTtSi、を用
いてもよい。Further, in the above embodiment, Ta5i is used as the metal silicide layer.
Although the z layer is used, the present invention is not limited to this, and for example, TtSi may be used.
以上詳述した如く本発明によれば、耐圧、リーク特性を
向上し得る半導体装置及びその製造方法を提供できるも
のである。As described in detail above, according to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can improve breakdown voltage and leakage characteristics.
第1図(a)〜(clは本発明の一実施例に係わる半導
体装置の製造方法を工程順に示す断面図、第2図は本発
明に係わる’paSiの組成比と誘電率との関係を示す
特性図、第3図は低温酸化後のシリコン基板の断面図、
第4図は低温長時間酸化後のシリコン基板の断面図、第
5図はT a S 1 zを酸化した時のオージェ分析
を示す特性図である。
11・・・シリコン基板、12・・・’l’as i
x層(金属ケイ化物層)、13.17・・・SiO,層
、14・・・Ta0層、15 ・・・電極、16 、1
8−810.と’l’a205との混合物層。
出願人代理人 弁理士 鈴 江 武 彦tlllllJ
第2図 、
13′。
1J5WA
7゜し=qT
、粗An二FIGS. 1(a) to (cl) are cross-sectional views showing the manufacturing method of a semiconductor device according to an embodiment of the present invention in order of process, and FIG. 2 shows the relationship between the composition ratio and dielectric constant of 'paSi according to the present invention. The characteristic diagram shown in Figure 3 is a cross-sectional view of the silicon substrate after low-temperature oxidation.
FIG. 4 is a cross-sectional view of a silicon substrate after oxidation at low temperature for a long time, and FIG. 5 is a characteristic diagram showing Auger analysis when T a S 1 z is oxidized. 11...Silicon substrate, 12...'l'as i
x layer (metal silicide layer), 13.17...SiO, layer, 14...Ta0 layer, 15...electrode, 16, 1
8-810. and 'l'a205 mixture layer. Applicant's agent Patent attorney Suzue TakehikotllllllJ Figure 2, 13'. 1J5WA 7゜shi=qT, rough An2
Claims (4)
物層の酸化により得られる酸化物層と、この酸化物層上
に形成された電極とを具備することを特徴とする半導体
装置。(1) A semiconductor device comprising a semiconductor substrate, an oxide layer formed on the substrate and obtained by oxidizing a metal silicide layer, and an electrode formed on the oxide layer.
用いることを特徴とする特許請求の範囲第1項記載の半
導体装置b(2) The semiconductor device b according to claim 1, characterized in that a 'l'ag Sis layer is used as the metal silicide layer.
、この金属ケイ化物層を酸化して酸化物層を形成する工
程と、この酸化物層上に電極を形成する工程とを具備す
ることを特徴とする半導体装置の製造方法。(3) comprising the steps of forming a metal silicide layer on a semiconductor substrate, oxidizing this metal silicide layer to form an oxide layer, and forming an electrode on this oxide layer. A method for manufacturing a semiconductor device, characterized in that:
イ化物層を形成することを特徴とする特許請求の範囲第
3項記載の半導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to claim 3, wherein the metal silicide layer is formed after forming a thin oxide film on the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21905583A JPS60111451A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21905583A JPS60111451A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60111451A true JPS60111451A (en) | 1985-06-17 |
Family
ID=16729554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21905583A Pending JPS60111451A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60111451A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147470A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Semiconductor device |
JPS5810852A (en) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | Semiconductor device |
-
1983
- 1983-11-21 JP JP21905583A patent/JPS60111451A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147470A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Semiconductor device |
JPS5810852A (en) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | Semiconductor device |
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