JPH0624222B2 - Method of manufacturing thin film capacitor - Google Patents

Method of manufacturing thin film capacitor

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Publication number
JPH0624222B2
JPH0624222B2 JP1217918A JP21791889A JPH0624222B2 JP H0624222 B2 JPH0624222 B2 JP H0624222B2 JP 1217918 A JP1217918 A JP 1217918A JP 21791889 A JP21791889 A JP 21791889A JP H0624222 B2 JPH0624222 B2 JP H0624222B2
Authority
JP
Japan
Prior art keywords
thin film
dielectric constant
silicon
heat treatment
film capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1217918A
Other languages
Japanese (ja)
Other versions
JPH0380562A (en
Inventor
正吾 松原
洋一 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1217918A priority Critical patent/JPH0624222B2/en
Publication of JPH0380562A publication Critical patent/JPH0380562A/en
Publication of JPH0624222B2 publication Critical patent/JPH0624222B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、超小型電子回路に用いる薄膜コンデンサの製
造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film capacitor used in a microelectronic circuit.

(従来の技術) 集積回路技術の発達によって電子回路が、ますます小形
化しており、各種電子回路に必須の回路素子であるコン
デンサの小形化も一段と重要になっている。誘電体薄膜
を用いた薄膜コンデンサが、トランジスタ等の能動素子
と同一の基板上に形成されて利用されているが、能動素
子の小形化が急速に進む中で薄膜コンデンサの小形化は
遅れており、より一層の高集積化を阻む大きな要因とな
ってきている。これは、従来用いられている誘電体薄膜
材料がSiO2、Si3N4等のような誘電率がたかだか10以下
の材料に限られているためであり、薄膜コンデンサを小
形化するためには誘電率の大きな誘電体薄膜を開発する
ことが必要である。化学式ABO3で表されるペロブス
カイト型酸化物であるBaTiO3、SrTiO3、PbTiO3、PbZrO3
およびイルメナイト型酸化物LlNbO3あるいはBi4Ti3O12
等の強誘電体に属する酸化物は、上記の単一組成ならび
に相互の固溶体組成で、単結晶あるいはセラミックにお
いて100以上10000にも及ぶ誘電率を有することが知られ
ており、セラミック・コンデンサに広く用いられてい
る。これら材料の薄膜化は上述の薄膜コンデンサの小形
化に極めて有効であり、かなり以前から研究が行われて
いる。それらの中で比較的良好な特性が得られている例
としては、プロシーディング・オブ・アイ・イー・イー
・イー(Proceedings of thw IEEE)第59巻10号1440-1447
頁に所載の論文があり、スパッタリングによる成膜およ
び熱処理を行ったBaTiO3薄膜で16(室温で作成)から1900
(1200℃熱処理)の誘電率が得られている。
(Prior Art) With the development of integrated circuit technology, electronic circuits are becoming smaller and smaller, and it is becoming more important to make capacitors, which are circuit elements essential for various electronic circuits, smaller. Thin film capacitors using dielectric thin films are used by being formed on the same substrate as active elements such as transistors, but miniaturization of thin film capacitors has been delayed due to rapid miniaturization of active elements. , Has become a major factor preventing further high integration. This is because the dielectric thin film materials used conventionally are limited to materials with a dielectric constant of at most 10 such as SiO 2 and Si 3 N 4 , and in order to miniaturize thin film capacitors. It is necessary to develop a dielectric thin film with a large dielectric constant. BaTiO 3, SrTiO 3, PbTiO 3 is a perovskite type oxide represented by the chemical formula ABO 3, PbZrO 3
And ilmenite type oxide LlNbO 3 or Bi 4 Ti 3 O 12
It is known that oxides belonging to ferroelectrics such as, etc. have the above-mentioned single composition and mutual solid solution composition, and have a dielectric constant of 100 to 10,000 in single crystals or ceramics, and are widely used in ceramic capacitors. It is used. Thinning these materials is extremely effective for miniaturizing the above-mentioned thin film capacitor, and research has been conducted for quite some time. Among them, examples in which relatively good characteristics are obtained are Proceedings of thw IEEE Vol. 59, No. 10, 1440-1447.
There is a paper published on the page, BaTiO 3 thin films sputtered and heat-treated from 16 (created at room temperature) to 1900
A dielectric constant of (1200 ° C heat treatment) is obtained.

(発明が解決しようとする課題) しかしながら、上記のような従来作製されているBaTiO3
等の高誘電率薄膜は、高誘電率薄膜作成時に高温を必要
とするためにいずれも白金、パラジウム、金などの貴金
属材料からなる下部電極の上に作製されたものである。
このような貴金属材料の電極は、現在そのほとんどがシ
リコン基板を用いて作製されている各種の集積回路には
適合せず、したがって上記の従来技術による高誘電率薄
膜を集積回路に適用することは不可能である。上記貴金
属材料が集積回路に適合しない理由としては、それらが
不純物となってシリコン・トランジスタの動作不良を引
起こすこと、ならびにそれら貴金属の微細加工技術が確
立されていないこと等があげられる。
(Problems to be Solved by the Invention) However, BaTiO3 conventionally produced as described above is used.
The high dielectric constant thin films such as A and B are all formed on the lower electrode made of a noble metal material such as platinum, palladium, and gold because a high temperature is required for forming the high dielectric constant thin films.
Such electrodes of noble metal materials are not compatible with various kinds of integrated circuits most of which are currently manufactured using a silicon substrate. Therefore, it is not possible to apply the above-mentioned conventional high dielectric constant thin film to integrated circuits. It is impossible. The reasons why the noble metal materials are not compatible with integrated circuits include that they act as impurities to cause malfunction of silicon transistors, and that fine processing techniques for these noble metals have not been established.

シリコン集積回路に広く用いられている電極材料は多結
晶シリコンあるいはシリコン基板自体の一部に不純物を
高濃度にドーピングした低抵抗シリコン層である。以下
これらを総してシリコン電極と呼ぶ。シリコン電極は微
細加工技術が確立されており、すでに広く用いられてい
るため、シリコン電極上に良好な高誘導率薄膜が形成で
きれば、集積回路用コンデンサへの利用が可能となる。
しかしながら、従来技術では、例えばIBM・ジャーナル・
オブ・リサーチ・アンド・ディベロップメント(IBM Journa
l of Research and Development)1969年11月号686-695
頁に所載のSrTiO3膜に関する論文において、その687-68
8頁の記載に、シリコン上に高誘電率材料の薄膜を形成
する場合には約100Åの二酸化シリコン(SiO2)に等価な
層が界面に形成されてしまうと報告されている。この界
面層は誘電率が低い層であるため、結果としてシリコン
上に形成した高誘電率薄膜の実効的な誘電率は大きく低
下してしまい、高誘電率材料が用いる利点がほとんど損
なわれていた。同様の報告の他の例としては、ジャーナ
ル・オブ・バキュームサイエンス・アンド・テクノロジー(J
ournal of Vacuum Science and Technology)第16巻2 号
315-318頁に所載のBaTiO3に関する論文において、316頁
の記載にみることができる。
The electrode material widely used in silicon integrated circuits is polycrystalline silicon or a low resistance silicon layer in which a part of the silicon substrate itself is highly doped with impurities. Hereinafter, these are collectively called a silicon electrode. Since a fine processing technique has been established for silicon electrodes and is already widely used, if a good high-inductivity thin film can be formed on silicon electrodes, it can be used for capacitors for integrated circuits.
However, in the prior art, for example, IBM
Of Research and Development (IBM Journa
l of Research and Development) November 1969 686-695
687-68 in the paper on SrTiO 3 films on page
The description on page 8 reports that when a thin film of a high dielectric constant material is formed on silicon, a layer equivalent to about 100 Å silicon dioxide (SiO 2 ) is formed at the interface. Since this interface layer is a layer having a low dielectric constant, the effective dielectric constant of the high dielectric constant thin film formed on silicon was greatly reduced as a result, and the advantage of using a high dielectric constant material was almost lost. . Another example of a similar report is the Journal of Vacuum Science and Technology (J
ournal of Vacuum Science and Technology) Volume 16 Issue 2
It can be found in the description on page 316 in the paper on BaTiO 3 published on pages 315-318.

本発明はBaTiO3、SrTiO3に代表される強誘電体に属する
高誘電率材料の薄膜をシリコン電極上に形成する場合に
おいて、界面に生成する低誘電率の層の影響を極めて小
さくすることを可能とし、これをもって集積回路に適用
可能な小形の薄膜コンデンサを実現さることを目的とし
ている。
The present invention, when forming a thin film of a high dielectric constant material belonging to a ferroelectric material typified by BaTiO 3 and SrTiO 3 on a silicon electrode, makes it possible to extremely reduce the influence of a low dielectric constant layer generated at the interface. The purpose is to realize a small-sized thin film capacitor that can be applied to an integrated circuit.

(課題を解決するための手段) 上記問題点を解決するために本発明の薄膜コンデンサの
製造方法は、シリコンからなる下部電極上にBaTiO
3、SrTiO3、PbTiO3、PbZrO3、LiNb
3、Bi4Ti312から選ばれた一つの組成、あるい
は固溶体からなる高誘電率誘電体薄膜300℃以上500℃以
下の基板温度で作製し、その後550℃以上650℃以下の温
度で熱処理を施し、しかる後に上部電極を形成すること
によって作成することを特徴として構成される。
(Means for Solving the Problem) In order to solve the above-mentioned problems, a method of manufacturing a thin film capacitor according to the present invention is directed to BaTiO 3 on a lower electrode made of silicon.
3 , SrTiO 3 , PbTiO 3 , PbZrO 3 , LiNb
A high dielectric constant dielectric thin film consisting of one composition selected from O 3 and Bi 4 Ti 3 O 12 or a solid solution was prepared at a substrate temperature of 300 ° C to 500 ° C, and then at a temperature of 550 ° C to 650 ° C or less. It is characterized in that it is formed by performing heat treatment and then forming an upper electrode.

以下、実施例に基づいて本発明を詳細に説明する。Hereinafter, the present invention will be described in detail based on examples.

(実施例) 不純物としてリン(P)を高濃度にドーピングして形成し
た低抵抗層を表面に有するシリコン基板上に、RFマグ
ネトロン・スパッタ法によって50〜500nmのSrTiO3薄膜を
作製した。作製する際の基板温度を変化させると共に、
種々の温度で熱処理を行った。上部電極としてアルミニ
ウム(Al)を形成して実効誘電率とリーク電流の評価を行
った。
Example An SrTiO 3 thin film of 50 to 500 nm was prepared by RF magnetron sputtering on a silicon substrate having a low resistance layer formed by doping phosphorus (P) as an impurity at a high concentration. While changing the substrate temperature during fabrication,
Heat treatment was performed at various temperatures. Aluminum (Al) was formed as the upper electrode, and the effective dielectric constant and leakage current were evaluated.

第1図は種々の基板温度で作製したSrTiO3薄膜の、熱処
理を施さない状態で評価した実効誘電率と膜厚の関係を
示す。曲線1は基板温度400℃で作成した膜について、曲
線2は同600℃で作製した膜について、曲線3は同700℃で
作成した膜についてのデータを示す。いずれの膜におい
ても実効誘電率の膜厚依存性が顕著であり、すでに説明
した従来技術と同様に界面に低い誘電率の層が依存する
ことが明らかである。特に膜厚の小さい領域で界面低誘
電率層の影響が大きい。また、基板温度700℃では全体
的に実効誘電率の低下が著しく、高温における界面の著
しい反応を示唆している。
Figure 1 shows the relationship between the effective dielectric constant and film thickness of SrTiO 3 thin films prepared at various substrate temperatures, evaluated without heat treatment. Curve 1 shows data for a film made at a substrate temperature of 400 ° C, curve 2 shows data for a film made at 600 ° C, and curve 3 shows data for a film made at 700 ° C. The film thickness dependence of the effective permittivity is remarkable in any of the films, and it is clear that the interface of the low permittivity layer depends on the interface as in the conventional technique described above. In particular, the influence of the low dielectric constant layer at the interface is large in the region where the film thickness is small. In addition, at a substrate temperature of 700 ° C, the effective permittivity decreased as a whole, suggesting a significant interface reaction at high temperatures.

第2図は300℃〜600℃の基板温度で作製したSrTiO3薄膜
を熱処理した後の、実効誘電率と膜厚の関係を示す。曲
線1は熱処理温度550℃〜650℃の場合について、曲線2は
同700℃〜800℃の場合についてのデータを示す。第1図
と比較すると明らかなように550℃〜650℃での熱処理に
よって特に膜厚の小さい領域での実効誘電率が増大す
る。曲線2のデータからわかるように、さらに高い熱処
理温度では再び実効誘電率が低下する。以上の結果は、
550〜650℃の熱処理で界面の低誘電率層の結晶化が生じ
て実効誘電率の増大をもたらすが、700℃以上の熱処理
では界面の反応が顕著となるために実効誘電率が低下す
るものと解釈される。なお、550℃以下の熱処理温度で
は曲線2と同等以下の実施誘電率であった。
Figure 2 shows the relationship between effective permittivity and film thickness after heat treatment of SrTiO 3 thin films prepared at substrate temperatures of 300 ° C to 600 ° C. Curve 1 shows the data at a heat treatment temperature of 550 ° C to 650 ° C, and curve 2 shows the data at a temperature of 700 ° C to 800 ° C. As is clear from comparison with FIG. 1, heat treatment at 550 ° C. to 650 ° C. increases the effective dielectric constant particularly in the region where the film thickness is small. As can be seen from the data in curve 2, the effective permittivity decreases again at higher heat treatment temperatures. The above results are
Heat treatment at 550 to 650 ° C causes crystallization of the low dielectric constant layer at the interface to increase the effective permittivity, but heat treatment at 700 ° C or higher decreases the effective permittivity due to significant interface reaction. Is interpreted as At the heat treatment temperature of 550 ° C. or lower, the actual dielectric constant equal to or lower than that of the curve 2 was obtained.

第3図は550〜650℃で熱処理した膜厚100nmの膜につい
て、10Vの電圧を印加した時のリーク電流と作製時の基
板温度との関係を示したものである。300℃以下の基板
温度で作製した膜では熱処理時に大きな歪みが発生し、
ひどい場合にはクラックを生じるためにリーク電流が大
きくなる。一方、500℃以上の基板温度で作製した膜で
は作製時におけるシリコンとの反応によりリーク電流が
大きいものと解釈される。第3図から、300〜500℃の基
板温度で作製した膜においてのみ、実用レベルのリーク
電流(10-9A/cm2以下)に抑えることができることがわか
る。
FIG. 3 shows the relationship between the leak current when a voltage of 10 V is applied and the substrate temperature at the time of fabrication for a film having a thickness of 100 nm that has been heat-treated at 550 to 650 ° C. A film produced at a substrate temperature of 300 ° C or less causes large strain during heat treatment,
In a severe case, a crack is generated and a leak current becomes large. On the other hand, it is interpreted that a film produced at a substrate temperature of 500 ° C. or higher has a large leak current due to a reaction with silicon during the production. From FIG. 3, it can be seen that the leak current at a practical level (10 −9 A / cm 2 or less) can be suppressed only in the film formed at the substrate temperature of 300 to 500 ° C.

以上のデータを総合的に見ることにより、実用的に意味
ある薄厚である100nm付近において実用的に価値ある値
として100以上の高い実効誘電率と同時に低いリーク電
流を達成する作製方法として、300℃以上500℃以下の基
板温度で成膜した後に550℃以上650℃以下の温度で熱処
理を施すという本発明がなされたものである。
Comprehensively looking at the above data, as a fabrication method that achieves a high effective dielectric constant of 100 or more as a practically valuable value and a low leakage current at a practically meaningful thin thickness of 100 nm, a 300 ° C The present invention has been made in which a film is formed at a substrate temperature of 500 ° C. or higher and a heat treatment is performed at a temperature of 550 ° C. or higher and 650 ° C. or lower.

以上はSrTiO3薄膜について説明したが、この他にBaTi
O3、PbTiO3、PbZrO3、LiNbO3、Bi4Ti3O12および固溶体
(Ba、Sr)TiO3、(Ba、Pb)TiO3、Pb(Zr、Ti)O3について同
様の作製、評価を行った結果、SrTiO3の場合と同様の作
製方法において最も高い実効誘電率と低いリーク電流が
得られることが確認された。すなわち本発明による薄膜
コンデンサの製造方法は、上記のような強誘電体に属す
る高誘電率酸化物の広い範囲の材料について有効であ
る。なお、本実施例では薄膜の作製方法としてRFマグネ
トロン・スパッタ法を用いたが、本発明はスパッタ法、
イオンビームスパッタ法、蒸着法などの物理的気相成長
法のすべての手法が適用できることは言うまでもない。
The above is the description of the SrTiO 3 thin film.
O 3 , PbTiO 3 , PbZrO 3 , LiNbO 3 , Bi 4 Ti 3 O 12 and solid solution
(Ba, Sr) TiO 3 , (Ba, Pb) TiO 3 , Pb (Zr, Ti) O 3 the same preparation and evaluation results, the highest effective dielectric constant in the same preparation method as SrTiO 3 It was confirmed that a low leakage current was obtained. That is, the method for manufacturing a thin film capacitor according to the present invention is effective for a wide range of materials of high dielectric constant oxides belonging to the above-mentioned ferroelectrics. In this example, the RF magnetron sputtering method was used as the method for forming the thin film, but the present invention is the sputtering method,
It goes without saying that all methods of physical vapor deposition methods such as the ion beam sputtering method and the vapor deposition method can be applied.

(発明の効果) 以上説明したように本発明によれば、シリコンからなる
下部電極の上に実効誘電率が高くリーク電流の小さい高
誘電率電体薄膜か作製でき、したがって集積回路に適し
た小形の薄膜コンデンサの製造が可能となり、一層の高
集積化に貢献することができる。
(Effect of the Invention) As described above, according to the present invention, a high dielectric constant thin film having a high effective dielectric constant and a small leak current can be formed on a lower electrode made of silicon, and therefore a small size suitable for an integrated circuit can be obtained. It is possible to manufacture the thin film capacitor of, and it is possible to contribute to higher integration.

【図面の簡単な説明】[Brief description of drawings]

第1図は熱処理を施す前のSrTiO3膜の実効誘電率と膜厚
の関係を示す図、第2図は300〜600℃の基板温度で作製
したSrTiO3膜の熱処理後の実効誘電率と膜厚の関係を示
す図、第3図は550〜650℃で熱処理を施したSrTiO3膜に
ついて、作製時の基板温度とリーク電流の関係を示す
図。
Figure 1 shows the relationship between the effective permittivity and film thickness of the SrTiO 3 film before heat treatment, and Figure 2 shows the effective permittivity after heat treatment of the SrTiO 3 film prepared at a substrate temperature of 300 to 600 ° C. FIG. 3 is a diagram showing the relationship between the film thickness, and FIG. 3 is a diagram showing the relationship between the substrate temperature and the leak current at the time of manufacturing the SrTiO 3 film subjected to the heat treatment at 550 to 650 ° C.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上にシリコンからなる下部電極、高誘
電率誘電体薄膜、上部電極を積層形成する工程を有する
薄膜コンデンサの製造方法において、該高誘電率誘電体
薄膜は、BaTiO3、SrTiO3、PbTiO3、P
bZrO3、LiNbO3、Bi4Ti312から選ばれた
一つの組成、あるいは固溶体からなり、該下部電極の上
に300℃以上500℃以下の基板温度で作成した後5
50℃以上650℃以下の温度で熱処理を施し、しかる
後に上部電極を形成することを特徴とする薄膜コンデン
サの製造方法。
1. A method of manufacturing a thin film capacitor comprising a step of laminating a lower electrode made of silicon, a high dielectric constant dielectric thin film and an upper electrode on a substrate, wherein the high dielectric constant dielectric thin film is made of BaTiO 3 or SrTiO 3 . 3 , PbTiO 3 , P
One composition selected from bZrO 3 , LiNbO 3 , and Bi 4 Ti 3 O 12 or a solid solution, which is formed on the lower electrode at a substrate temperature of 300 ° C. or more and 500 ° C. or less and then 5
A method of manufacturing a thin film capacitor, characterized by performing heat treatment at a temperature of 50 ° C. or higher and 650 ° C. or lower, and then forming an upper electrode.
JP1217918A 1989-08-23 1989-08-23 Method of manufacturing thin film capacitor Expired - Lifetime JPH0624222B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1217918A JPH0624222B2 (en) 1989-08-23 1989-08-23 Method of manufacturing thin film capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1217918A JPH0624222B2 (en) 1989-08-23 1989-08-23 Method of manufacturing thin film capacitor

Publications (2)

Publication Number Publication Date
JPH0380562A JPH0380562A (en) 1991-04-05
JPH0624222B2 true JPH0624222B2 (en) 1994-03-30

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Country Link
JP (1) JPH0624222B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424958A (en) * 1990-05-15 1992-01-28 Mitsubishi Materials Corp Structure of capacitive element
EP0514149B1 (en) * 1991-05-16 1995-09-27 Nec Corporation Thin film capacitor
JPH06349218A (en) * 1993-04-12 1994-12-22 Sony Corp Magneto-optical disc device
JPH0855449A (en) * 1994-08-11 1996-02-27 Sony Corp Disk driving device
US6352889B1 (en) 1998-01-08 2002-03-05 Matsushita Electric Industrial Co., Ltd. Method for fabricating capacitor and method for fabricating semiconductor device

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