JPS6262472B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitor suitable as a passive element in a semiconductor integrated circuit, etc., and a method for manufacturing the same.

Junction capacitance or MOS structure capacitance is used as a capacitor element in semiconductor integrated circuits.
The dielectric of the capacitor element in the latter MOS structure is
Currently, most of them are made of silicon dioxide (SiO ₂ ).

Silicon dioxide is a suitable material used for various purposes in current semiconductor integrated circuits.
MOS dynamic random access memory (hereinafter abbreviated as MOS RAM) will be explained. The structural unit of this MOS RAM is called a memory cell, and FIG. 1 shows an equivalent circuit of one element memory cell.

In the memory cell shown in FIG. 1, MOS transistor 1 is a transfer transistor that turns on only when word line 2 is selected and transfers charges so that digit line 3 and the transistor side electrode of MOS capacitor 4 have the same potential. . Writing information to a memory cell involves selecting the word line 2 and accumulating charge in the MOS capacitor 4, which is set to the same potential as the digit line 3. Reading information is performed by selecting the word line 2 and storing charge in the MOS capacitor 4, which is set to the same potential as the digit line 3. This is the detection of the difference between the potential after the dummy cell is connected to the precharged digit line and the potential changed by the movement of charge between the word line 2 and the MOS capacitor 4 when the word line 2 is selected. A change in the potential of the digit line 3 when the word line 2 is selected, ΔV _D , is given by the following equation.

△V _D =C/C+ _CD (V _C -V _D ) In the above formula, C... Capacity of MOS capacitor 4 C _D ... Distributed capacitance of digit line 3 (5 in Figure 1) V _C ... MOS capacitor Voltage V _D across the digit line 3 is the voltage across the distributed capacitance C _D of the digit line 3. From the above equation, in order to increase ΔV _D , it is necessary to increase V _C or increase the ratio of C to _CD .

FIG. 2 is a sectional view showing the structure of the most common type of MOS RAM. A polycrystalline silicon layer is formed on the substrate 6 with a silicon dioxide layer 9 interposed therebetween, with the n ⁺ region 7 provided on the P-type silicon substrate 6 and the inversion layer 8 formed on the surface of the substrate 6 functioning as a source or drain. The n ⁺ region 7 of the transfer transistor with gate 10 is connected to the n ⁺ regions of many other memory cells to form a digit line. The inversion layer 8 constitutes one electrode of the MOS capacitor, the polycrystalline silicon layer 11 is the opposite electrode, and the silicon dioxide layer 9 interposed therebetween is a dielectric.

Since the digit line connects a large number of memory cells, the amount of wiring distribution is large, and in the current 64k-bit MOS RAM, C _D /C is about 15 times as large. Even if a sufficient logic level charge corresponding to 1 is stored, the read signal is only about 100 mV. For this reason, the sense amplifier that detects and amplifies this read signal must be highly sensitive. In order to increase this read signal as much as possible, relax the operating conditions of the sense amplifier, and eliminate malfunctions due to noise voltage, it is necessary to provide the capacitor 4 of the memory cell with as large a capacitance as possible. It is. For this purpose, the planar arrangement of the memory cells is devised to maximize the area of the capacitor and to minimize the thickness of the silicon dioxide layer 9. One way to overcome the limitations of this method and further improve the degree of integration of memory cells is to change the point that the transfer transistor and capacitor are on the same plane and maximize the capacitor area by multilayering. Other methods use silicon nitride ( _{Si 3} ^N ₄ ) (ε _s =5 to 7), and by using tantalum oxide (ε _s =20 to 28) as a dielectric material, the capacitance density is increased.

Tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), hafnium (Hf), vanadium (V) are
Along with aluminum (Al) and silicon (Si), it is known as a film-forming metal or valve metal. These metals, especially tantalum, can be processed to a technically selected thickness by anodization, thermal oxidation, etc., either as a single metal, or in the form of an alloy or a compound with nitrogen, etc. The formed oxide has superior chemical and physical stability compared to aluminum oxide, etc., and can withstand large electric field strengths and reduce leakage current as a dielectric material of capacitors. It has features such as low dielectric constant and high dielectric constant.

Capacitors using tantalum oxide (Ta ₂ O ₅ ) as a dielectric material, which are used in thin-film integrated circuits, contain manganese dioxide (MnO ₂ ) or lead dioxide (PbO ₂ ), etc., which are laminated in contact with the tantalum oxide layer. There are two types of capacitors: one has a solid electrolyte layer, and the other has no solid electrolyte layer.

In a capacitor having a solid electrolyte layer, this solid electrolyte layer, for example, a manganese dioxide layer, is produced by thermally decomposing a manganese nitrate Mn(NO ₃ ) ₂ solution at a temperature of 200-400°C and depositing it on the surface of the tantalum oxide layer as manganese dioxide. It forms a part of the electrode structure, and has the function of recovering a dielectric breakdown point in the tantalum oxide layer by the oxidizing action of oxygen generated from the breakdown point. Because of this recovery effect, the tantalum oxide layer is made thinner, about 100 nm, compared to capacitors with a structure that does not have a solid electrolyte layer, and capacitance densities of about 2000 PF/mm ² have been put into practical use.

On the other hand, capacitors that use tantalum oxide as a dielectric and do not have a solid electrolyte layer have an increase in the capacitance temperature coefficient or loss coefficient, or an increase in the capacitance and loss frequency due to the solid electrolyte layer forming part of the electrode. Although it is possible to solve the problem of deterioration in characteristics, the thickness of the tantalum oxide layer must be 300 to 500 nm or more, and the capacitance density can be stably put into practical use.
It is estimated to be around 400PF/mm ² to 600PF/mm ² .

Comparing the above two types of structures, tantalum oxide capacitors having a solid electrolyte layer are preferable from the standpoint of increasing capacity density, but manganese dioxide, which is commonly used as a solid electrolyte, decomposes at about 450°C, and oxygen Heating above this level is not allowed because it releases oxides and becomes a low-level oxide, which loses its intended function. The same applies to lead dioxide, and this structure is inappropriate as a capacitor element for a semiconductor integrated circuit.

Furthermore, in many examples of tantalum oxide capacitors for thin film integrated circuits, an unoxidized tantalum metal monomer or the like is left as one electrode. This structure is disadvantageous in controlling the thickness of the tantalum oxide layer when thermal oxidation is used, and although there are differences depending on the structure of the tantalum metal layer, oxygen in the tantalum oxide is trapped inside the unoxidized metal. Thermal diffusion phenomenon can occur at temperatures above about 200℃, and when exposed to high temperatures in subsequent processes, tantalum silicide may be generated due to the interfacial reaction between metal tantalum and silicon, which may cause instability. have a problem.

Based on the above reasons, FIG. 3 shows an experimental example of a MOS RAM equipped with a tantalum oxide capacitor element that does not have a tantalum metal layer or a solid electrolyte layer. In this figure, a polycrystalline silicon layer 12, a tantalum oxide layer 13, and a polycrystalline silicon layer 14 form a capacitor element. A structure similar to this experimental example was developed by k. Ohta et al. in the ISSCC Dig.
Reported in Technical Papers (1980.p.66).

This document indicates the use of an amorphous tantalum oxide film as a dielectric, but amorphous tantalum oxide crystallizes when placed at high temperatures, and the leakage current through the layer increases thereafter, making it difficult to use for memory devices. It was previously recognized that this significantly deteriorates the charge retention characteristics that are important for capacitors.

For this reason, for example, when forming the insulating layer 15, a high temperature atmosphere of about 900° C. or higher is usually required.
After forming the tantalum oxide layer, manufacturing methods that have traditionally been considered optimal for semiconductor integrated circuits, such as not using the CDV method (chemical vapor deposition method) but relying on plasma CVD methods or sputtering methods that can be formed at low temperatures, are used. The manufacturing cost increases due to changing the manufacturing method to one that can be carried out at low temperatures in order to prevent the progression of corrosion, and the characteristics of the interlayer insulating layer itself, such as moisture resistance and level difference mitigation ability, are inferior to those formed at high temperatures. This has been considered a problem in increasing the capacitance density by using tantalum oxide as a dielectric material.

In order to solve the above-mentioned problems, the present invention is designed to withstand high-temperature processing of approximately 1000°C in the manufacturing process of semiconductor devices including the same, and to be superior to similar capacitors for thin film integrated circuits in terms of capacitance density and leakage current. The purpose of the present invention is to obtain a capacitor element with high performance and a method for manufacturing the same.

In the process leading to the present invention, the inventor formed a tantalum layer with a thickness of about 20 nm on an n-type polycrystalline silicon layer by sputtering, and then completely oxidized the tantalum layer in dry oxygen at about 500°C. An amorphous tantalum oxide layer was obtained. After heating this to 800°C to 1000°C for 30 minutes each, we analyzed changes in the composition of the film in the depth direction using an ion microanalyzer, and found that silicon had diffused into the tantalum dioxide region.

The present inventor determined that it is possible to reduce leakage current by oxidizing the silicon that has moved to the grain boundaries due to this thermal diffusion and converting it into silicon dioxide, which is a good electrical insulating material, and has developed the present invention. I got it.

That is, in the present invention, after forming an amorphous tantalum oxide layer in contact with a polycrystalline silicon layer, etc., this is kept at a high temperature higher than the crystallization temperature of the amorphous tantalum oxide in an oxidizing atmosphere, and the tantalum oxide is crystallized. By diffusing silicon into grain boundaries that occur during crystallization and oxidizing them, the grain boundaries are filled with silicon dioxide and the conduction path for leakage current is blocked.

4a, b, and c are cross-sectional views schematically showing the state of the capacitor element according to the present invention, and FIG. 4a shows a tantalum oxide layer 17 formed in an amorphous state on a polycrystalline silicon layer 16. ing.

FIG. 4b shows the state in which the capacitor element in the state shown in FIG. 4a is heated at 800° C. for 30 minutes, and the tantalum oxide 17 is crystallized and silicon is diffused into its crystal grain boundaries 18. FIG. 4c shows the state in which the capacitor element in the state of FIG. Filled with silicon 19.

FIG. 5 is a diagram showing changes in the characteristics of the tantalum oxide layer, in which the horizontal axis represents the heat treatment temperature, and the vertical axis represents leakage current and dielectric constant. Crystallization of tantalum oxide partially begins at around 450℃, but crystallization progresses above 600℃, and
Thermal diffusion of silicon is active, causing a rapid increase in leakage current. Note that the dielectric constant increases as crystallization progresses. As mentioned above, the leakage current decreases rapidly at high temperatures exceeding 800℃, and the results of heat treatment at 1000℃ show that
Excellent results of less than 5×10 ^-9 A/cm ² were obtained at an electric field of 1 MV/cm. Also, the dielectric constant of silicon dioxide is much smaller than that of tantalum oxide, but since the area occupied by the crystal grain boundaries is small compared to the total area of the capacitor element, the dielectric constant as a capacitor element is It maintains a sufficient value of 20 or more. Thus, according to the present invention, an excellent dielectric material with far less leakage current and an equally large dielectric constant compared to conventional amorphous tantalum oxide was obtained.

The dielectric layer treated by the method of the present invention maintains stable characteristics even when placed at high temperatures of about 900°C to 1000°C to form an interlayer insulating layer after forming a capacitor element, and increases leakage current. etc., and can be treated in the same manner as silicon dioxide, etc.

The present invention will be explained below according to an embodiment thereof using the drawings.

FIG. 6 is a cross-sectional view showing the state of a MOS RAM memory cell during the manufacturing process. By a well-known method, a gate 24 made of polycrystalline silicon is provided on a P-type silicon substrate 20 with n ⁺ regions 21 and 22 serving as a source or drain interposed therebetween and an insulating layer 23 made of silicon dioxide. Next, a polycrystalline silicon layer 25 is formed to a thickness of about 200 nm by a well-known method such as silane (SiH ₄ ) thermal decomposition method. This polycrystalline silicon layer 25 becomes one electrode of the intended capacitor element, and is doped to have the same n-type polarity as the source and drain electrodes.

FIG. 7 is a sectional view showing a state following the previous figure.
First, a tantalum layer with a thickness of about 20 nm is formed on the polycrystalline silicon layer 25. This tantalum layer can be formed by electron beam heating vacuum evaporation, but even better results can be obtained by sputtering.
Next, the substrate is placed in a dry oxygen atmosphere at about 500° C. for about 30 minutes to completely oxidize the tantalum layer to obtain the tantalum oxide layer 26. In this oxidation process, tantalum changes into an oxide because it is easily oxidized, but the polycrystalline silicon forming the layer 25 below it is not noticeably oxidized unless it is at least 900°C or higher, so tantalum is not uniform. A tantalum oxide layer with good properties can be easily obtained. Subsequently, the substrate is placed in a dry oxygen atmosphere at about 1000° C. for about 30 minutes. Through this heat treatment, as described above, tantalum oxide is crystallized, and the silicon diffused from the polycrystalline silicon layer 25 to the crystal grain boundaries generated by the crystallization is oxidized, and the crystal grain boundaries are insulated with silicon dioxide as the main component. Filled with things.

If the heat treatment time is extended, the leakage current will be reduced, but on the other hand, the oxidation of the surface of the polycrystalline silicon layer 25 will progress, and the capacitance density of the capacitor element will be reduced.

FIG. 8 is a sectional view showing a state following the previous figure.
A polycrystalline silicon layer 27, which will become an upper electrode, is formed on the crystallized tantalum oxide layer 26. This polycrystalline silicon layer 27 can be formed without any concern by a silane thermal decomposition method at a reaction temperature of about 900°C. Subsequently, a pattern as a capacitor element is formed by photoetching. Next, an insulating layer 28 made of silicon dioxide or phosphosilicate glass (hereinafter referred to as PSG), and an aluminum wiring layer 29 serving as a digit line are formed to form a structure similar to that shown in FIG. 3. However, this embodiment differs in the structure of the insulating layer 28 when compared with the known example cited in FIG. has been created.

That is, by carrying out the present invention, it has become possible to carry out a manufacturing method that requires a high temperature of about 1000°C, so that it is possible to carry out a manufacturing method that requires a high temperature of about 1000°C. PSG, which requires about 1000℃ for remelting for flow technology, and 900 to 1000℃ for densification.
This is due to the fact that it has become possible to utilize silicon dioxide produced by chemical vapor deposition, which requires temperatures at ℃. As a result, a reliable wiring layer can be formed even in a structure in which a large step difference occurs in the three-dimensional structure as in this embodiment. The capacitance density of the capacitor element in this example is approximately 5000PF/mm ² , and the leakage current is approximately 2×10 ^-3 A/FV.
and has fully achieved its purpose.

In the above embodiments, dry oxygen was used as the atmosphere during the heat treatment for crystallizing tantalum oxide and oxidizing silicon, but it is also effective to use humidified oxygen containing water vapor. Silicon oxidizes quickly in a humidified oxygen atmosphere, so compared to dry oxygen, the same result can be obtained by shortening the time or lowering the temperature, and if the temperature and time are the same, the leakage current,
Capacity density also decreases.

Furthermore, crystallization of tantalum oxide and silicon diffusion into the tantalum oxide layer can be achieved by heat treatment in a non-oxidizing atmosphere such as nitrogen, or in an oxidizing atmosphere at a temperature at which oxidation of silicon does not proceed significantly. Even if the silicon is oxidized by the heat treatment in the oxidizing atmosphere after the above-mentioned oxidizing atmosphere, the same results as in the above embodiment can be obtained.

In addition, we actively introduce silicon atoms into the tantalum oxide layer to prevent silicon atoms from segregating at grain boundaries with incomplete crystallinity, film defects, etc. during the crystallization process of tantalum oxide. This silicon atom may be oxidized using the silicon atom. Specifically, this method involves incorporating silicon into the metal tantalum when depositing it, or by oxidizing the tantalum and then introducing silicon atoms into the film by ion implantation or the like. can be carried out.

Next, in the above embodiment, the electrode material of the capacitor element was polycrystalline silicon, but the lower electrode was made of the single crystal silicon of the substrate or a layer of metal silicide such as molybdenum silicide (MoSi ₂ ) instead of polycrystalline silicon. However, the same effect as in the above embodiment can be obtained, and the upper electrode may be made of a metal layer such as molybdenum (Mo) or gold (Au) in addition to the above-mentioned materials.

Furthermore, in the above embodiment, tantalum oxide was used as the dielectric material of the capacitor element, but oxides of titanium, niobium, zirconium, tungsten, hafnium, and vanadium also have properties similar to tantalum oxide, and are susceptible to crystallization of the oxide layer. Regarding leakage current, there is a phenomenon similar to that described above, and the present invention can be applied to this phenomenon.

In particular, titanium oxide (TiO ₂ ) has a very high dielectric constant of about 100, but has a disadvantage of having a large leakage current, so the present invention is a very effective means.

As stated in the above explanation, the present invention provides tantalum,
An oxide of the metal such as titanium is used as the dielectric of the capacitor element, and the metal oxide is crystallized in an oxidizing high-temperature atmosphere, and the crystal grain boundaries generated by the crystallization are diffused from the electrode in contact with the oxidation of silicon. The level of capacitors for thin-film integrated circuits that can withstand high-temperature processing of around 1000°C by being filled with material and can utilize manufacturing methods that are currently suitable for semiconductor integrated circuits, and that use the same type of metal oxide as a dielectric. The present invention provides a capacitor with a capacitance density exceeding that of the previous one, and a leakage current comparable to that of the previous capacitor, and a method for manufacturing the same. Although the present invention is intended for implementation in semiconductor integrated circuits, it can also be applied to thin film integrated circuits or individual circuit components.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of a memory cell that is an example of a capacitor element, Figure 2 is a cross-sectional view showing the main parts of the structure of a conventional memory cell, and Figure 3 is an experimental example of a memory cell using conventional technology. FIG. 4 is a cross-sectional view showing the state of the dielectric layers in a, b, and c. FIG. 5 is a characteristic chart for explaining the effects of the present invention. and FIG. 8 are cross-sectional views showing one embodiment of the present invention. 1...MOS transistor, 2...word line,
3...digit wire, 4...MOS capacitor,
5... Distributed capacitance of digit line, 6... P-type silicon substrate, 7... n ⁺ region, 8... Inversion layer, 9...
... silicon dioxide layer, 10 ... polycrystalline silicon layer, 11 ... polycrystalline silicon layer, 12 ... polycrystalline silicon layer, 13 ... tantalum oxide layer, 14 ...
Polycrystalline silicon layer, 15... Insulating layer, 16... Polycrystalline silicon layer, 17... Tantalum oxide layer, 18
...Grain boundary, 19...Silicon dioxide, 20...
...P-type silicon substrate, 21...n ⁺ region, 22...
...n ⁺ region, 23...insulating layer, 24...gate,
25... Polycrystalline silicon layer, 26... Tantalum oxide layer, 27... Polycrystalline silicon layer, 28... Insulating layer, 29... Wiring layer.

Claims (1)

[Claims] 1. Oxidation of at least one metal among tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), hafnium (Hf), or vanadium (V). In a capacitor in which the dielectric layer is a film formed on a conductive substrate or layer serving as an electrode, the metal oxide is crystallized, and the metal oxide is formed at the grain boundaries of the dielectric layer. A capacitor characterized in that it is filled with a conductive substrate or layer, or a silicon oxide formed of silicon diffused from the metal oxide. 2 A film made of an oxide of at least one metal among tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), hafnium (Hf), or vanadium (V). , a method for manufacturing a capacitor comprising the step of forming a dielectric layer on a conductive substrate or layer serving as an electrode, crystallizing the metal oxide,
and a capacitor comprising the step of diffusing silicon into the metal oxide layer from the conductive substrate or layer serving as the electrode, and oxidizing the silicon diffused into the metal oxide layer to form silicon oxide. manufacturing method.