JPH0656877B2 - Method for producing tantalum oxide thin film - Google Patents
Method for producing tantalum oxide thin filmInfo
- Publication number
- JPH0656877B2 JPH0656877B2 JP62228872A JP22887287A JPH0656877B2 JP H0656877 B2 JPH0656877 B2 JP H0656877B2 JP 62228872 A JP62228872 A JP 62228872A JP 22887287 A JP22887287 A JP 22887287A JP H0656877 B2 JPH0656877 B2 JP H0656877B2
- Authority
- JP
- Japan
- Prior art keywords
- tantalum oxide
- thin film
- film
- oxide thin
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 title claims description 30
- 229910001936 tantalum oxide Inorganic materials 0.000 title claims description 30
- 239000010409 thin film Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000007800 oxidant agent Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 38
- 239000003990 capacitor Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229910021480 group 4 element Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 206010021143 Hypoxia Diseases 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は、半導体素子などの電子デバイスにおける例え
ばキャパシタのための誘電体材料として用いられる酸化
タンタル薄膜の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for producing a tantalum oxide thin film used as a dielectric material for, for example, a capacitor in an electronic device such as a semiconductor element.
＜従来の技術＞ 近年、DRAMなどの半導体素子においては、微細化、高集
積化が進んでおり、これらに使用するキャパシタの面積
は、ますます縮小が望まれている。しかし、面積の縮小
をしてもメモリを保持するに必要な電荷量には限界があ
り、最小限の容量は保たれなければならない。<Prior Art> In recent years, semiconductor elements such as DRAMs have been miniaturized and highly integrated, and the area of capacitors used for these has been desired to be further reduced. However, even if the area is reduced, there is a limit to the amount of electric charge required to hold the memory, and the minimum capacity must be maintained.
従来、キャパシタの誘電膜は、形成のしやすさなどから
誘電率が約３．９のシリコン酸化膜が用いられてきた
が、必要容量を保持するためには、その膜厚を更に薄く
しなければならない。膜厚を薄くすると誘電膜には高電
界が印加され、その結果、絶縁破壊によって素子が破壊
されるという危険が生じる。現在の4MDRAMにおいては、
メモリキャパシタに使用するシリコン酸化膜はすでに絶
縁破壊耐圧から、信頼性が保証できる限界の膜厚で使用
している状況にある。Conventionally, a silicon oxide film having a dielectric constant of about 3.9 has been used as the dielectric film of a capacitor because of its ease of formation. However, in order to maintain the required capacitance, the film thickness must be made thinner. I have to. When the film thickness is made thin, a high electric field is applied to the dielectric film, and as a result, there is a risk that the device is destroyed by dielectric breakdown. In the current 4M DRAM,
The silicon oxide film used for the memory capacitor is already in a state of being used with a film thickness of the limit that can guarantee the reliability because of the dielectric breakdown voltage.
そのため今後の集積化デバイスにおいては、より高い誘
電率を有する誘電膜を使用し、キャパシタ面積を縮小す
る方法が研究されている。この中で最も有望視されてい
るものには、酸化タンタル、酸化チタンなどがある。Therefore, in future integrated devices, a method of using a dielectric film having a higher dielectric constant to reduce the capacitor area has been studied. Among these, the most promising are tantalum oxide and titanium oxide.
酸化タンタル薄膜は、スパッタ法、熱酸化法、陽極酸化
法、ＣＶＤ法、光ＣＶＤ法などで形成することができ、
誘電率はＳi の５〜６倍であり、これによって大幅な面
積縮小が望める。The tantalum oxide thin film can be formed by a sputtering method, a thermal oxidation method, an anodic oxidation method, a CVD method, an optical CVD method, or the like,
The permittivity is 5 to 6 times that of Si, and it is expected that the area will be greatly reduced.
しかし、これらの高誘電体膜は絶縁性の面で、シリコン
酸化膜よりも劣っている。即ち、酸化タンタルを５００
℃以下の温度で形成すると、一般にアモルファス状態と
なる。高温で形成した酸化タンタル膜は、通常、結晶化
しており、結晶粒界を通じて電流が流れやすいことから
絶縁性に問題があり実用化は困難である。この面からは
低温形成膜が有利であるが、低温形成膜には安定な化学
量論組成から組成のずれが有り、この膜中の酸素欠損が
電流の通路となるため、通常の状態では実用可能な絶縁
性の高い膜は得られない。そのため、保持している電荷
がリーク電流で放出され、メモリーの保持が困難になる
ことから実用化が遅れている。このリーク電流を低減す
るためには、何等かの方法で欠陥を減らしてやる必要が
ある。例としては、ＣＶＤ法で酸化タンタルを形成する
際、Ｔi を含む原料ガスを混入させて、５価のＴa を４
価の元素であるＴi で置換することで実質的に酸素欠損
を解消する方法が発表されている。（IEDM Tech.Dig.,2
9−6.PP.680−683,1986） また、光ＣＶＤによる酸化タンタル膜は比較的絶縁特性
に優れ、特に膜形成後のアニールによって膜中の酸素欠
損を排除する処理を追加することにより、実用的な特性
が得られている。（Extended abstracts of the 19th C
onference on Solid State Devices and Materials,Tok
yo,1987） ＜発明が解決しようとする問題点＞ 上記従来技術、特に光ＣＶＤ酸化タンタルの光酸素アニ
ール時において酸素欠損を解消する場合、比較的簡単な
プロセスですぐれた誘電膜を形成することができるとい
う利点がある反面、下地がSiまたは、シリサイドなどの
ように成分としてＳi を含んでいる必要があり、キャパ
シタ等として用いる場合に電極材料が限られることから
実使用においてはプロセス及び適用機器に制限があっ
た。However, these high dielectric films are inferior to the silicon oxide film in terms of insulating property. That is, 500 tantalum oxide
When it is formed at a temperature of ℃ or less, it is generally in an amorphous state. The tantalum oxide film formed at a high temperature is usually crystallized and a current easily flows through the crystal grain boundaries, so that there is a problem in the insulating property and it is difficult to put it into practical use. From this point of view, the low-temperature formed film is advantageous, but the low-temperature formed film has a composition deviation from the stable stoichiometric composition, and oxygen deficiency in this film serves as a current path, so it is practically used under normal conditions. A possible highly insulating film cannot be obtained. Therefore, the held electric charge is released as a leak current, which makes it difficult to hold the memory, which delays its practical application. In order to reduce this leak current, it is necessary to reduce defects by some method. As an example, when tantalum oxide is formed by the CVD method, a raw material gas containing Ti is mixed to change the pentavalent Ta to 4
A method of substantially eliminating oxygen deficiency by substituting Ti, which is a valent element, has been announced. (IEDM Tech.Dig., 2
9-6.PP.680-683,1986) In addition, the tantalum oxide film formed by photo-CVD has relatively excellent insulating properties, and in particular, by adding a treatment for eliminating oxygen vacancies in the film by annealing after film formation, Practical characteristics are obtained. (Extended abstracts of the 19th C
onference on Solid State Devices and Materials, Tok
yo, 1987) <Problems to be solved by the invention> In order to eliminate oxygen vacancies in the above-mentioned conventional technique, especially in photo-oxygen annealing of photo-CVD tantalum oxide, it is necessary to form an excellent dielectric film by a relatively simple process. On the other hand, it is necessary to contain Si as a component such as Si or silicide, and the electrode material is limited when it is used as a capacitor, etc. in the actual use because of the advantage that it is possible to process and applied equipment. There was a limit.
本発明は、これら欠陥を解消する元素をイオン注入によ
って膜中に導入し、その後の処理を通じて安定でリーク
電流の小さい酸化タンタル膜を下地材料の成分に関係な
く形成することを目的とする。An object of the present invention is to introduce an element that eliminates these defects into the film by ion implantation, and to form a stable tantalum oxide film having a small leakage current regardless of the composition of the underlying material through subsequent processing.
＜問題を解決するための手段＞ 本発明は、酸化タンタル薄膜の製造方法に係り、低温プ
ロセスにより非晶質酸化タンタル薄膜を形成後、４属元
素をイオン注入法によって上記薄膜内に注入し、その
後、光エネルギーまたは高周波電界によって活性化した
酸化剤を含む酸化雰囲気中で熱処理することを特徴とす
る酸化タンタル薄膜の製造方法である。<Means for Solving the Problem> The present invention relates to a method for producing a tantalum oxide thin film, in which an amorphous tantalum oxide thin film is formed by a low temperature process, and then a Group 4 element is implanted into the thin film by an ion implantation method. After that, a heat treatment is carried out in an oxidizing atmosphere containing an oxidant activated by light energy or a high frequency electric field, which is a method for producing a tantalum oxide thin film.
＜発明の作用＞ 本発明の方法によれば、酸化タンタル薄膜の欠陥を軽減
或いは解消する元素イオン注入法によって膜中に導入す
るため、Ｓi 等の４属元素を含まない金属電極上でも、
絶縁性の優れた酸化タンタル薄膜を形成することができ
る。<Operation of the Invention> According to the method of the present invention, since it is introduced into the film by the element ion implantation method for reducing or eliminating defects in the tantalum oxide thin film, even on a metal electrode containing no Group 4 element such as Si,
It is possible to form a tantalum oxide thin film having excellent insulating properties.
＜実施例＞ 第１図は、酸化タンタルを誘電膜とする積層型キャパシ
ターを備えた、ダイナミックランダムアクセスメモリの
セルの断面である。第２図にその形成工程を示す。<Example> FIG. 1 is a cross section of a cell of a dynamic random access memory provided with a multilayer capacitor having a dielectric film of tantalum oxide. FIG. 2 shows the forming process.
まず、フィルド酸化膜３が形成されたＳi 基板１上に通
常のＭＯＳデバイス製造工程を用いて、ゲート酸化膜を
介してゲート電極４を形成し、続いてゲート電極４の周
囲にサイドウォール５を形成し、それらをマスクとして
イオン注入法によりソース，ドレイン領域２を形成す
る。上記工程によりＳi 基板１にトランジスタ部を形成
する。その後ゲート電極４が形成されたＳi 基板１の表
面を被って絶縁膜６を形成し、その上にレジストを塗布
し、キャパシタ用のコンタクトホール等のパターニング
を行った後、エッチングによりコンタクトホールを開口
する。（第２図(a)）。First, the gate electrode 4 is formed via the gate oxide film on the Si substrate 1 on which the filled oxide film 3 is formed, using a normal MOS device manufacturing process, and then the sidewall 5 is formed around the gate electrode 4. Then, the source / drain regions 2 are formed by ion implantation using these as a mask. The transistor portion is formed on the Si substrate 1 by the above steps. After that, an insulating film 6 is formed so as to cover the surface of the Si substrate 1 on which the gate electrode 4 is formed, a resist is applied on the insulating film 6, and a contact hole for a capacitor is patterned, and then the contact hole is opened by etching. To do. (Fig. 2 (a)).
次にスパッタ法やＣＶＤ法を用いて、上記コンタクトホ
ールを通してＳi 基板１に被着し、且つ周辺の絶縁膜６
上に延在する金属薄膜を形成する。この金属薄膜は、キ
ャパシタの下部電極７となるが、従来、成分としてＳi
を含有する必要があり、ポリシリコンやタングステンシ
リサイドなどの材料に限られていた。本実施例の場合に
は、後の工程で温度的に耐えられるものであれば電極材
料を考慮する必要はなく、典型的な例としては、Ｍo,
Ｗ，Al等が使用可能である。この金属薄膜７を従来のホ
トリソグラフィ技術を用いて電極形状等にパターニング
したのち、ＣＶＤ法などで酸化タンタル８を形成する。
このとき成膜は比較的低温で処理することができるＣＶ
Ｄ，光ＣＶＤを利用する。成膜された酸化タンタル８上
から、Ｔi ，Ｓｉなどをイオン注入する。（第２図
(b)）このとき、典型的な注入条件は酸化タンタル膜厚2
50Åに対してＳi を注入する場合、加速電圧30ＫeＶ，
注入量2.5×1014cm-2である。しかし、この場合一般的
には加速電圧をＳi が酸化タンタル膜中へ到達する程度
の電圧，例えば２０〜８０ＫeＶにすれば良く、注入量
も、欠陥密度を上回る量、例えば5.0×1013〜1.0×1015
cm-2とすれば良い。Next, using a sputtering method or a CVD method, the Si substrate 1 is deposited through the contact holes and the insulating film 6 around the Si substrate 1 is deposited.
A metal thin film extending above is formed. This metal thin film serves as the lower electrode 7 of the capacitor, but conventionally, as a component, Si
Was required, and was limited to materials such as polysilicon and tungsten silicide. In the case of the present embodiment, it is not necessary to consider the electrode material as long as it can withstand temperature in the subsequent process, and as a typical example, Mo,
W, Al, etc. can be used. After patterning this metal thin film 7 into an electrode shape and the like by using a conventional photolithography technique, tantalum oxide 8 is formed by a CVD method or the like.
At this time, film formation can be performed at a relatively low temperature CV
D, photo CVD is used. Ti, Si, etc. are ion-implanted from above the deposited tantalum oxide film 8. (Fig. 2
(b)) At this time, the typical implantation condition is tantalum oxide film thickness 2
When Si is injected to 50Å, acceleration voltage is 30 KeV,
The injection volume is 2.5 × 10 14 cm -2 . However, in this case, generally, the accelerating voltage may be set to a voltage at which Si reaches the tantalum oxide film, for example, 20 to 80 KeV, and the amount of implantation is higher than the defect density, for example, 5.0 × 10 13 to 1.0. × 10 15
cm -2 is fine.
上記条件によって、膜中に４属元素を含んだ酸化タンタ
ルが得られるが、これらが欠陥と結合して安定な状態に
なるためには、適当な温度に一定時間以上保持すること
により再分布を生じさせる必要がある。さらに、この処
理を酸化性の雰囲気中で行うことによって残留する酸素
欠損を補うことができ、より特性向上を図ることが出来
る。この時の酸化剤は、単なる酸素でもよいが、紫外光
照射や放電、高周波誘導などの手法で活性化した強力な
酸化剤を用いれば、より有効である。この時の典型的な
処理条件は、基板加熱温度４００℃，酸素分圧１気圧、
紫外光照射強度５ｍＷ／cm2（185nm波長）、保持時間１
時間である。上記温度は３００〜６００℃で保持時間は
温度にもよるが３０分以上行えば良い。Under the above conditions, tantalum oxide containing a Group 4 element in the film can be obtained, but in order for these to be bound to defects and become stable, the redistribution can be achieved by holding at an appropriate temperature for a certain period of time or more. Need to occur. Further, by performing this treatment in an oxidizing atmosphere, residual oxygen vacancies can be compensated for, and the characteristics can be further improved. The oxidant at this time may be simple oxygen, but it is more effective if a strong oxidant activated by a method such as ultraviolet light irradiation, discharge, high frequency induction is used. Typical processing conditions at this time are a substrate heating temperature of 400 ° C., an oxygen partial pressure of 1 atm,
UV light irradiation intensity 5mW / cm 2 (185nm wavelength), holding time 1
It's time. The temperature is 300 to 600 ° C., and the holding time may be 30 minutes or longer, although it depends on the temperature.
上記処理を行った後、酸化タンタル薄膜上にキャパシタ
の上部電極となる金属薄膜９を形成し、キャパシタ部以
外の部分をその部分の膜下に存在する酸化タンタル薄膜
とともにエッチング除去し、キャパシタ部を得る。上記
工程によって誘導体としてすぐれた特性をもつ酸化タン
タル膜を得ることができる。After the above treatment, a metal thin film 9 to be an upper electrode of the capacitor is formed on the tantalum oxide thin film, and a portion other than the capacitor portion is removed by etching together with the tantalum oxide thin film existing under the portion film to remove the capacitor portion. obtain. Through the above steps, a tantalum oxide film having excellent characteristics as a derivative can be obtained.
＜発明の効果＞ 本発明による酸化タンタル薄膜中への４属元素のイオン
注入のプロセスを施すことにより、下部電極の材料の制
約なしに、優れた絶縁性のある高誘電薄膜を提供するこ
とが可能となり、極めて高密度のメモリ素子を実現する
ことが出来る。<Effects of the Invention> By subjecting the tantalum oxide thin film according to the present invention to ion implantation of a Group 4 element, it is possible to provide a high dielectric thin film having excellent insulating properties without restriction of the material of the lower electrode. It becomes possible to realize an extremely high-density memory device.
第１図は、酸化タンタルを用いた本発明による半導体装
置の断面図、第２図は、本発明の一実施例を示す工程を
説明する断面図である。 １……シリコン基板、２……Ｎ+拡散層、３……フィー
ルド酸化膜、４……ゲートメタル、５……サイドウォー
ル、６……層間絶縁膜、７……下部電極金属、８……酸
化タンタル、９……上部電極金属、１０……配線金属、
１１……保護絶縁膜FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention using tantalum oxide, and FIG. 2 is a cross-sectional view illustrating a process showing one embodiment of the present invention. 1 ... Silicon substrate, 2 ... N + diffusion layer, 3 ... Field oxide film, 4 ... Gate metal, 5 ... Sidewall, 6 ... Interlayer insulating film, 7 ... Lower electrode metal, 8 ... Tantalum oxide, 9 ... upper electrode metal, 10 ... wiring metal,
11 ... Protective insulation film
Claims (1)
温プロセスにより非晶質酸化タンタル薄膜を形成後、４
属元素をイオン注入法によって上記薄膜内に注入し、そ
の後、光エネルギーまたは高周波電界によって活性化し
た酸化剤を含む酸化雰囲気中で熱処理を行うことを特徴
とする、酸化タンタル薄膜の製造方法。1. A method for producing a tantalum oxide thin film, wherein after the amorphous tantalum oxide thin film is formed by a low temperature process, 4
A method for producing a tantalum oxide thin film, which comprises implanting a metal element into the above thin film by an ion implantation method, and then performing heat treatment in an oxidizing atmosphere containing an oxidant activated by light energy or a high frequency electric field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228872A JPH0656877B2 (en) | 1987-09-10 | 1987-09-10 | Method for producing tantalum oxide thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228872A JPH0656877B2 (en) | 1987-09-10 | 1987-09-10 | Method for producing tantalum oxide thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6471166A JPS6471166A (en) | 1989-03-16 |
| JPH0656877B2 true JPH0656877B2 (en) | 1994-07-27 |
Family
ID=16883190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62228872A Expired - Fee Related JPH0656877B2 (en) | 1987-09-10 | 1987-09-10 | Method for producing tantalum oxide thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656877B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225148A (en) * | 1988-03-04 | 1989-09-08 | Toshiba Corp | Thin film of dielectric and manufacture thereof |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
| US5320972A (en) * | 1993-01-07 | 1994-06-14 | Northern Telecom Limited | Method of forming a bipolar transistor |
| KR100319571B1 (en) | 1998-03-12 | 2002-01-09 | 루센트 테크놀러지스 인크 | Electronic Components With Doped Metal Oxide Dielectric Materials And A Process For Making Electronic Components With Doped Metal Oxide Dielectric Materials |
| KR100494322B1 (en) * | 1999-12-22 | 2005-06-10 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| JP3944367B2 (en) * | 2001-02-06 | 2007-07-11 | 松下電器産業株式会社 | Method for forming insulating film and method for manufacturing semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147177A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | A treatment method of tantaum oxide |
| JPS57167669A (en) * | 1981-03-27 | 1982-10-15 | Fujitsu Ltd | Capacitor and manufacture thereof |
-
1987
- 1987-09-10 JP JP62228872A patent/JPH0656877B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6471166A (en) | 1989-03-16 |
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