JPH0359534A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve the connection reliability of a common voltage supply terminal by providing a dummy terminal on the outside or both sides of the common voltage supply terminal. CONSTITUTION:Two pieces of dummy terminals 24, and one piece of dummy terminal 24 are provided on the outside of a common voltage supply terminal 22, and between a signal voltage supply terminal (drain signal terminal) 21 and the common voltage supply terminal 22, respectively. Also, an inspection pad 25 connected to the common voltage supply terminal 22 is provided. This inspection pad 25 utilizes a substrate discriminating substrate number formed simultaneously at the time of forming Cr for constituting, for instance, a gate electrode. In such a way, by providing the dummy terminal 24 on the outside of the common transparent picture element electrode 22, the connection reliability of the common voltage supply terminal 22 and an output terminal of tape automated bonding (TAB) is improved.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a liquid crystal display device, and particularly to the shape of a terminal portion for connecting a liquid crystal display panel and a peripheral circuit of a liquid crystal display module. [Prior Art] An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so compared to the so-called simple matrix method, which uses a 1-time division driving force method, the active method has better contrast, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT). Active matrix liquid crystal display devices using TPT are described in, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration," Nikkei Electronics, pp. 193-210, 1986.
It is known for being published by Nikkei McGraw-Hill on February 15th. [Problem to be solved by the invention] Conventionally, no consideration was given to the common voltage supply method during all-light inspection, and the signal supply terminal and the common voltage supply terminal provided almost adjacent to each other were short-circuited. The inspection prober must be brought into contact with the Moreover, for this reason, there is a problem in that the terminals at the left and right ends of the TAB, which have low reliability, become common voltage supply terminals. An object of the present invention is to improve the connection reliability of common voltage supply terminals. Another object of the present invention is to enable an inspection prober to easily come into contact with a common voltage supply terminal during an all-lights inspection. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] In order to solve the above problems, the liquid crystal display device of the present invention is characterized in that dummy terminals are provided outside or on both sides of the common voltage supply terminal. Further, the present invention is characterized in that a test pad connected to a common voltage supply terminal is provided. [Function] Since the dummy terminals are provided outside or on both sides of the common voltage supply terminal, the connection reliability of the common voltage supply terminal can be improved. Furthermore, since the testing pad connected to the common voltage supply terminal is provided, voltage can be easily supplied to the common voltage supply terminal without shorting the signal supply terminal during testing. [Example] Hereinafter, the configuration of the present invention will be described together with an example in which the present invention is applied to an active matrix color liquid crystal display device. Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the line 11B-IIB in FIG. 2A and the display panel. 2C is a cross-sectional view taken along the nc-nc line in FIG. 2A; FIG. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. (Pixel arrangement) As shown in Figure J2A, each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel is a thin film transistor TPT,
It includes a pixel electrode ITO1 and an additional capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in one row direction, and a plurality of video signal lines DL are arranged in the column direction. (Overall Structure of Panel Cross Section) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC. A color filter F is provided on the upper transparent glass substrate 5UBZ side.
A black matrix pattern BM for IL and light shielding is formed. For example, the lower transparent glass substrate 5UBl side is
1.1 It is constructed with a thickness of about 1 mm. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the liquid crystal sealing opening (
They are formed along the entire periphery of the transparent glass substrates/5UB1 and 5UB2 except for those (not shown). The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is at least at one location. The lower transparent glass substrate 5U is made of silver paste material SIL.
It is connected to the external lead wiring formed on the BI side. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Alignment films 0RII and 0RT2, transparent pixel electrode To, common transparent pixel electrode IT○, protective films PSVI and PSV2,
Each layer of the tIA9 film GI is formed inside the sealant SL. The polarizing plate POL has a lower transparent glass substrate 5UB
1. Formed on each outer surface of the upper transparent glass substrate 5UB2. The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film 0RII is formed on the protective film PSVI on the side of the lower transparent glass substrate 5UBI. On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) IrO2 and an upper alignment film RI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate 5UB1 side,
Each layer on the upper transparent glass substrate 5UB2 side is formed separately, and then the upper and lower transparent glass substrates 5UBI and 5UB2 are formed separately.
It is assembled by overlapping the two and sealing the liquid crystal LC between them. (Thin film transistor TPT> The thin film transistor TPT operates in such a way that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.Thin film transistor of each pixel TPT is 3 within a pixel.
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TPT2, and TPT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate insulating film Gr, i
It is composed of an amorphous Si semiconductor layer AS (intrinsic, not doped with conductivity type determining impurities), a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity of their threshold, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain. (Gate electrode GT> As shown in detail in FIG. 4 (a plan view depicting only the layers g1, g2, and AS in FIG. 2A), the gate electrode GT is connected vertically from the scanning signal line GL (FIG. 2A and The gate electrode GT is configured to protrude upward (in FIG. 4) (branched into a T-shape).The gate electrode GT is configured to protrude to the formation regions of the thin film transistors TPTI to TFT3, respectively. Thin film transistor TPT1~TF
The respective gate electrodes GT of T3 are integrally formed (as a common gate electrode) and are formed continuously to the scanning signal line OL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film GL is formed using, for example, a chromium (Cr) film formed by sputtering, and has a thickness of about 1000 [layers]. As shown in FIGS. 2A, 2B, and 4, this gate electrode GT is formed to be thicker than the semiconductor RAS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the substrate 5UBI, the opaque Cr gate electrode GT casts a shadow, and the backlight light does not shine on the semiconductor layer AS.
A conductive phenomenon, that is, deterioration of the off-characteristics of TPT due to light irradiation becomes less likely to occur. The original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SDZ (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel width. W
The depth length that determines the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm, is determined. Of course, the size of the gate electrode in this example is important. It is made larger than the original size mentioned above. Considering only the function of the gate and light shielding of the gate electrode GT, the gate electrode and its wiring GL may be integrally formed in a single layer, and in this case, Si is used as the opaque conductive material.
A1 containing A1. Pure AI. Also, A1 containing Pd can be selected. (Scanning Signal Line GLI> The scanning signal line GL is composed of a composite film consisting of a first conductive film d1 and a second conductive film g2 provided on the top of the first conductive film d1. g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g1 is
For example, aluminum formed by sputtering (A Q
) film with a thickness of about 2000 to 4000 [A]. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information). Furthermore, the scanning signal AiGL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal @GL has a gradual step shape on its side wall. (Gate insulating film GI> Absolute #L film GI is thin film transistor TPT1 to TFT3
It is used as a gate insulating film for each. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI uses, for example, a silicon nitride film formed by plasma CVD, and
The i-type semiconductor layer AS is formed to have a film thickness of about 6 (semiconductor layer AS). As shown in FIG. The semiconductor layer AS is made of an amorphous silicon film or a polycrystalline silicon film, and is formed to a thickness of approximately 1800 [A].
, N, following the formation of the gate insulating film GI. It is formed using the same plasma CVD equipment without being exposed to the outside from the equipment. Furthermore, P-doped N''RdO (Fig. 2B) for ohmic contact is formed continuously in the same way to a thickness of approximately 400 mm.Then, the lower substrate 5UBI is taken out from the CVD apparatus. Re,
By photoprocessing techniques, the N+ layers dO and iNAS are patterned into independent islands as shown in FIGS. 2A, 2B, and 4. As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS is located at the intersection of the scanning signal line GL and the video signal line DL (
The cross-over section) is also provided between the two. This intersection i-type semiconductor IAs receives the scanning signal &1 at the intersection.
It is configured to reduce short circuits between iGL and video signal line DL. (Source/drain electrodes SDI, SD2>The respective source electrodes SDI and drain electrodes SD2 of thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in FIGS. 2A, 2B, and 5 (layers d1 to d1 in FIG. 2A). As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer AS.
-first conductive film d from the lower layer side in contact with the type semiconductor layer dO
1, a second conductive film d2, and a third conductive film d3 are sequentially stacked. First conductive film d1 of source electrode SDI
, the second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [A] (in this example, 6
The film thickness is approximately 0.00 [person]. When forming a chromium film thicker, the stress increases, so 2000
The film thickness is formed within a range of about [λ]. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer do. The first conductive film di is formed of a high melting point metal (Mo, Ti, Ta, W) film and a high melting point metal silicide (M.Si2.TiSi2.TaSi, WSi,) film in addition to the chromium film. Good too. After patterning the first conductive film d1 by photo processing, the N+ layer do is removed using the same photo processing mask or using the first conductive film d1 as a mask. That is, the portion of the N+ layer dO remaining on the i-layer As except for the first conductive film d1 is removed by the self-alignment. At this time, the N'' layer do is etched so that its entire thickness is removed, so the i MAS is also slightly etched on its surface, but the extent can be controlled by the etching time. 2 conductive film d2 is formed by aluminum sputtering to a thickness of 3000 to 4000[lambda] (in this example, a film thickness of about 3000[lambda]).The aluminum film is less stressed than the chromium film. The second conductive film d2, which can be formed to be small and thick and configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL, may be made of other materials other than an aluminum film. Alternatively, it may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive. After patterning the second conductive film d2 using a photo processing technique, a third conductive film d3 is formed. The third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
in-Oxide ITO: consists of 1
Film thickness of 000 to Z000 [people] (in this example, 120
The film thickness is approximately 0 [A]. This third conductive film d3 constitutes the source electrode SDI, drain electrode SD2, and video signal line DL, and also constitutes the transparent pixel electrode ITOI.
is configured. First conductive film d1 of source electrode SD1, drain electrode SD
Each of the two first conductive films d1 extends further inward (into the channel region) than the upper second conductive film d2 and third conductive film d3. In other words, the first conductive film di in these parts is Nd
The structure is such that the gate length of the thin film transistor TPT can be defined independently of 2 and d3. As described above, the source electrode SD1 is the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N1 layer d
It is configured along a step corresponding to the sum of the film thickness of the i-type semiconductor layer AS and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI includes a first conductive film di formed along the step shape of the i-type semiconductor layer As, and a first conductive film d.
1, a second conductive film d2 is formed on the side connected to the transparent pixel electrode ITOI in a smaller size than that of the second conductive film d2, and a third conductive film connected to the first conductive film d1 exposed from the second conductive film. d3. Source electrode SDI
The second conductive film d2 cannot be formed thickly because the chromium film of the first conductive film d1 increases stress, and cannot overcome the step shape of the i-type semiconductor layer AS.
It is designed to overcome. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly,
This greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). The third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2. The second conductive film d2 is configured to be connected to the exposed first conductive film d1 by reducing its size. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. (Pixel electrode ITOI> The transparent pixel electrode IT○1 is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section.The transparent pixel electrode IT○1 is divided into a plurality of one pixel. It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the thin film transistors TPTI to TFT3.The transparent pixel electrodes E1 to E3 are each connected to the source electrode SDI of the thin film transistor TPT. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area.In this way, the thin film transistor TPT of one pixel is divided into a plurality of thin film transistors TFTK to TFT3. By connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPTI to TFT3, a divided part (for example, TF
Even if TI) becomes a point defect, it is no longer a point defect when looking at the entire pixel (TFT2 and TFT3 are not defective), so
The probability of point defects can be reduced, and defects can be made difficult to see. Further, by configuring each of the divided transparent pixel electrodes El to E3 of the pixel to have substantially the same area, each liquid crystal composed of each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode ITO2 Capacity (Cpix) can be made uniform. (Protective film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode IrO2. The protective film PSV1 is mainly formed to protect the thin film transistor TPT from heat etc. The protective film PSVI is made of a silicon oxide film or a silicon nitride film formed by plasma CVD, for example, and has a film resistance of 8000[
Formed with a film thickness of approximately A. (Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer AS used as a channel formation region. The pattern is as shown by the hatching in Fig. 6. Note that Fig. 6 is a plan view depicting only the ITOIli/ld3, the filter layer FIL, and the light shielding film BM in Fig. 2A.The light shielding film BM is For example, a film with a high shielding property against light is formed of an aluminum film, a chromium film, etc. In this example, the chromium film is formed by sputtering to a thickness of about 1300 [people]. The common semiconductor RAS is sandwiched between the upper and lower light-shielding films BM and the thick gate electrode GT, and that part is not exposed to external natural light or backlight light.The light-shielding film BM is as shown by the hatched part in FIG. The light shielding film BM is formed around the pixel, that is, it is formed in a grid pattern (black matrix), and the effective display area of one pixel is partitioned by this grid.Therefore, the outline of each pixel is defined by the light shielding film BM. The light shielding film BM has two functions: shielding the semiconductor layer As and serving as a black matrix.The backlight is attached to the 5UB2 side, and the 5UBI
can also be set to the wt detection side (externally exposed side). (Common electrode ITO2> The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common electrode IrO2. This common transparent pixel electrode ITO2 has a common voltage Vco
m is applied. Common voltage Vc
om is a low level opening voltage vdmin applied to the video signal line DL and a high level driving voltage Vd wax
It is the intermediate potential between (Color filter FIL> The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye.The color filter FIL has dots for each pixel at a position facing the pixels. (Fig. 7) is formed into a shape (Fig. 7) and is dyed separately (Fig. 7 depicts only the third conductive film fid3 and color filter layer FIL in Fig. 3, and each of the R, G, and B filters is colored separately. , 45', 135°, with cross hatches).The color filter FIL is formed thick so as to cover all of the pixel electrodes ITOI (El to E3) as shown in FIG. The BM is formed inside the periphery of the pixel electrode ITOI so as to overlap with the color filter FIL and the edge portion of the pixel electrode ITOI.The color filter FIL can be formed as follows.First, an upper transparent glass substrate is formed. A dyed base material is formed on the surface of 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology.After this, the dyed base material is dyed with red dye and fixed treatment is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing the same process. The protective film PSV2 prevents the dyes that have been used to dye the color filters FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin. (Pixel Arrangement) Each pixel of the liquid crystal display section is arranged as shown in FIGS. 3 and 7. As shown in , a plurality of pixel columns are arranged in the same column direction as the direction in which the scanning signal line GL extends, and constitute pixel columns Xi, X2°X3, X4, etc. Each pixel column X1, X2 .X3.X4
．． Each pixel of... is a thin film transistor TFTI~
The TFT 3 and the transparent pixel electrodes E1 to E3 are arranged in the same position. That is, odd pixel columns XI, X3 .・・・
・Each pixel is a thin film transistor TFTI-TFT
3 are arranged on the left side, and transparent pixel electrodes E1 to E3 are arranged on the right side.・・・
. . , adjacent even-numbered pixel columns in the row direction X2. X4.・・・
The pixels of each of the odd-numbered pixel columns Xi, X3 . . . . each pixel is made up of pixels that are symmetrically turned upside down with respect to the extending direction of the video signal line DL. That is, 1 pixel column X2. X4. In each pixel, thin film transistors TPT1 to TFT3 are arranged on the right side, and transparent pixel electrodes E1 to E3 are arranged on the left side. Then, pixel columns X 2 , X 4 . , . . . are arranged in pixel columns XI, X3 . . . are moved (shifted) by half a pixel interval in the column direction. In other words, the interval between each pixel in the pixel row X is set to 1.0 (1
, 0 pitch), the pixel row X of the primary stage has each pixel interval of 1.0, and the pixel row
The pixel interval (0.5 pitch) is off. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixels in the previous pixel column The pixels on which the same color filter is formed (for example, the pixel on which the red filter R of the pixel row becomes. Color filter FIL
The triangular arrangement structure of RGB can improve the mixing of each color, thereby improving the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Equivalent circuit of the entire display panel) An equivalent circuit of this liquid crystal display device is shown in FIG. X i G, X i + I G, ... are video signal lines DL connected to the pixels in which the green filter G is formed.
It is. XiB, Xi+IB, . . . are video signal lines DL connected to the pixels in which the blue filter B is formed. X x +I R, X x + 2 Rr, . . . are video signal lines DL connected to pixels in which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. As shown in FIGS. 3 and 7, Yi is Yi+1. Yi+2. Each of the pixel rows X2 .
X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL are connected to the vertical scanning circuit, a Cadd indicates an additional capacitance, and Vcom indicates a common voltage. (Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is a thin film transistor T.
It is bent into an L-shape so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to PT. As is clear from FIG. 2C, this superposition is such that each of the transparent pixel electrodes E1 to E3 is connected to one electrode PL.
2, and the adjacent scanning signal 1iAGL is applied to the other electrode PLI.
A storage capacitance element (electrostatic capacitance element) Cadd is configured. The dielectric film of this storage capacitor element Cadd is made of the same layer as the insulating film GI used as the gate insulating film of the thin film transistor TPT. As is clear from FIG. 4, the storage capacitor Cadd has a layer gl in a portion where the width of the IM g1 of the gate line GL is widened to reduce the probability of short circuit with the drain line. Similar to the source electrode SD1, a portion between the capacitor electrode line (gl) and each of the transparent pixel electrodes E1 to E3 that are overlapped to form the storage capacitor element Cadd is provided with a In order to prevent the transparent pixel electrode IT○1 from being disconnected, an island region made up of the first conductive film d1 and the second conductive film d2 is provided. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO1. (Equivalent circuit of additional capacitance Cadd and its operation) The equal magnified circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode 5DI and the source electrode 5DI. The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cp
ix is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode IT○2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film P.
Sv1, alignment film 0RII, and ○RI2. Vlc is a midpoint potential. The storage capacitor element Cadd works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TPT switches. This situation can be expressed by the formula ΔV lc= ((Cgs/ (Cgs+Cadd+C
pix)) XΔVg. Here, ΔVlc is ΔVg
represents the change in midpoint potential due to This change ΔVie
causes a DC component applied to the liquid crystal, but the retention capacity Ca
The larger dd is, the smaller its value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reduction of DC component applied to liquid crystal LC. It is possible to improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor IAS, the source/drain electrodes SD1. The overlapping area with SD2 increases, and therefore the parasitic capacitance Cgs increases, causing the opposite effect that the midpoint potential Vlc becomes more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix<Cadd<8・Cpix), superposition capacitance Cgs
8 to 32 times (8・Cgs<Cadd<32
・Set to a value of about Cgs). (Connection method of additional capacitance Cadd electrode line) As shown in FIG. ) Connect to IrO2. As shown in FIG. 2B, the common transparent pixel electrode IT○2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, part of the conductive layer (gl and g2) of this external lead wiring is constructed in the same manufacturing process as the scanning signal and IGL. As a result, the final stage capacitor electrode MOL can be easily connected to the common transparent pixel electrode ITO2. Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line GL at the final stage (first stage) may be connected to the scanning signal line GL at the first stage (last stage). Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. (DC cancellation by additional capacitance Cadd scanning signal) This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention. Diagram (time chart)
As shown in FIG. 3, by controlling the opening voltage of the scanning signal aDL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 10, ■i is the parking voltage of an arbitrary scanning signal mGL, and V i +1 is the driving voltage of the scanning signal IIXGL at the next stage. Vea is the scanning signal A
Low level opening voltage Vdm1n applied to IGL,
Vdd is a high-level opening voltage V d max applied to the scanning signal gGL. The voltage change amount ΔV to Δv4 of the midpoint potential vlc (see FIG. 9) at each time t=t1 to t4 is as follows. 1=1. :ΔV x = (Cgs/C)・V 2
1=12:△V,=+(Cgs/C)(V1+V2)-
(Cadd/C)・V 2 1=1. :ΔV,=-(Cgs/C)・V1+(Cad
d/C)・(V1+V2) 1=14:ΔV4=-(Cadd/C)・Vl,
Total pixel capacitance: C= Cg5 + Cpix +
add Here, if the oscillation voltage applied to the scanning signal line GL is sufficient (see below)

(See note), the DC voltage applied to the liquid crystal LC is ΔV, +ΔV4= (Cadd・V 2− Cgs−V
1)/C, so Cadd-V2=Cgs-
When Vl is set, the DC voltage applied to the liquid crystal LC is O. [Note] At times t□ and t2, the change in the scanning line Vi affects the midpoint potential Vlc, but during the period from t2 to t3, the midpoint potential Vlc is made the same potential as the video signal potential through the signal line Xi. (Enough writing of video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period).Therefore, the DC component applied to the liquid crystal is calculated based on the period t1.
~t can be almost ignored, and it is only necessary to consider the potential immediately after the TPT is turned off, that is, the influence during transients at times t3 and t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, in the DC cancellation method, the drop caused by the pull-in of the midpoint potential Vlc by one superimposed capacitor Cgs is pushed up by the dynamic voltage applied to the storage capacitor Cadd and the next stage scanning signal 8GL (capacitive electrode line), and the liquid crystal The DC component applied to the LC can be made extremely small. As a result,
The liquid crystal display device can improve the lifespan of the liquid crystal LC. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly. FIG. 11 is a partially cutaway plan view of the liquid crystal display module. 5 is an upper shield case, 6 is a lower shield case, 7 is a liquid crystal display window provided in the upper shield case 5, 1 is a liquid crystal display panel attached to the liquid crystal display window 7, and 19 is an FPC for inputting external signals. (Flexible printed wiring board), 8 is a positioning hole, 16 is a rivet, 15 is a hole for the rivet, and F is a recess provided in the shield case 5.6 for mounting the rivet. The two upper and lower shield cases 5.6 are combined and fixed by a plurality of rivets 16 and soldering. 2 is an opening IC for opening the liquid crystal display panel 1; 3 is a TAB (tape automated bonding) on which a turbulence IC 2 is mounted; 4 is a printed wiring board (P) on which the TAB 3 is mounted;
CB), 8 is the input terminal of the liquid crystal display panel l, and T
Connected to the output terminal of AB3. FIGS. 1A to 1D are plan views showing embodiments of the liquid crystal display device of the present invention, respectively. 5UB1 is a lower transparent glass substrate on which TPT etc. are formed, and 5UB2 is an upper transparent glass substrate on which color filters etc. are formed. The lower transparent glass substrate SUB is larger in size than the upper transparent glass substrate 5UB2, and each input terminal of the liquid crystal display panel is provided on the lower transparent glass substrate 5UBI around the upper transparent glass substrate 5UB2. On top of that, the T shown in Figure 11
The output terminal of AB is connected. 21 is a signal voltage supply terminal (drain signal terminal) connected to the gate line or drain line of each pixel, 22 is a common voltage supply terminal connected to the common transparent pixel electrode, and 23 is a terminal extraction of the common transparent pixel electrode. 24 is a dummy terminal, 25 is a test pad using the board number, 26 is a test pad provided separately from the board number, 27 is a power supply prober for testing all lights, and 28 is a cutting of the lower transparent glass board. 29 is a short wiring provided on the transparent glass plate before cutting, and 30 is a discharge portion. In the embodiment shown in FIG. 1A, two dummy terminals 24 are provided outside the common voltage supply terminal 22, and one dummy terminal 24 is provided between 2I and 22. Further, a test pad 25 connected to the common voltage supply terminal 22 is provided. This inspection pad 25 is formed at the same time as, for example, forming Cr constituting the gate electrode, and uses the substrate number for substrate identification. It may be formed using another conductive film. The embodiment shown in FIG. 1(B) is an example in which a test pad 26 is newly provided in addition to the board number. This test pad 2
6 is provided at the same time using, for example, an ITO film for forming a pixel electrode. Note that the test pad 26 may be provided using another conductive film such as a Cr film for forming a gate electrode. FIG. 1C shows how the two test power supply probers 27 are brought into contact with both the signal voltage supply terminal 21 and the test pad 26 to turn on all the pixels and perform the test. Through this inspection, gap unevenness, wire breakage, and T
It is possible to check PT, interlayer short circuit between gate line and drain line, etc. FIG. 1(D) is an example in which a short wiring 29 for preventing electrostatic breakdown of the gate insulating film is provided before cutting the lower transparent glass substrate SUB↓. For short wiring, the gate line and drain line may all be shorted, but in this state, all lights cannot be tested. Therefore, in the short wiring 29 of this embodiment,
A discharge section 30 was provided which consisted of a pattern (referred to as a lightning rod pattern) in which a gate line short-circuited, a drain line short-circuited, and a line connected to the test pad 25 were closely spaced apart from each other. Therefore, when large static electricity enters the wiring pattern during the manufacturing process, discharge occurs in the discharge portion 30, and electrostatic breakdown of the gate insulating film is prevented. In addition,
A line with the gate line shorted instead of the above lightning rod pattern,
A capacitance pattern may be provided in which a short-circuited drain line and a line connected to the test pad 25 are brought close to each other via an insulating film. In this embodiment, before the lower transparent glass substrate 5UB1 is cut, a full-light inspection is possible with the short wiring 29 present. That is, a common voltage is supplied to the test pad 25 using a test power supply prober,
A signal voltage is supplied to the short wiring 29. According to each of the embodiments described above, since the dummy terminal 24 is provided outside the common transparent pixel electrode 22, the common voltage is supplied. Further, since the test pads 25 and 26 are provided, the test power supply prober 27 can be easily brought into contact with the test pads 25 and 26, and a full-light test can be performed without shorting with the signal voltage supply terminal 21. Furthermore, if a dummy terminal 24 is provided between the signal voltage supply terminal 21 and the common voltage supply terminal 22, the distance between them will increase, so even if the test pad 25.
Even if 26 is not provided, an inspection can be performed by bringing the inspection power supply prober 27 into contact with the signal voltage supply terminal 21 without causing a short circuit. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, the number of dummy terminals 24, the number of inspection bands 2526
The shape of the test pad 2 or which conductive film is used to
5.26 is not limited to the above embodiment, and various configurations may be used. Furthermore, although this embodiment shows an inverted staggered structure in which gate electrode formation → gate insulating film formation → semiconductor layer formation → source/drain electrode formation, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be. [Effects of the Invention] As explained above, in the liquid crystal display device of the present invention, since the dummy terminals are provided outside or on both sides of the common voltage supply terminal, the connection reliability of the common voltage supply terminal can be improved. Since the test pad connected to the common voltage supply terminal is provided, the lighting test can be easily performed without shorting with the signal voltage supply terminal.

[Brief explanation of drawings]

1A to 1D are plan views showing embodiments of the liquid crystal display device of the present invention, and FIG. 2A is a plan view of an active matrix color liquid crystal display device, which is Embodiment I of the present invention. FIG. 2B is a plan view of a main part showing one pixel of the liquid crystal display section. FIG. 2B is a cross-sectional view of the portion taken along the nB-JIB cutting line in FIG.
FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged; FIGS. 7 is a plan view depicting only a predetermined layer of the pixel shown in FIG. FIG. 9 is an equivalent circuit diagram showing the liquid crystal display section of a matrix type color liquid crystal display device.
FIG. 10 is an equivalent circuit diagram of the pixel shown in FIG. A. FIG. 10 is a time chart showing the opening voltage of the scanning signal line using the DC cancellation method. FIG. 11 is a partially cutaway plan view of the liquid crystal display module. In the figure, 21...Terminal for signal voltage supply, 22...Terminal for common voltage supply, 23...Terminal extraction part of common transparent pixel electrode, 24...Dummy terminal, 25...Using board number common voltage supply terminal inspection pad, 26...
Common voltage supply terminal inspection pad, 27...Power supply prober for lighting inspection, SUB...Transparent glass substrate, GL/
...Scanning signal line, DL...Video signal line, GI...Insulating film, GT...Gate electrode, AS...I-type semiconductor layer, SD...Source electrode or drain electrode, psv...
・Protective film, LS...light shielding film, LC...liquid crystal, TPT
...Thin film transistor, ITO...Transparent electrode, go
d... Conductive film, Cadd... Holding capacitor element, Cgs
...superposition capacitance, Cpix...liquid crystal capacitance (
Numerical subscripts after alphabetic characters are omitted). Figure 3 Figure 6 Figure 9 Figure 10 l t2 t, 5 t4 Shadow 11 Figure 7 ---- Award display

Claims (1)

[Scope of Claims] 1. A liquid crystal display device characterized in that dummy terminals are provided outside or on both sides of a common voltage supply terminal. 2. A liquid crystal display device comprising a test pad connected to a common voltage supply terminal.