JPH0359461B2 - - Google Patents

Info

Publication number
JPH0359461B2
JPH0359461B2 JP59176021A JP17602184A JPH0359461B2 JP H0359461 B2 JPH0359461 B2 JP H0359461B2 JP 59176021 A JP59176021 A JP 59176021A JP 17602184 A JP17602184 A JP 17602184A JP H0359461 B2 JPH0359461 B2 JP H0359461B2
Authority
JP
Japan
Prior art keywords
processing
processing request
sequential
requests
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59176021A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6154554A (ja
Inventor
Makoto Sekine
Shigeaki Okuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59176021A priority Critical patent/JPS6154554A/ja
Publication of JPS6154554A publication Critical patent/JPS6154554A/ja
Publication of JPH0359461B2 publication Critical patent/JPH0359461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP59176021A 1984-08-24 1984-08-24 逐次制御回路 Granted JPS6154554A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59176021A JPS6154554A (ja) 1984-08-24 1984-08-24 逐次制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59176021A JPS6154554A (ja) 1984-08-24 1984-08-24 逐次制御回路

Publications (2)

Publication Number Publication Date
JPS6154554A JPS6154554A (ja) 1986-03-18
JPH0359461B2 true JPH0359461B2 (cs) 1991-09-10

Family

ID=16006334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59176021A Granted JPS6154554A (ja) 1984-08-24 1984-08-24 逐次制御回路

Country Status (1)

Country Link
JP (1) JPS6154554A (cs)

Also Published As

Publication number Publication date
JPS6154554A (ja) 1986-03-18

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees