JPH0353650B2 - - Google Patents

Info

Publication number
JPH0353650B2
JPH0353650B2 JP62024589A JP2458987A JPH0353650B2 JP H0353650 B2 JPH0353650 B2 JP H0353650B2 JP 62024589 A JP62024589 A JP 62024589A JP 2458987 A JP2458987 A JP 2458987A JP H0353650 B2 JPH0353650 B2 JP H0353650B2
Authority
JP
Japan
Prior art keywords
data
circuit
output
input
subtraction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62024589A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62187933A (ja
Inventor
Yoshimune Hagiwara
Shizuo Sugyama
Shigemichi Maeda
Osamu Yumoto
Takashi Akazawa
Masahito Kobayashi
Yasuhiro Kita
Juzo Kida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP62024589A priority Critical patent/JPS62187933A/ja
Publication of JPS62187933A publication Critical patent/JPS62187933A/ja
Publication of JPH0353650B2 publication Critical patent/JPH0353650B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
JP62024589A 1987-02-06 1987-02-06 加減算装置 Granted JPS62187933A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62024589A JPS62187933A (ja) 1987-02-06 1987-02-06 加減算装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62024589A JPS62187933A (ja) 1987-02-06 1987-02-06 加減算装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP55152051A Division JPS5776634A (en) 1980-10-31 1980-10-31 Digital signal processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP18737389A Division JPH02224019A (ja) 1989-07-21 1989-07-21 加減算装置

Publications (2)

Publication Number Publication Date
JPS62187933A JPS62187933A (ja) 1987-08-17
JPH0353650B2 true JPH0353650B2 (enrdf_load_stackoverflow) 1991-08-15

Family

ID=12142342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62024589A Granted JPS62187933A (ja) 1987-02-06 1987-02-06 加減算装置

Country Status (1)

Country Link
JP (1) JPS62187933A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821883B2 (ja) * 1988-07-20 1996-03-04 松下電器産業株式会社 エコーキャンセラ
US4994996A (en) * 1989-02-03 1991-02-19 Digital Equipment Corporation Pipelined floating point adder for digital computer
JP3029812B2 (ja) * 1997-06-03 2000-04-10 株式会社ジャストシステム 演算エラー復旧方法およびその装置，並びにその方法をコンピュータに実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体
JP4575609B2 (ja) * 2001-03-13 2010-11-04 旭化成エレクトロニクス株式会社 データ変換装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346577B2 (enrdf_load_stackoverflow) * 1974-03-25 1978-12-14
JPS53103335A (en) * 1977-02-21 1978-09-08 Fujitsu Ltd Logic arithmetic circuit
JPS6051728B2 (ja) * 1978-06-06 1985-11-15 富士通株式会社 高速演算処理方式

Also Published As

Publication number Publication date
JPS62187933A (ja) 1987-08-17

Similar Documents

Publication Publication Date Title
JPS6242296B2 (enrdf_load_stackoverflow)
US6009451A (en) Method for generating barrel shifter result flags directly from input data
JP3110288B2 (ja) 指数対数変換回路
US5457805A (en) Microcomputer enabling high speed execution of product-sum operation
JPH08234962A (ja) ２４ビットおよび１６ビット算術演算の双方を実行するための装置および方法
JPH04127364A (ja) 積和算器
JP3665409B2 (ja) 強化されたデジタル信号プロセッサの方法および装置
JPH0353650B2 (enrdf_load_stackoverflow)
US5402368A (en) Computing unit and digital signal processor using the same
US5822557A (en) Pipelined data processing device having improved hardware control over an arithmetic operations unit
JPH026089B2 (enrdf_load_stackoverflow)
Thompson et al. An LSI digital signal processor
JPH0357488B2 (enrdf_load_stackoverflow)
JPH0357486B2 (enrdf_load_stackoverflow)
JPH0357487B2 (enrdf_load_stackoverflow)
JPS645500B2 (enrdf_load_stackoverflow)
US6792442B1 (en) Signal processor and product-sum operating device for use therein with rounding function
JPS63153636A (ja) 情報処理装置
JPH0225924A (ja) 浮動小数点演算処理装置
JPH0784763A (ja) 乗算回路
JPH01240961A (ja) Ｄｍａ転送方式
JPH01266668A (ja) 情報処理装置
JPS62285137A (ja) デイジタル信号処理プロセツサ
JPS59186070A (ja) 高速信号処理装置
JPH03226831A (ja) ２↑ｎ倍演算回路